JPH03280533A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the adhesion of a conductor layer to a connection hole and to contrive to improve the reliability of a semiconductor device by a method wherein a second conductor layer having a good adhesion to both of the conductor layer and an insulating film is made to interpose in the boundary part between the insulating film on the sidewall of the connection hole and the conductor layer, which is formed in the interior of the connection hole. CONSTITUTION:A damage layer is formed on the surface of an Al alloy film on the bottom of an interlayer connection hole 4, a substrate 1 in such a state is put in a vacuum container and the damage layer on the surface of the Al alloy film and a natural oxide film are etched away using BCl3 gas. Subsequently, a tungsten silicide film 5 is deposited under a vacuum state in the interior of the substrate subsequent to a treatment. After this, the tungsten silicide film is made to remain on the sidewall of a silicon oxide film, which is used as an interlayer insulating film, using sulfur hexafluoride gas as etching gas. Here, the substrate is transferred without breaking the vacuum state and a tungsten film 6 is buried in the hole 4. Lastly, an Al alloy (Al-Si) film 7 is again formed, this Al alloy film is patterned and a second layer wiring pattern is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to embedding a conductor layer into a connection hole formed in an insulating film.

(Prior Art) High integration of semiconductor devices is brought about by miniaturization of elements. For example, VLSIs such as IMDRAM and 256KSRAM are 1 to 1. ．． It is manufactured using a design standard of 2 μm, and is now being manufactured using a submicron design standard for the purpose of higher integration.

However, the miniaturization of elements accompanying this high degree of integration is
is becoming increasingly difficult to manufacture. For example, in electrode wiring technology, connection holes become narrower and deeper, so that sufficient coverage cannot be obtained with aluminum alloy wiring formed by the conventional sputtering method. This is because the film thickness becomes thinner at the bottom of the side wall of the connection hole due to the shadowing effect. The overhang shape of aluminum wiring as shown in 2 can also cause so-called "slip" when forming an insulating film on aluminum wiring. In this way, as elements become smaller, a problem arises in that the reliability of aluminum wiring formed by sputtering decreases.

Therefore, in recent years, a method has been proposed in which a conductive film is formed by low pressure chemical vapor deposition (LPCVD).

Among them, it is known that a high melting point metal thin film ζ such as tungsten is deposited only on the semiconductor or conductor film on the substrate surface under certain deposition conditions. The so-called selective CVD method, which deposits only on the semiconductor or conductor film and not on the insulating film, is attracting attention as a method to solve the problem caused by the large aspect ratio of the contact hole. has been done.

For example, as shown in FIG. 5, a contact hole (not shown) formed in a silicon oxide film (not shown) as an interlayer insulating film is connected to a diffusion layer (not shown) on the surface of a silicon substrate 1. A silicon oxide film 3 is further formed as an interlayer insulating film by a plasma CVD method on the first aluminum alloy layer 2 formed so as to be in contact with the first aluminum alloy layer 2, and a selective CVD method is applied to a contact hole 4 formed in the silicon oxide film 3. A structure is often used in which a tungsten film 6 is formed and buried, and aluminum wiring 7 and the like are formed on top of the tungsten film 6. In this case, the adhesion between the oxide film and the tungsten film 6 is poor, and there may be gaps when viewed microscopically.

In such a case, if a pattern shift occurs due to the photolithography used for patterning, the etching gas will quickly diffuse through this gap, and in extreme cases, a phenomenon such as etching the first aluminum layer 2 may occur. be.

In addition, since chlorine-based gas is often used for etching aluminum, residual fluorine from metal fluorides such as tungsten hexafluoride gas used in forming the tungsten film may be present on the first aluminum layer. There was a problem in that the coexistence of fluorine and chlorine could cause corrosion of the first aluminum layer.

In addition, when forming a wiring pattern after embedding a conductor layer in the (interlayer) contact hole in this way, it is also necessary to bury the conductor layer directly into the interlayer contact hole so that it extends onto the interlayer insulating film as well as burying the interlayer contact hole. Even when embedding a tungsten thin film or the like, there is a problem in that the adhesion between the insulating film and the tungsten film is poor, and the tungsten thin film is only in close contact with the bottom of the connection hole, making it easy to peel off.

(Problems to be Solved by the Invention) In this way, not only the selective CVD method but also the CVD (Blanket C
When a metal film is formed by a CVD method, such as CVD of VD), A1 film, or Cu film, the adhesion between the side wall of a connection hole and a conductor layer such as a buried conductor layer becomes a problem.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor device having a highly reliable contact structure with high adhesion to the side wall of a connection hole.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the present invention, a first layer made of a semiconductor or a conductor formed on the surface of a base substrate, a first layer formed on the surface of a base substrate,
a connection hole formed in an insulating film covering the surface of the layer; an intermediate layer formed of a conductor layer formed to cover at least a part of the side wall of the connection hole; and an intermediate layer formed embedded in the connection hole. and a second layer made of a conductor.

(Function) In other words, since a conductor layer with good adhesion to both the second layer, which is the buried layer, and the insulating film is interposed as an intermediate layer, the conductor layer with good adhesion to the connection hole is provided. It becomes possible to form a second layer.

For this reason, even if pattern misalignment occurs due to photolithography used in patterning the wiring pattern formed on the second layer, there is no gap in the connection hole, and the etching gas will diffuse into the underlying first layer. There is no such thing as etching.

Furthermore, the membrane does not cause defects such as cracks.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Example 1 First, a desired element region (not shown) is formed on the surface of a silicon substrate 1 with element isolation, and then a silicon oxide film (not shown) is formed to form a contact hole (not shown). ), and on this upper layer, an aluminum alloy (AI-5
i) Form a film 2, pattern this aluminum alloy film by ordinary photolithography and reactive ion etching (RIE), and apply silicon oxide with a thickness of 1.4 μm as an interlayer insulating film on top of this by CVD. After forming the film 3, as shown in FIG. 1(a), interlayer connection holes 4 are formed by photolithography and reactive ion etching.

The surface of the aluminum alloy at the bottom of the interlayer connection hole 4 formed in this manner incorporates fluorine, carbon, etc. of the etching gas when the hole is opened by reactive ion etching, and a so-called damaged layer is formed. Further, the surface layer is oxidized by oxygen and water vapor in the air to form an oxide film.

Therefore, in order to remove the oxide film and the damaged layer, the substrate 1 in such a state is placed in a vacuum container and exposed to BCl3.
Gas flow rate 10 cc/sin, pressure 2X 10
Torr, substrate temperature 20℃, high frequency human power 200
WBit, substrate bias - 500v1 processing time 1
Etching was performed under the conditions of 20S, and the substrate after this treatment was etched at a vacuum degree of IX 10-6 Torr without breaking the vacuum.
Heat at 400°C for 1 minute using the following settings. At this time, the surface of the first layer aluminum alloy film is etched at a rate of 120 to 15Q8/win, and the damaged layer and natural oxide film on the surface of the aluminum alloy film are etched away. In this state, atoms such as boron and chlorine remain on the surface. Therefore, by performing the heat treatment, the atoms of boron, chlorine, etc. that have been adsorbed and bonded to the surface of the aluminum alloy film are sublimated or evaporated, and a clean aluminum alloy film surface can be obtained.

Subsequently, the substrate after this treatment is subjected to CV CV without breaking the vacuum.
Transfer to a vacuum device for performing D, substrate temperature 350°C, WF6 flow rate 10 cc/min, S i H4 flow rate] 00 cc
Tungsten silicide 5 is deposited at a deposition pressure of 50 wTorr and a deposition time of 60 seconds (FIG. 1(b)).

After this, sulfur hexafluoride (SF6) is used as an etching gas.
The entire surface was etched using the RIE method, as shown in Figure 1 (
As shown in c), a tungsten silicide film is left on the sidewall of the silicon oxide film as an interlayer insulating film. If the substrate is transported and etched without breaking the vacuum, it is further transported without breaking the vacuum and a tungsten film is formed. When etching is performed using other equipment, or when a so-called resist etch-back method is used that combines resist and random etching, the oxide film is removed using BC13 gas again, and then the oxide film is removed without breaking the vacuum. The substrate is transferred to a vacuum device that performs CVD, and a tungsten film is formed. This tungsten deposition is
Substrate temperature 300℃, WF6 flow rate 10cc/1n, S
i H4 flow rate 60cc/ll1in, deposition pressure 10w
Torr and deposition time of 60 seconds using the selective CVD method, as shown in FIG. 1(d), the deposition rate was 0.
．． The tungsten film 6 is connected to the interlayer connection hole 4 at a thickness of 2 μm/n+in.
Embed inside.

Finally, as shown in Figure 1(e), an aluminum alloy (Al-
5i) A film 7 is formed, and this aluminum alloy film is patterned by ordinary photolithography and reactive ion etching (RIE) to obtain a second layer wiring pattern.

According to this method, since the tungsten silicide film 5 as an intermediate layer is interposed between the tungsten film 6 as a buried layer and the silicon oxide film 3 on the side wall of the interlayer connection hole 4, good adhesion can be achieved. It becomes possible to form highly reliable multilayer wiring.

Furthermore, even if the pattern is removed by photolithography used in patterning the aluminum alloy film as the second layer wiring pattern, there is no gap in the connection hole, so the etching gas may diffuse and etch the underlying aluminum alloy film. Never.

In the above embodiments, the CVD method was used to form the intermediate layer, but the method is not limited to the CVD method, and a sputtering method, a thermal oxidation method, etc. may also be used. Further, it is desirable that this intermediate layer be formed so as to cover the entire side wall of the interlayer connection hole, but even a small amount has an effect, and the thickness and depth can be changed as appropriate by selecting etching conditions.

In addition, the material of the intermediate layer must have good adhesion to both the interlayer insulating film and the buried conductor layer, and when the intermediate layer itself is etched, the shape of the underlying conductor layer will be significantly damaged. Other materials such as aluminum or its alloy, titanium nitride, titanium tungsten alloy, amorphous silicon, etc. may also be used.

Further, in the above embodiment, an aluminum alloy film was used as the underlying first conductor layer, but in addition to a metal film such as a thin copper film, p
Other conductor layers such as silicon layers such as 10 diffusion layers and n10 diffusion layers, polycrystalline silicon layers into which impurities are introduced, silicides such as molybdenum silicide, titanium silicide, and tungsten silicide, and nitrides such as titanium nitride. It may be used on two or more types of substrates at the same time.

Furthermore, the third conductor layer is not limited to an aluminum alloy film.

In addition, in the above embodiment, when embedding the conductor layer in the interlayer contact hole, a tungsten film was selectively formed in the interlayer contact hole by selective CVD method, but it was not deposited on the entire surface (blanket), and etchback was performed. You can do it as well.

Furthermore, although a silicon oxide film was used as the interlayer insulating film, silicon nitride (S) is not limited to the silicon oxide film.
It is also applicable to cases where other insulating films such as IN) are used.

Furthermore, in the above embodiment, the wiring pattern is formed by embedding a conductor layer in the interlayer connection hole, and then depositing and patterning another conductor film. Make it longer,
It can also be applied to cases in which tungsten is formed so as to fill interlayer connection holes and extend onto an interlayer insulating film (a so-called blanket), and to directly pattern tungsten and use it as a wiring pattern.

Example 2 As an example of this, a second embodiment of the present invention will be described.

As shown in FIG. 1(e), the formation is performed in exactly the same manner as in the first embodiment up to the step of leaving the tungsten silicide film 5 on the sidewall of the silicon oxide film 3 as an interlayer insulating film (see FIG. 2). (a)).

After this, the substrate after this treatment is subjected to CV CV without breaking the vacuum.
Transfer to a vacuum device for performing D, substrate temperature 350°C, WF6 flow rate 20 cc/win, S i H4 flow rate 12 cc/win.
A tungsten film 16 is deposited on the entire surface of the substrate using the CVD method under the conditions of 1.Win and a deposition pressure of 20 mTorr (FIG. 2(b)).

Finally, as shown in FIG. 2(c), this tungsten film 16 is patterned by ordinary photolithography and reactive ion etching (RIE).
A layer wiring pattern can be obtained.

According to this method, the tungsten film 16 as the second layer wiring pattern and the silicon oxide film 3 on the side wall of the interlayer connection hole 4 are combined.
Since the tungsten silicide film 5 as an intermediate layer is interposed between the tungsten silicide film 5 and the tungsten silicide film 5, it is possible to obtain a wiring pattern that has good adhesion not only to the bottom of the interlayer connection hole but also to the sidewall, which makes it difficult to peel off and increases reliability. It becomes possible to form multilayer wiring with high resistance.

In this embodiment as well, as in the case of the first embodiment, changes can be made as appropriate without departing from the spirit of the present invention.

Example 3 Next, a third embodiment of the present invention will be described.

In the second example, for connection holes hl and h2 with different depths,
A method of simultaneously embedding a conductor layer using a selective CVD method will be described.

First, as shown in FIG. 3(a), a desired element region (not shown) is placed on the surface of the silicon substrate 11 where the elements have been isolated.
After forming an insulating film 12 such as a PSG film and planarizing it, a first connection hole ht is formed so as to contact the wiring pattern 13 made of a polycrystalline silicon film. n1 diffusion layer 1 on the surface of silicon substrate 11
The second connecting hole h2 is formed so deep as to reach 4.

After this, as shown in FIG. 3(b), surface treatment is performed using the same method as used in Example 1, and the damaged layer and natural oxide film on the surface of the substrate and the surface of the wiring pattern 13 are etched away. After obtaining a clean surface, the processed substrate was transferred to a vacuum device for CVD without breaking the vacuum, and the substrate temperature was 350°C and the WF6 flow rate was 10cc/si.
Tungsten silicide 15 is deposited at a SiH4 flow rate of 100 cc/n+in and a deposition pressure of 501 Torr.

Thereafter, the entire surface is etched by RIE using SF6 as etching gas, leaving a tungsten silicide film on the sidewalls of the silicon oxide film serving as an interlayer insulating film, as shown in FIG. 3(c). At this time, the etching conditions are controlled to leave the tungsten silicide film 15 in a shape that covers the entire side wall of the connection hole.

Subsequently, the substrate after this treatment was transferred to a vacuum device for CVD, and the substrate temperature was 300°C and the WF6 flow rate was 10cc/win.
SS i H4 flow rate 6 cc/sin, deposition pressure 10m
Tungsten is deposited using the selective CVD method under Torr conditions, and the tungsten film 16 is embedded in the first and second connection holes h1 and h2, as shown in FIG. 3(d).

Here, tungsten silicide 15 as an intermediate layer
is present on the side wall of the contact hole, so during selective CVD, film growth occurs not only from the substrate surface and wiring pattern 13 at the bottom of the contact hole, but also from this tungsten silicide 15, so that it depends on the depth of the contact hole. This makes it possible to obtain a very good embedding shape.

In this way, the tungsten film 16 can be satisfactorily buried in the first and second connection holes h1 and h2, which have greatly different depths.

Finally, as shown in Figure 3(e), aluminum alloy (AI-
5i) Film] 7 is formed, and this aluminum alloy film is patterned by ordinary photolithography and reactive ion etching (RIE) to obtain a second layer wiring pattern.

According to this method, since the tungsten silicide film 15 as an intermediate layer is interposed between the tungsten film 16 as a buried layer and the PSG film 12 on the side wall of the interlayer connection hole hl h2, good adhesion can be achieved. It becomes possible to form highly reliable multilayer wiring.

For comparison, directly select C without any intermediate layer formation.
FIG. 4 shows the growth results when a tungsten film was grown in the connection hole by the VD method.

In this case, during selective CVD, the film grows only from the substrate surface at the bottom of the connection hole and the wiring pattern 13;
Shallow connection holes can be filled, but deep grooves cannot be filled at the same time.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention, the boundary between the insulating film on the side wall of the connection hole and the conductor layer formed inside the contact hole has adhesiveness to both the conductor layer and the insulating film. Since the second conductor layer with good adhesion is interposed, it is possible to form a conductor layer with good adhesion to the connection hole, and reliability is improved.

[Brief explanation of the drawing]

1(a) to 1(e) are diagrams showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention, and FIG. 2(a) to FIG. 3(a) to 3(e) are diagrams showing the manufacturing process of the semiconductor device of the third embodiment of the present invention,
FIGS. 4 and 5 are diagrams showing a semiconductor device formed by a conventional method. 1. Silicon substrate, 2. Aluminum alloy (AI-
5i) Film (first wiring layer) 3... Silicon oxide film (
4. Interlayer connection hole, 5. Tungsten silicide film (intermediate layer), 6. Tungsten film (buried layer), 7. Aluminum alloy (AI-5i) film (second wiring) layer), 11... silicon substrate, 12...
・Aluminum alloy (AI-3i) film (first wiring layer)
, 13... silicon oxide film (interlayer insulating film), 14...
・Diffusion layer, hl h2... Connection hole, 15... Tungsten silicide film (intermediate layer), 16... Tungsten film, 17... Aluminum alloy (AI-3i) film (
second wiring layer). Figure ξ Figure 3 (No. 1) Figure (No. 2)

Claims (1)

[Scope of Claims] A first layer made of a semiconductor or a conductor formed on the surface of the base substrate, a connection hole formed in an insulating film covering the surface of the base substrate and the first layer, and at least the connection hole. A semiconductor comprising: an intermediate layer made of a conductor layer formed to cover a part of the side wall of the hole; and a second layer made of a conductor embedded in the connection hole. Device.