JPH03280539A - Fabrication method for semiconductor device with insulation layer - Google Patents

Fabrication method for semiconductor device with insulation layer

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Publication number
JPH03280539A
JPH03280539A JP8196790A JP8196790A JPH03280539A JP H03280539 A JPH03280539 A JP H03280539A JP 8196790 A JP8196790 A JP 8196790A JP 8196790 A JP8196790 A JP 8196790A JP H03280539 A JPH03280539 A JP H03280539A
Authority
JP
Japan
Prior art keywords
insulating film
substrate
film
bias
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8196790A
Other languages
Japanese (ja)
Other versions
JP2803304B2 (en
Inventor
Mitsuo Sasaki
光夫 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
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Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2081967A priority Critical patent/JP2803304B2/en
Publication of JPH03280539A publication Critical patent/JPH03280539A/en
Application granted granted Critical
Publication of JP2803304B2 publication Critical patent/JP2803304B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To form an insulator film with excellent step coverage without damaging a substrate surface and step areas by executing multiple process steps which vary the high-frequency bias output applied to the substrate, the presence of Ar gas and other gases, and other conditions of a process which uses an ECR plasma CVD method. CONSTITUTION:An interconnection 22 is formed on the surface of a silicon substrate 21 and over this a lower layer protection oxide layer 23 is formed. In order to prevent damage, hillocks, or stress migration on the surface of interconnection 22, this sealing protection oxide layer 23 is formed by either applying no RF bias or low-output RF bias to the silicon substrate 21. Furthermore, this layer is made as thin as possible to shorten the later planarization step. Next, high-output RF bias is applied to the silicon substrate 21 and a high-coverage oxide film 24 with enhanced step coverage is formed to increase film thickness. Finally, Ar and He gases are introduced into a reaction chamber 6, sputter etching is performed, and a planar oxide layer 25 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野) 本発明は、絶縁膜を備えた半導体装置の製造方法に関し
、特に、ECRプラズマCVD法により基板の段差部、
例えば電極、配線等の上に絶a膜を形成する技術に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device equipped with an insulating film, and in particular, the present invention relates to a method for manufacturing a semiconductor device equipped with an insulating film.
For example, it relates to a technique for forming an amorphous film on electrodes, wiring, etc.

[従来の技術) 半導体集積回路の眉間絶縁膜やパッシベーション膜とし
ては、通常、熱CVD法や高周波プラズマCVD法によ
り形成された酸化膜、窒化膜等が用いられている。しか
し、近年、半導体装置の集積化及び高密度化が進み、配
線間隔、配線幅等の構造寸法がサブミクロン領域に移行
するに伴って絶縁膜の高品質化が要求されるようになり
、上記の成膜方法以外の手法が種々試みられている。そ
のうちの1つとして、低温成膜可能で耐酸性、緻密性に
優れた絶縁膜を形成できるECR(1を子サイクロトロ
ン共鳴)プラズマCVD法が開発されている。
[Prior Art] As a glabellar insulating film or a passivation film of a semiconductor integrated circuit, an oxide film, a nitride film, or the like formed by a thermal CVD method or a high-frequency plasma CVD method is usually used. However, in recent years, as semiconductor devices have become more integrated and denser, and structural dimensions such as interconnect spacing and interconnect width have moved to the submicron range, higher quality insulating films have been required. Various methods other than the film forming method have been attempted. As one of these methods, an ECR (echo cyclotron resonance) plasma CVD method has been developed, which can be formed at a low temperature and can form an insulating film with excellent acid resistance and density.

このECRプラズマCVD法は、所定強度の磁場中にガ
スを導入し、ここに磁場強度に対応した周波数のマイク
ロ波を入射することによって該マイクロ波のエネルギー
を共鳴吸収させ、これにより高密度に生成されたプラズ
マを、反応ガスと伴に基板上に導入して成膜するもので
ある。
In this ECR plasma CVD method, a gas is introduced into a magnetic field of a predetermined strength, and by injecting microwaves with a frequency corresponding to the magnetic field strength, the energy of the microwaves is resonantly absorbed, thereby producing high-density gas. The resulting plasma is introduced onto a substrate together with a reactive gas to form a film.

ここで、基板上の段差(例えば、基板上に形成された電
極、配線等による凹凸)の上に絶縁膜を形成する場合に
は、絶縁特性を向上させ、或いは多層構造を形成可能と
するために、平坦化処理を施す必要がある。この平坦化
処理を不要とするために、絶縁膜の成膜時に平坦化を達
成する方法として、基板に高周波バイアスを印加し、基
板の自己バイアス効果によってエツチングとデイポジシ
ョンを同時に行なうバイアススパッタリング法が知られ
ている。この高周波バイアスの印加は、ECRプラズマ
CVD法においても施すことが可能であり、これにより
、絶縁膜の段差被覆性の改善が期待されている。
Here, when an insulating film is formed on a step on a substrate (for example, unevenness due to electrodes, wiring, etc. formed on a substrate), it is necessary to improve insulation properties or to form a multilayer structure. It is necessary to perform a flattening process. In order to eliminate the need for this planarization process, a bias sputtering method is used to achieve planarization during the formation of an insulating film, in which a high frequency bias is applied to the substrate and etching and day positioning are performed simultaneously using the self-bias effect of the substrate. Are known. Application of this high frequency bias can also be applied in the ECR plasma CVD method, and is expected to improve the step coverage of the insulating film.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、ECRプラズマCVD法により高周波バ
イアスの印加の下で基板上に絶縁膜を形成した場合には
、高周波バイアスに基づくイオン衝撃等により、基板上
の配線等にヒロック、ストレスマイグレーション、その
他の損傷が発生するという問題点があった。
However, when an insulating film is formed on a substrate using the ECR plasma CVD method under the application of a high-frequency bias, hillocks, stress migration, and other damage may occur in the wiring on the substrate due to ion bombardment caused by the high-frequency bias. There was a problem that occurred.

更に、絶縁膜のうち段差部を被覆する部分の膜質が特に
悪いことから、膜内に空洞が発生する場合があり、また
、印加する高周波バイアスの出力増加に伴って膜厚分布
が不均一となり、全体としてもM質が悪化するという問
題点があった。
Furthermore, because the film quality of the part of the insulating film that covers the stepped portion is particularly poor, cavities may occur within the film, and the film thickness distribution becomes uneven as the output of the applied high-frequency bias increases. However, there was a problem in that the overall M quality deteriorated.

そこで、本発明は上記問題点を解決するものであり、そ
の課題は、ECRプラズマCVD法の特性を利用して成
膜状態の異なる複数工程を以て絶縁膜を形成することに
よって、膜質が高く、段差被覆性及び平坦性に優れた絶
縁膜が形成可能であって、しかも下地損傷を生じない絶
縁膜の製造方法を提供することにある。
SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned problems, and its object is to form an insulating film through multiple steps with different film formation conditions by utilizing the characteristics of the ECR plasma CVD method. It is an object of the present invention to provide a method for manufacturing an insulating film that can form an insulating film with excellent coverage and flatness and does not cause damage to the underlying layer.

〔課題を解決するための手段〕[Means to solve the problem]

上記問題点を解決するために、本発明が講じた手段は、 基板に高周波バイアスを印加しないか、又は低出力の高
周波バイアスを印加することにより、基板上の段差部の
周面上に下地保護絶縁膜を形成する工程と、その後、よ
り高出力の高周波バイアス下にて下地保護絶縁膜の上層
に高被覆性絶縁膜を形成する工程とを設けるものである
In order to solve the above problems, the measures taken by the present invention are to protect the base on the circumferential surface of the step portion on the substrate by not applying a high frequency bias to the substrate or by applying a low output high frequency bias to the substrate. The method includes a step of forming an insulating film, and then a step of forming a highly covering insulating film on the base protective insulating film under a high-power high-frequency bias.

また、高被覆性絶縁膜を形成する工程の後に、成膜ガス
中にAr又はAr及びHeを混入して高周波バイアス下
にて成膜する工程を設け、平坦化絶縁膜を形成する場合
もある。
In addition, after the step of forming a highly covering insulating film, a step of mixing Ar or Ar and He into the film forming gas and forming a film under high frequency bias may be provided to form a flattened insulating film. .

このような上記各工程において、基板の周囲にはカスプ
磁場(逆方向の2つの発散磁場によって形成される磁場
をいう、)を形成し、このカスプ磁場中におけるカスプ
面(法線方向の磁界強度がゼロになる平面若しくは曲面
をいう、)の近傍に基板を設置し、基板面をカスプ面に
対して平行に配置する場合もある。
In each of the above steps, a cusp magnetic field (a magnetic field formed by two divergent magnetic fields in opposite directions) is formed around the substrate, and the cusp surface (magnetic field strength in the normal direction) in this cusp magnetic field is In some cases, the substrate is placed near a plane or curved surface (which is a plane or curved surface on which the angle is zero), and the substrate surface is placed parallel to the cusp surface.

〔作用〕[Effect]

かかる手段によれば、基板上の段差部には、先ず、高周
波バイアス無印加又は低出力の高周波バイアス印加によ
り下地保護絶縁膜が形成される。
According to this method, a base protective insulating film is first formed on the step portion on the substrate by applying no high-frequency bias or applying a low-power high-frequency bias.

この絶縁膜は、高周波バイアス印加による基板の自己バ
イアス効果がない状態又は弱い状態で成膜されるため、
段差部や基板表面に損傷を与えるおそれが少なく、また
、電極や配線部のヒロックやストレスマイグレーション
の発生を防ぐことができる。
This insulating film is formed in a state where the self-bias effect of the substrate is absent or weak due to the application of a high-frequency bias.
There is less risk of damaging the stepped portion or the substrate surface, and it is possible to prevent hillocks and stress migration in the electrodes and wiring portions.

次に、下地保護絶縁膜の上層に、より高出力の高周波バ
イアスを印加することにより高被覆性絶縁膜を形成する
ので、基板の自己バイアス効果により段差部の被覆性が
改善され、絶縁膜の上面の平坦性が向上する。この工程
中、上記の下地保護絶縁膜の存在によって、高周波バイ
アス印加による段差部等の損傷は生じない。
Next, a high-coverage insulating film is formed by applying a high-power high-frequency bias to the upper layer of the base protective insulating film, so the coverage of the stepped portion is improved due to the self-bias effect of the substrate, and the insulating film is The flatness of the top surface is improved. During this step, due to the presence of the base protective insulating film, damage to the stepped portions and the like due to high frequency bias application does not occur.

更に、この後に、成膜ガス中にArを混入して成膜する
工程を設ける場合には、自己バイアス効果によるスパッ
タ作用が強化され、高いアスペクト比を備えた配線等の
段差部上にも、より平坦な絶縁膜を形成することができ
る。Arと共にHeを混入する場合には、Arのスパッ
タエツチング速度が緩和され、絶縁膜中へのArの混入
を防止する上に、スパッタ速度の面内均一性を向上させ
る効果がある。したがって、ArとHeの流量及び混合
比を調整することによって、段差部形状に応じた絶縁膜
の平坦化を図ることが可能であり、更に、膜質改善及び
膜厚の均一化を期すことができる。
Furthermore, if a step of forming a film by mixing Ar into the film forming gas is provided after this, the sputtering effect due to the self-bias effect is strengthened, and even on stepped portions such as wiring with a high aspect ratio, A flatter insulating film can be formed. When He is mixed with Ar, the sputter etching rate of Ar is reduced, which has the effect of preventing the incorporation of Ar into the insulating film and improving the in-plane uniformity of the sputtering rate. Therefore, by adjusting the flow rate and mixing ratio of Ar and He, it is possible to planarize the insulating film according to the shape of the stepped portion, and furthermore, it is possible to improve the film quality and make the film thickness uniform. .

このように、成膜状態の異なった複数の工程により段階
的に絶縁膜を形成するので、基板表面や段差部等に損傷
を与えることもなく、段差被覆性が良く、充分に平坦化
された高品質の絶縁膜を形成することができる。
In this way, the insulating film is formed step by step through multiple processes with different film formation conditions, so there is no damage to the substrate surface or step areas, and the step coverage is good and the insulating film is sufficiently flattened. A high quality insulating film can be formed.

上記の各工程において、基板の周囲にカプス磁場を形成
し、カプス面の近傍に基板を平行配置した場合には、カ
プス面の磁束の急激な発散により基板に到達するプラズ
マ流が均一化され、絶縁膜の膜厚及び膜質の均一化が更
に向上する。この効果は高出力の高周波バイアス印加時
にも失われないため、上記方法には特に有効である。
In each of the above steps, when a caps magnetic field is formed around the substrate and the substrate is placed in parallel near the caps surface, the plasma flow reaching the substrate is made uniform due to the sudden divergence of the magnetic flux on the caps surface. The uniformity of the thickness and quality of the insulating film is further improved. This effect is not lost even when a high-power, high-frequency bias is applied, so it is particularly effective for the above method.

〔実施例〕〔Example〕

次に、添付図面を参照して、本発明に係る半導体装置の
製造方法の実施例を説明する。
Next, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

先ず、第1図を参照して、本実施例に用いるECRプラ
ズマCVDI置装構造を説明する。導波管1はマイクロ
波導入窓2を介して、主磁気コイル4により磁場が形成
されたプラズマ生成室5に接続されており、空洞共振器
を構成するプラズマ生成室5内でマイクロ波周波数と磁
界強度がECR条件を充たすことにより、第1ガス導入
系3から流入する0□ガスはエネルギーを共鳴吸収し、
高密度のプラズマとなる。この0!プラズマは、開口部
8付近に形成された発散磁場によって、プラズマ生成室
5から反応室6へ引き出される。この時、第2ガス導入
系7からSiH,(シラン)ガスを導入すると、0!プ
ラズマのエネルギーにより5iHaガスが分解されて、
試料台10に設置された基板9の表面上にSi0g膜が
形成される。ここで、試料台IOには、高周波電源12
が接続され、基板9にRFバイアスを印加できるように
なっており、また、試料台10の下方には補助磁気コイ
ル11が設けられ、主磁気コイル4により形成される発
散磁場と補助磁気コイル2により形成される磁場とから
反応室6内にカスプ磁場が形成されるようになっている
First, with reference to FIG. 1, the structure of the ECR plasma CVDI device used in this example will be explained. The waveguide 1 is connected via a microwave introduction window 2 to a plasma generation chamber 5 in which a magnetic field is formed by a main magnetic coil 4, and the microwave frequency and When the magnetic field strength satisfies the ECR condition, the 0□ gas flowing from the first gas introduction system 3 absorbs energy resonantly,
It becomes a high-density plasma. This 0! The plasma is drawn out from the plasma generation chamber 5 to the reaction chamber 6 by a divergent magnetic field formed near the opening 8 . At this time, when SiH, (silane) gas is introduced from the second gas introduction system 7, 0! 5iHa gas is decomposed by plasma energy,
A Si0g film is formed on the surface of the substrate 9 placed on the sample stage 10. Here, the sample stage IO has a high frequency power supply 12.
is connected so that an RF bias can be applied to the substrate 9, and an auxiliary magnetic coil 11 is provided below the sample stage 10, and the diverging magnetic field formed by the main magnetic coil 4 and the auxiliary magnetic coil 2 A cusp magnetic field is formed in the reaction chamber 6 from the magnetic field formed by the magnetic field.

次に、上記のECRプラズマCVD装置を用いてSiO
□膜を形成する方法を、第2図を参照して説明する。第
2図(a)に示すように、シリコン基Fi、21の表面
上には配線22が形成されてお。
Next, using the above ECR plasma CVD apparatus, SiO
□The method for forming the film will be explained with reference to FIG. As shown in FIG. 2(a), a wiring 22 is formed on the surface of the silicon base Fi.

す、これらの上に、第2図(b)に示すように、基板に
下地保護酸化膜23を形成する。この下地保護酸化膜2
3は、配線22の表面に損傷、ヒロック、ストレスマイ
グレーションを発生させないため、シリコン基板21に
RFバイアスを印加しないか又は小出力のRFバイアス
を印加して形成される。また、後の平坦化了程を短縮す
るためになるべく薄<形成する0次に、第2図(C)に
示すように、高出力のRFバイアスをシリコン基板21
に印加して、より段差被覆性を向上させた高被覆性酸化
膜24を形成して膜厚をある程度大きくする。最後に、
第2図(d)に示すように、反応室6内にAr及びHe
ガスを導入してスパッタエツチング効果を生じさせ、平
坦化酸化膜25を形成する。
Then, a base protective oxide film 23 is formed on the substrate as shown in FIG. 2(b). This base protective oxide film 2
3 is formed by applying no RF bias to the silicon substrate 21 or by applying a low-output RF bias to the silicon substrate 21 in order to prevent damage, hillocks, and stress migration from occurring on the surface of the wiring 22. In addition, in order to shorten the planarization process later, a high-power RF bias is applied to the silicon substrate 21 to form it as thin as possible.
is applied to form a high coverage oxide film 24 with improved step coverage and increase the film thickness to some extent. lastly,
As shown in FIG. 2(d), Ar and He are present in the reaction chamber 6.
A gas is introduced to produce a sputter etching effect to form a planarized oxide film 25.

このように、成膜条件を段階的に変えた複数の工程によ
って、完全に平坦化された酸化膜を形成することが可能
であり、しかも、下地保護酸化膜23によって、シリコ
ン基板21の表面や配m22に与える損傷が少なくなり
、ヒロック、ストレスマイグレーション等が発生しない
、ここに、上記の第2図(a)、(b)及び(c)の各
工程において、それぞれ、成膜条件の異なった複数の酸
化膜を形成することも可能であり、また、各工程の間に
、前後の工程における成膜条件の中庸的な条件で成膜す
る工程を設けることもできる。二のような形成方法の例
として、ECRプラズマCVD法の基本的な成膜条件を
第1表に示し、第2表には、第1実施例における各工η
ごとの成膜条件を示す。
In this way, it is possible to form a completely flattened oxide film through a plurality of steps in which the film formation conditions are changed stepwise.Moreover, the underlying protective oxide film 23 protects the surface of the silicon substrate 21 and the surface of the silicon substrate 21. Damage to the metal 22 is reduced, and hillocks, stress migration, etc. do not occur. Here, in each of the steps shown in FIGS. It is also possible to form a plurality of oxide films, and a step of forming a film under conditions that are intermediate to the film forming conditions of the previous and subsequent steps can also be provided between each step. As an example of the formation method described in 2, Table 1 shows the basic film formation conditions of the ECR plasma CVD method, and Table 2 shows the respective process η in the first example.
The film formation conditions for each are shown below.

第   1   表 第 表 ここで、前処理工程においては、第1ガス導入系3から
の02ガスのみを導入し、第2ガス導入系7からはSi
H,ガスを導入しない、これは、シリコン基板21の表
面に02プラズマを照射することによって、表面を活性
化すると共にクリーニング効果を生ぜしめるものである
。また、第1層の酸化膜を形成する第1工程と、高出力
のRFバイアスを印加して成膜する第3工程との間に、
小出力のRFバイアスを印加して成膜する第2工程を設
けている。更に、第4工程におけるA「ガス及びHeガ
スは、酸化膜の平坦化の進行状態を観察しながら、各流
量及び混合割合を調整して成膜することもできる0例え
ば、スパッタエツチング速度を低下させたい場合には、
Arガスの流量を低下させ又はHeガスの流量を増加す
ることにより対処できる。なお、Heガスの混入は、A
rガスによるスパッタエツチング速度をある程度低下さ
せ、また、酸化膜中にArが混入することによって成膜
後にAtが脱気して酸化膜を破壊する現象を防止し、更
に膜厚分布を均一化する効果がある。一方、Heガスは
他の物質との反応性が低いため、膜質に影響を与えない
、第4図には、Arガスを混入しない場合と、Arガス
及びHeガスの双方を混入した場合とを比較するために
、双方の条件にて形成した酸化膜のBHF (HF、H
!0及びNH,Fの混合液)によるエツチング速度−耐
酸性の目安となる−と、酸化膜の成膜速度とを示した。
Table 1 Here, in the pretreatment process, only the 02 gas from the first gas introduction system 3 is introduced, and the Si gas is introduced from the second gas introduction system 7.
No H gas is introduced. This is because the surface of the silicon substrate 21 is irradiated with 02 plasma to activate the surface and produce a cleaning effect. Furthermore, between the first step of forming the first layer oxide film and the third step of forming the film by applying a high-power RF bias,
A second step is provided in which a low-power RF bias is applied to form a film. Furthermore, in the fourth step, the A gas and the He gas may be used to form a film by adjusting the flow rate and mixing ratio of each while observing the progress of planarization of the oxide film. For example, the sputter etching rate may be reduced. If you want to
This can be dealt with by decreasing the flow rate of Ar gas or increasing the flow rate of He gas. In addition, the mixing of He gas is caused by A
It reduces the sputter etching speed by r gas to some extent, prevents the phenomenon that Ar is mixed into the oxide film and At degass after film formation and destroys the oxide film, and furthermore makes the film thickness distribution uniform. effective. On the other hand, He gas has low reactivity with other substances, so it does not affect the film quality. Figure 4 shows the case where Ar gas is not mixed and the case where both Ar gas and He gas are mixed. For comparison, BHF (HF, H
! The etching rate (which is a measure of acid resistance) using a mixed solution of 0, NH, and F, and the rate of oxide film formation are shown.

このように、Arガス及びHeガスの混入は膜質には大
きな影響を与えない一方で、RF小出力混合比により成
膜速度等を変えることができるので、成膜条件を制御す
る手段の一つとすることができると共に、同一工程内に
おいてA「ガス及びHeガスの混合比を変更する等の手
段により成膜条件を変化させることが可能となり、工程
の省略及び短縮化を図ることができる。
In this way, while the mixing of Ar gas and He gas does not have a large effect on the film quality, it is possible to change the film formation rate etc. by changing the RF low output mixing ratio, so it is considered as a means to control the film formation conditions. In addition, it becomes possible to change the film forming conditions within the same process by changing the mixing ratio of A gas and He gas, and it is possible to omit and shorten the process.

上記の効果は、第3表に各工程の条件を示す第2実施例
においても同様に達成される。この第2実施例では、下
地保護絶縁膜を形成する第1工程において、小出力のR
Fバイアスを基板に印加することによりある程度の段差
被覆性を6育保している。ここで、第2工程は、膜厚の
均一性を改善するために導入されたものである。
The above effects are similarly achieved in the second embodiment, the conditions of each step of which are shown in Table 3. In this second embodiment, in the first step of forming the underlying protective insulating film, a small output R
By applying F bias to the substrate, a certain level of step coverage can be maintained. Here, the second step was introduced to improve the uniformity of the film thickness.

第    3    表 更に、上記の第1実施例及び第2実施例に示す4工程の
後に第4表に示す2工程を追加することによって、より
完全に平坦化成膜を施すことが可能であり、高アスペク
ト比の配線部が形成された基板上にも平坦な酸化膜を成
膜することが可能である。
Table 3 Furthermore, by adding the two steps shown in Table 4 after the four steps shown in the first and second examples above, it is possible to more completely planarize the film. It is also possible to form a flat oxide film on a substrate on which a wiring portion with a high aspect ratio is formed.

第 4 表 以上の実施例においては、主磁気コイル4による磁場に
加えて補助磁気コイル11による磁場を発生させ、両磁
場により、反応室6内にカスプ磁場を形成しており、シ
リコン基板21がカスプ面上に沿って平行に配置するよ
うにしている。この結果、シリコン基板9に到達するプ
ラズマの密度及びエネルギーが均一化すると考えられ、
実際にも膜厚及び膜質の面内分布が均一化される。この
効果は、第4図に示すように、従来の発散磁場の下にお
ける成膜と異なり、RF比出力高い場合にも失われない
ので、均一性を低下させることなくRF印加を施すこと
ができる。
Table 4 In the above embodiments, a magnetic field is generated by the auxiliary magnetic coil 11 in addition to the magnetic field by the main magnetic coil 4, and a cusp magnetic field is formed in the reaction chamber 6 by both magnetic fields, and the silicon substrate 21 is They are arranged parallel to each other along the cusp surface. As a result, it is thought that the density and energy of the plasma reaching the silicon substrate 9 become uniform,
In fact, the in-plane distribution of film thickness and film quality is made uniform. As shown in Figure 4, unlike conventional film formation under a divergent magnetic field, this effect is not lost even when the RF specific output is high, so RF application can be performed without reducing uniformity. .

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、ECRプラズマCVD
法を用いた半導体装置の製造方法において、基板に印加
する高周波バイアスの出力、Arガス等の混入有無等の
条件を変えた複数の工程によって基板の段差部上に絶縁
膜を形成することに特徴を有するので、以下の効果を奏
する。
As explained above, the present invention is applicable to ECR plasma CVD
A method for manufacturing semiconductor devices using the method, characterized by forming an insulating film on the stepped portion of the substrate through multiple steps in which conditions such as the output of the high-frequency bias applied to the substrate and the presence or absence of mixing of Ar gas, etc. Since it has the following effects.

■ 高周波バイアスの印加の有無及び高周波バイアスの
出力の増減によって、下地保護絶縁膜と高被覆性絶縁膜
を形成するので、基板表面及び段差部に損傷を与えずに
段差被覆性の良い絶縁膜を形成できる。
■ A base protective insulating film and a high-coverage insulating film are formed by applying or not applying a high-frequency bias and increasing or decreasing the output of the high-frequency bias, so an insulating film with good step coverage can be formed without damaging the substrate surface or step portion. Can be formed.

■ Arガスの混入により平坦化絶縁膜を成膜する工程
を設ける場合には、高周波バイアスの印加によるスパッ
タ効果が強化され、高アスペクト比の段差部上にも充分
な平坦性を備えた絶縁膜を形成することができる。ここ
で、Heガスを混合する場合には、スパッタエツチング
条件を調整変更することができると共にその面内均一性
を高めることができ、更に、絶縁膜中へのArの混入を
防止できる。
■ If a step is provided to form a flattened insulating film by mixing Ar gas, the sputtering effect by applying a high frequency bias will be strengthened, and the insulating film will have sufficient flatness even on stepped portions with high aspect ratios. can be formed. Here, when He gas is mixed, the sputter etching conditions can be adjusted and changed, the in-plane uniformity can be improved, and furthermore, the incorporation of Ar into the insulating film can be prevented.

■ 基板の周囲にカスプ磁場を形成し、カスプ面近傍に
基板を設置する場合には、膜厚及び膜質の均一性が向上
する。また、高出力の高周波バイアスを印加する場合に
もその均一性は悪化しないので、高周波バイアスによる
平坦化制御をより有効に行なうことができる。
(2) When a cusp magnetic field is formed around the substrate and the substrate is placed near the cusp surface, the uniformity of film thickness and film quality is improved. Further, even when applying a high-power high-frequency bias, the uniformity does not deteriorate, so that flattening control using the high-frequency bias can be performed more effectively.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による半導体装置の製造方法の実施例に
用いるECRプラズマCVD装置の構造を示す縦断面図
である。 第2図は同実施例の製造方法を示す工程断面図である。 第3図は同実施例における絶縁膜のエツチング速度及び
成膜速度のRF比出力対する依存性を、Arガスを成膜
ガス中に混入せずに形成した場合と、Arガス及びHe
ガスを成膜ガス中に混合した場合との比較において示す
グラフ図である。 第4図は同実施例において形成した絶縁膜の膜厚の面内
均一性を従来技術との比較において示すグラフ図である
。 〔符号の説明〕 l・・・導波管 2・・・マイクロ波導入窓 3・・・第1ガス導入系 4・・・主磁気コイル 5・・・プラズマ生成室 6・・・反応室 7・・・第2ガス導入系 8・・・開口部 9・・・基板 10・・・試料台 11・・・補助磁気コイル 12・・・高周波電源 21・・・シリコン基板 22・・・配線 23・・・下地保護酸化膜 24・・・高被覆性酸化膜 25・・・平坦化酸化膜。 排気系 第 ] 図 第 図 00 00 300 400  500 RF−Power (W) 00 第 区 試料中心がらの距離 第 図
FIG. 1 is a longitudinal sectional view showing the structure of an ECR plasma CVD apparatus used in an embodiment of the method of manufacturing a semiconductor device according to the present invention. FIG. 2 is a process sectional view showing the manufacturing method of the same embodiment. FIG. 3 shows the dependence of the etching rate and deposition rate of the insulating film on the RF specific output power in the same example, when the insulating film was formed without mixing Ar gas into the deposition gas, and when it was formed using Ar gas and He gas.
It is a graph diagram shown in comparison with a case where a gas is mixed into a film forming gas. FIG. 4 is a graph showing the in-plane uniformity of the thickness of the insulating film formed in the same example in comparison with the prior art. [Explanation of symbols] l... Waveguide 2... Microwave introduction window 3... First gas introduction system 4... Main magnetic coil 5... Plasma generation chamber 6... Reaction chamber 7 . . . Second gas introduction system 8 . . . Opening 9 . . . Substrate 10 . ...Underlying protective oxide film 24...High coverage oxide film 25...Flattening oxide film. Exhaust system] Diagram 00 00 300 400 500 RF-Power (W) 00 Section Distance from the center of the sample Diagram

Claims (3)

【特許請求の範囲】[Claims] (1)基板に高周波バイアスを印加可能なECRプラズ
マCVD法により、該基板に形成された段差部上に絶縁
膜を形成する工程を有する半導体装置の製造方法におい
て、 高周波バイアスを印加しないか又は低出力の高周波バイ
アスを印加することにより、前記段差部の周面上に下地
保護絶縁膜を形成する工程と、その後、より高出力の高
周波バイアス下にて該下地保護絶縁膜の上層に高被覆性
絶縁膜を形成する工程とを有することを特徴とする絶縁
膜を備えた半導体装置の製造方法。
(1) In a method for manufacturing a semiconductor device that includes a step of forming an insulating film on a stepped portion formed on a substrate by an ECR plasma CVD method that can apply a high frequency bias to the substrate, the high frequency bias is not applied or the high frequency bias is low. A step of forming a base protective insulating film on the circumferential surface of the stepped portion by applying an output high frequency bias, and then forming a high coverage layer on the base protective insulating film under a higher output high frequency bias. 1. A method for manufacturing a semiconductor device including an insulating film, the method comprising: forming an insulating film.
(2)前記高被覆性絶縁膜を形成する工程の後に、Ar
又はAr及びHeを混入した成膜ガスにより高周波バイ
アス下において平坦化絶縁膜を形成する工程を有するこ
とを特徴とする請求項第1項に記載の絶縁膜を備えた半
導体装置の製造方法。
(2) After the step of forming the high coverage insulating film, Ar
2. A method for manufacturing a semiconductor device having an insulating film according to claim 1, further comprising the step of forming a planarized insulating film under a high frequency bias using a film forming gas mixed with Ar and He.
(3)前記各工程において、前記基板の周囲にはカスプ
磁場が形成され、前記基板は該カスプ磁場中におけるカ
スプ面近傍に設置され、前記基板の表面は該カスプ面に
対し平行に配置されていることを特徴とする請求項第1
項又は第2項に記載の絶縁膜を備えた半導体装置の製造
方法。
(3) In each of the above steps, a cusp magnetic field is formed around the substrate, the substrate is placed near the cusp surface in the cusp magnetic field, and the surface of the substrate is arranged parallel to the cusp surface. Claim 1 characterized in that
A method for manufacturing a semiconductor device comprising the insulating film according to item 1 or 2.
JP2081967A 1990-03-29 1990-03-29 Method for manufacturing semiconductor device having insulating film Expired - Fee Related JP2803304B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2081967A JP2803304B2 (en) 1990-03-29 1990-03-29 Method for manufacturing semiconductor device having insulating film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2081967A JP2803304B2 (en) 1990-03-29 1990-03-29 Method for manufacturing semiconductor device having insulating film

Publications (2)

Publication Number Publication Date
JPH03280539A true JPH03280539A (en) 1991-12-11
JP2803304B2 JP2803304B2 (en) 1998-09-24

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02100054A (en) * 1988-10-07 1990-04-12 Fuji Photo Film Co Ltd Positive type photosensitive composition
JPH07106330A (en) * 1993-10-08 1995-04-21 Nippon Precision Circuits Kk Formation of insulating layer in semiconductor device
US5575886A (en) * 1994-07-30 1996-11-19 Nec Corporation Method for fabricating semiconductor device with chemical-mechanical polishing process for planarization of interlayer insulation films
KR970052911A (en) * 1995-12-29 1997-07-29 김주용 Planarization method of semiconductor device
US5948485A (en) * 1995-04-05 1999-09-07 Tokyo Electron Limited Plasma deposition method and an apparatus therefor
US5981375A (en) * 1996-07-11 1999-11-09 Oki Electric Industry Co., Ltd. Method of manufacturing a semiconductor device
JP2000077404A (en) * 1998-07-31 2000-03-14 Samsung Electronics Co Ltd Insulating film formation method
KR100607820B1 (en) * 2004-12-29 2006-08-02 동부일렉트로닉스 주식회사 Method of forming interlayer insulating film of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6465843A (en) * 1987-09-07 1989-03-13 Hitachi Ltd Plasma treatment device
JPH01241136A (en) * 1988-03-23 1989-09-26 Toshiba Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6465843A (en) * 1987-09-07 1989-03-13 Hitachi Ltd Plasma treatment device
JPH01241136A (en) * 1988-03-23 1989-09-26 Toshiba Corp Manufacture of semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02100054A (en) * 1988-10-07 1990-04-12 Fuji Photo Film Co Ltd Positive type photosensitive composition
JPH07106330A (en) * 1993-10-08 1995-04-21 Nippon Precision Circuits Kk Formation of insulating layer in semiconductor device
US5575886A (en) * 1994-07-30 1996-11-19 Nec Corporation Method for fabricating semiconductor device with chemical-mechanical polishing process for planarization of interlayer insulation films
US5948485A (en) * 1995-04-05 1999-09-07 Tokyo Electron Limited Plasma deposition method and an apparatus therefor
KR970052911A (en) * 1995-12-29 1997-07-29 김주용 Planarization method of semiconductor device
US5981375A (en) * 1996-07-11 1999-11-09 Oki Electric Industry Co., Ltd. Method of manufacturing a semiconductor device
JP2000077404A (en) * 1998-07-31 2000-03-14 Samsung Electronics Co Ltd Insulating film formation method
KR100607820B1 (en) * 2004-12-29 2006-08-02 동부일렉트로닉스 주식회사 Method of forming interlayer insulating film of semiconductor device

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