JPH03280565A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03280565A JPH03280565A JP2082691A JP8269190A JPH03280565A JP H03280565 A JPH03280565 A JP H03280565A JP 2082691 A JP2082691 A JP 2082691A JP 8269190 A JP8269190 A JP 8269190A JP H03280565 A JPH03280565 A JP H03280565A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- thin film
- plating
- gold
- hue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、 外部リードに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device, Regarding external leads.
特に半導体装置の
半導体装置は、その封止材としてプラスチックを用いた
ものや金属、セラミックスを用いたものがあり、いずれ
も金属よりなる複数本の外部リードを具備している。第
2図は従来の半導体装置の断面図である。外部リード1
の封止材2に埋めこまれた部分1aは半導体素子3の電
極と金属細線4で接続され、外部リード1の封止材2か
ら露出した部分1bは第3図に示すようにプリント配線
基板8等に接続される。この接続は錫鉛系の共晶合金を
用いて行なわれる。その接続を容易にするため外部リー
ド1の露出部分には既に錫鉛の半田めっきらが施工され
ている。In particular, some semiconductor devices use plastic, metal, or ceramic as their sealing material, and all of them are equipped with a plurality of external leads made of metal. FIG. 2 is a sectional view of a conventional semiconductor device. External lead 1
A portion 1a embedded in the encapsulant 2 is connected to an electrode of the semiconductor element 3 by a thin metal wire 4, and a portion 1b of the external lead 1 exposed from the encapsulant 2 is connected to a printed wiring board as shown in FIG. Connected to 8th grade. This connection is made using a tin-lead based eutectic alloy. In order to facilitate the connection, the exposed portions of the external leads 1 have already been plated with tin-lead solder.
上述した従来の半導体装置をプリント配線基板の所定の
位置に仮止めし、そのまま溶融半田槽をくぐらせて半導
体装置の外部リード1とプリント配線基板8上に設けら
れた導体パターン9と半田付して実装する(第3図)。The above-described conventional semiconductor device is temporarily fixed at a predetermined position on a printed wiring board, and passed through a molten solder tank as it is to solder the external leads 1 of the semiconductor device and the conductor pattern 9 provided on the printed wiring board 8. (Figure 3).
又、前述の導体パターンの所定個所に半田ペーストを印
刷し、その半田ペースト上に半導体装置の外部リードを
おき、そのまま加熱して外部リードと導体パターンを半
田付けする方法もある。いずれの場合も半田付けの良否
を確認するため、外部リードと導体パターンとの接続部
をチエツクする必要がある。Another method is to print a solder paste at a predetermined location on the conductive pattern described above, place the external lead of the semiconductor device on the solder paste, and heat it as it is to solder the external lead and the conductive pattern. In either case, it is necessary to check the connection between the external lead and the conductor pattern to confirm the quality of the soldering.
ところで、最近、高密度実装が容易であるため、SOP
、SOJといった表面実装対応の半導体装置の使用量が
増えている。しかしながら、第3図に示すように外部リ
ード1の下面とプリント配線基板8上面の導体パターン
9上面とが半田接続されるため、接続部を目視観察する
ことができない、そこで外部リード上面、端面、側面の
色調や半田盛り上がり形状を観察し、半田付けの良否を
判断していた。しかしながら、この方法では目視観察に
要する時間が膨大な上、誤判定も多いという欠陥を有し
ていた。By the way, recently, because high-density packaging is easy, SOP
The usage of surface-mountable semiconductor devices such as , SOJ, etc. is increasing. However, as shown in FIG. 3, since the lower surface of the external lead 1 and the upper surface of the conductor pattern 9 on the upper surface of the printed wiring board 8 are connected by soldering, it is not possible to visually observe the connection part. The quality of the soldering was determined by observing the color tone of the sides and the shape of the solder bulges. However, this method has the disadvantage that it takes an enormous amount of time for visual observation and also causes many erroneous determinations.
本発明は、半田めっきを施した外部リードを有する半導
体装置において、半田めっきが施された外部リード表面
をさらに半田めっきの色相とは全く異なる物質によって
コーティングしたことを特徴とする。半田めっきの色相
と全く異なる物質は、電解又は無電解銅めっき薄膜又は
金めつき薄膜である。又、赤外線吸収機能を有する有機
化合物被膜や単に色素被膜も適用することができる。The present invention is characterized in that, in a semiconductor device having solder-plated external leads, the surface of the solder-plated external leads is further coated with a substance completely different in hue from the solder plating. A substance that is completely different in hue from solder plating is an electrolytic or electroless copper plating thin film or a gold plating thin film. Further, an organic compound film having an infrared absorption function or a simple dye film can also be applied.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第1の実施例の縦断面図である。外部
リード1の封止材2に埋めこまれている一端la部は半
導体素子3の表面電極と金属細線4と接続され、封止材
2から露出しているもう一方の部分lb部は半田めっき
5によって被膜され、さらに半田めっき5の表面は銅め
っき薄膜6により被膜されている。FIG. 1 is a longitudinal sectional view of a first embodiment of the invention. One end part (la) of the external lead 1 that is embedded in the sealing material 2 is connected to the surface electrode of the semiconductor element 3 and the thin metal wire 4, and the other part (lb) which is exposed from the sealing material 2 is solder plated. Further, the surface of the solder plating 5 is coated with a copper plating thin film 6.
半導体装置の外部リード処理プロセスにおいて、従来と
同様に半田めっきを5〜20u施工した後、電解銅めっ
き浴を用いて0.01〜0.1μの厚さの銅めっきを析
出させる。銅めっき浴はビロリン酸銅浴、スルファシン
酸銅浴などが用いられ、特に限定はされない。銅めっき
自体の酸化変色をきらう場合は電解金めつき浴にて0.
O1〜0.05μ程度の金めつきを析出させてもよい。In an external lead processing process for a semiconductor device, after applying 5 to 20 microns of solder plating as in the conventional method, copper plating with a thickness of 0.01 to 0.1 micron is deposited using an electrolytic copper plating bath. The copper plating bath used may be a copper birophosphate bath, a copper sulfacate bath, or the like, and is not particularly limited. If you do not want oxidation discoloration of the copper plating itself, use an electrolytic gold plating bath.
Gold plating of about 01 to 0.05μ may be deposited.
このようにして外部リード1の半田めつき5上に銅、金
などめっき薄膜6を形成させたのち、リード切断、曲げ
加工を行なって半導体装置を作成する。この方法ではめ
つき後切断するため外部リードの切断面は着色できない
欠点を持っている。After forming a plating thin film 6 of copper, gold, etc. on the solder plating 5 of the external lead 1 in this manner, the leads are cut and bent to produce a semiconductor device. This method has the disadvantage that the cut surface of the external lead cannot be colored because it is cut after plating.
このようにして製造した半導体装置の外部り−ド1は半
田の色相である銀白色とは全く異なった赤褐色、金色の
色相を呈している。この赤褐色又は金色の銅、金めつき
薄膜6は、第3図に示すようにプリント配線基板8に実
装する際加熱され、外部リードに施工されている半田め
っきが溶融する状況では徐々に溶融半田に拡散するもの
の半田付に要する時間では完全に拡散することはなく、
赤褐色ないし金色の色相を呈している。一方で外界から
供給される半田10特に噴流状態の半田には容易に巻き
込まれて溶解し、赤褐色又は金色の色相を失なう。つま
り、外界から供給される噴流半田10と外部リード1が
接触し、濡れが開始されると色相が消失するになる。こ
の場合も前述の欠点である切断したリード端面は、全く
色相の変化がないので後述の目視判定に誤判定を生むポ
テンシャルを有する。この点を避けるためには着色のた
めのめっきを外部リードの切断、曲げ加工後に行なう方
法がある。この場合はめっきとして次亜リン酸ソーダな
ど還元剤を用いた無電界鋼又は金めつきを用いることが
できる。The external board 1 of the semiconductor device manufactured in this way has a reddish-brown and golden hue that is completely different from the silvery-white hue of the solder. This reddish-brown or gold-colored copper or gold-plated thin film 6 is heated when it is mounted on a printed wiring board 8 as shown in FIG. However, it does not completely diffuse in the time required for soldering.
It has a reddish-brown to golden hue. On the other hand, the solder 10 supplied from the outside, especially the solder in a jet state, is easily entangled and melted, and loses its reddish-brown or golden hue. That is, when the jet solder 10 supplied from the outside comes into contact with the external lead 1 and wetting begins, the hue disappears. In this case as well, the cut end face of the lead, which is the drawback described above, has the potential to cause an erroneous judgment in the visual judgment described below since there is no change in hue at all. To avoid this problem, there is a method of performing coloring plating after cutting and bending the external leads. In this case, electroless steel or gold plating using a reducing agent such as sodium hypophosphite can be used as the plating.
第4図は本発明の第2の実施例の縦断面図である。外部
リード1の封止材2から露出している部分1bの半田め
っき5を第5図に示す構造式を有する赤外線吸収剤7で
被覆する。赤外線吸収剤7として0.勅μmに吸収波長
(λ□8は0.71μm)を有する暗緑色を呈する色素
、例えばモノアゾ系の色素(構造式を第5図に示した)
を用いることができる。この赤外線吸収剤7を溶剤に溶
解し、その溶液に半導体装置を浸漬し取り出して乾燥す
ることによって外部リード1に被覆することができる。FIG. 4 is a longitudinal sectional view of a second embodiment of the invention. The solder plating 5 on the portion 1b of the external lead 1 exposed from the sealing material 2 is coated with an infrared absorber 7 having the structural formula shown in FIG. 0.0 as infrared absorber 7. Pigments exhibiting a dark green color with an absorption wavelength in the micrometer range (λ□8 is 0.71 μm), such as monoazo dyes (the structural formula is shown in Figure 5)
can be used. The external leads 1 can be coated by dissolving the infrared absorber 7 in a solvent, immersing the semiconductor device in the solution, taking it out, and drying it.
前述の赤外線吸収剤7は250’C付近の温度に加熱す
ると急速に分解し、赤外線吸収機能は消滅する。When the above-mentioned infrared absorber 7 is heated to a temperature around 250'C, it rapidly decomposes and loses its infrared absorbing function.
近赤外領域に吸収波長を有し、かつ200℃以上の高温
で分解する化学物質であれば第5図に示した色素以外の
ものでも同様に取り扱かうことができる。又、効果の点
で若干不充分であるが、熱分解性を有し、かつ可視光領
域に吸収波長を有する化合物であればある程度の効果を
得ることができる。Chemical substances other than the dyes shown in FIG. 5 can be similarly treated as long as they have absorption wavelengths in the near-infrared region and decompose at high temperatures of 200° C. or higher. Further, although the effect is somewhat insufficient, a certain degree of effect can be obtained if the compound is thermally decomposable and has an absorption wavelength in the visible light region.
以上説明したように本発明の半導体装置の外部リードは
半田めっきとは異なる色相の金属薄膜又は暗緑色その他
の色相を有する化合物薄膜に被われている。このような
本発明の半導体装置をプリント配線基板に半田付は実装
すると、プリント配線基板上の所定の個所に置かれた半
導体装置の外部リードと基板の導体パターンの間及びそ
の周辺に外部から供給された溶融半田が到達し、その半
田が外部リード表面と接触した時に金属薄膜が溶融半田
に巻き込まれ溶解して金属薄膜の色相が消失する。又、
赤外線吸収剤等も溶融半田と接触すると急速に分解して
色相が消滅する。従って外界から供給された溶融半田に
被われた外部リードの着色は消失し、溶融半田に被われ
ていない外部リードの着色はそのまま残る。As described above, the external leads of the semiconductor device of the present invention are covered with a metal thin film of a different hue from solder plating or a compound thin film of dark green or other hue. When such a semiconductor device of the present invention is soldered and mounted on a printed wiring board, an external supply is applied between and around the external leads of the semiconductor device placed at a predetermined location on the printed wiring board and the conductor pattern of the board. When the molten solder reaches the external lead surface and the solder contacts the surface of the external lead, the metal thin film is caught up in the molten solder and melts, causing the color of the metal thin film to disappear. or,
When an infrared absorber or the like comes into contact with molten solder, it rapidly decomposes and its hue disappears. Therefore, the coloring of the external leads covered with the molten solder supplied from the outside disappears, and the coloring of the external leads not covered with the molten solder remains as is.
半田付実装後の外観検査では、外部リードの着色の有無
をみるだけで半田付は性の良否を判定することができる
。これによって外観検査を短時間で済ますことができ、
良否の検出力を著しく改善することができる。In the visual inspection after soldering and mounting, it is possible to determine whether the soldering is good or not by simply checking whether the external leads are colored or not. This allows the visual inspection to be completed in a short time.
The ability to detect pass/fail can be significantly improved.
さらに赤外線吸収剤等を使用するとそれに対応する光源
を用い、分光された特定波長を照射し、その反射係数等
を検出する機構を用いて外観検査を自動化することが容
易である。又、光源として赤外線吸収剤の波長と同一波
長を有するレーザー光を用いると半田付不良個所のみを
再加熱することができ、不良個所の再生が容易である。Furthermore, if an infrared absorber or the like is used, it is easy to automate the visual inspection using a corresponding light source and a mechanism that irradiates a spectroscopic specific wavelength and detects its reflection coefficient. Furthermore, if a laser beam having the same wavelength as the infrared absorber is used as a light source, only the defective soldering area can be reheated, and the defective area can be easily regenerated.
以上のように本発明は、表面実装型の半導体装置を改善
することで実装の信頼度向上、実装コスト低減に大いに
寄与するものである。As described above, the present invention greatly contributes to improving mounting reliability and reducing mounting costs by improving surface-mounted semiconductor devices.
第1図は本発明の第1の実施例の縦断面図、第2図は従
来例の縦断面図、第3図は半導体装置を実装した状態を
表わす断面図、第4図は本発明の第2の実施例を表わす
縦断面図、第5図は第2の実施例に用いた化学物質の構
造式である。
1・・・外部リード、2・・・封止材、3・・・半導体
素子、4・・・金属細線、5・・・半田めっき、6・・
・金属薄膜、7・・・赤外線吸収剤、8・・・プリント
配線基板、9・・・導体パターン、10・・・半田。FIG. 1 is a vertical cross-sectional view of the first embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a conventional example, FIG. 3 is a cross-sectional view showing a state in which a semiconductor device is mounted, and FIG. FIG. 5, a vertical cross-sectional view showing the second example, shows the structural formula of the chemical substance used in the second example. DESCRIPTION OF SYMBOLS 1... External lead, 2... Sealing material, 3... Semiconductor element, 4... Metal thin wire, 5... Solder plating, 6...
- Metal thin film, 7... Infrared absorber, 8... Printed wiring board, 9... Conductor pattern, 10... Solder.
Claims (2)
において、外部リードの半田めっき表面に銅又は金めっ
きよりなる金属薄膜を設けたことを特徴とする半導体装
置。1. 1. A semiconductor device having solder-plated external leads, characterized in that a metal thin film made of copper or gold plating is provided on the solder-plated surface of the external leads.
において、外部リードの半田めっき表面に可視及び近赤
外光領域に吸収波長を有する化合物被膜を設けたことを
特徴とする半導体装置。2. 1. A semiconductor device having solder-plated external leads, characterized in that a compound coating having an absorption wavelength in the visible and near-infrared light region is provided on the solder-plated surface of the external leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082691A JPH03280565A (en) | 1990-03-29 | 1990-03-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082691A JPH03280565A (en) | 1990-03-29 | 1990-03-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03280565A true JPH03280565A (en) | 1991-12-11 |
Family
ID=13781440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2082691A Pending JPH03280565A (en) | 1990-03-29 | 1990-03-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03280565A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07240488A (en) * | 1994-02-28 | 1995-09-12 | Nec Corp | Semiconductor device and manufacturing method thereof |
| EP0778618A3 (en) * | 1992-12-23 | 1998-05-13 | Shinko Electric Industries Co. Ltd. | Lead frame and method for manufacturing it |
| US6150712A (en) * | 1998-01-09 | 2000-11-21 | Sony Corporation | Lead frame for semiconductor device, and semiconductor device |
-
1990
- 1990-03-29 JP JP2082691A patent/JPH03280565A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0778618A3 (en) * | 1992-12-23 | 1998-05-13 | Shinko Electric Industries Co. Ltd. | Lead frame and method for manufacturing it |
| US5909053A (en) * | 1992-12-23 | 1999-06-01 | Shinko Electric Industries Co. Ltd. | Lead frame and method for manufacturing same |
| JPH07240488A (en) * | 1994-02-28 | 1995-09-12 | Nec Corp | Semiconductor device and manufacturing method thereof |
| US6150712A (en) * | 1998-01-09 | 2000-11-21 | Sony Corporation | Lead frame for semiconductor device, and semiconductor device |
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