JPH03280610A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To limit the amplitude of a reception signal within a stable range and to input the limited signal to an equalizer by calculating power of a training signal, retarding a burst signal for a processing time of power calculation or over, and correcting the amplitude of an output signal of a delay means based on the result of calculation. CONSTITUTION:The control circuit is provided with a power calculation means 3 receiving a burst signal comprising a training signal and a data signal to calculate the power of the training signal and a delay means 1 receiving the burst signal, and retarding the burst signal for a processing time or over required for the power calculation means 3. Moreover, an amplitude control means 5 is provided, which corrects the amplitude of an output signal of the delay means 1 based on the power obtained from the power calculation means 3 and a prescribed power to bring the amplitude of the training signal within a prescribed range. Then the training signal is used to control the amplitude in the burst signal by the feed forward method and the training signal especially important in the burst signal is controlled to an ideal value. Thus, excellent amplitude control is implemented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an automatic gain control circuit that controls the amplitude of a received signal and provides a signal with an appropriate amplitude to a fixture.

(Prior art) In digital mobile communications, equal equipment is required when demodulating received input signals that are affected by fading and multipath effects. It is essential to keep the amplitude of the signal within a certain range.

To achieve this, an automatic gain control circuit (AGC circuit) may be provided before the fixture.

Conventionally, there is such an AGC circuit as shown in FIG. This circuit controls the amplitude of the next received signal based on information about the current received power of one burst.

As shown in FIG. 5, this AGC circuit consists of an amplifier 1
01, detector 103, absolute value detector 105, memory 10
7, a subtracter 109 and a gain switching circuit 111.

In this AGC circuit, the gain of the amplifier 101 is varied according to the output signal of the gain switching circuit 111, and the human input signal is detected by the detector 103 via the amplifier 101, and detected by the absolute value detector 105. The absolute value of the signal is detected, and the subtracter 109 calculates the difference between the target value stored in the memory 107 and the detected absolute value, and the residual signal is input to the gain switching circuit 111 to generate a residual signal. The gain of the amplifier 101 is controlled so that the value becomes zero.

In general, when equalizing a burst signal consisting of a training signal and a data signal, the amplitude of the training signal must not be the ideal value for the equalizer in order to achieve complete equalization of the bursts. must not.

However, the AGC circuit shown in Figure 5 uses a feedback system that controls the amplitude of the next or future burst based on information about the amplitude of the current received signal, so it is not affected by fading or multipath. At least it is not possible to control the amplitude of the information of previous bursts.

Furthermore, in the case of the TDMA method, since there is a time interval between one burst, the fading state changes during the interval, and the amplitude cannot be controlled correctly. Therefore, some or all of the most important training signals for the fixture must be input to the fixture without amplitude control or with incorrect amplitude control. Therefore, when using a conventional AGC circuit,
Fixtures may not function properly.

(Problems to be Solved by the Invention) As described above, conventional AGC circuits waste part or all of the burst information in order to control the amplitude, and are unable to sufficiently follow changes in fading amplitude. There was a problem.

The present invention eliminates such problems and provides an AGC circuit that can perform extremely stable operation against fading without wasting burst information, and can input a signal with an appropriate amplitude to the equalizer. The purpose is to provide.

[Configuration of the Invention (Means for Solving the Problem) In order to achieve the above-mentioned object, the present invention provides a power calculation means that receives a burst signal consisting of a training signal and a data signal and calculates the power of the training signal. and,
The burst signal is inputted, and the delay means delays the burst signal by a processing time required for the power calculation means, based on the power obtained by the power calculation means and a predetermined power. The present invention is characterized by comprising amplitude control means for correcting the amplitude of the output signal so that the amplitude of the training signal falls within a predetermined range.

(Operation) In the present invention, the power of the training signal is calculated, the burst signal is delayed for more than the processing time required by the power calculation means, and the output signal of the delay means is calculated based on the power obtained by the power calculation means. The amplitude of the training signal is corrected so that the amplitude of the training signal falls within a predetermined range.

That is, the amplitude during a burst is controlled by a feedforward method using a training signal. Therefore, a particularly important training signal portion within one burst signal can be controlled to the ideal value itself.

At this time, amplitude control can be performed without missing any information of the received signal.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 shows an AGC circuit according to a first embodiment of the present invention. This AGC circuit includes a delay circuit 1, a power calculation circuit 3, an amplitude control circuit 5, and an AD converter 7.
The output of the D converter 7 is input to the fixture 9.

In this embodiment, the input burst signal is an analog signal consisting of a training signal and a data signal, and the power calculation circuit 3 calculates the power of this training signal.

The delay circuit 1 receives the burst signal and delays the aforementioned burst signal by a processing time required by the power calculation circuit 3 or more.

The amplitude control circuit 5 corrects the amplitude of the burst signal output from the delay circuit 1 based on the power obtained by the power calculation circuit 3, so that the amplitude of the training signal falls within an appropriate range for the equipment. Do it like this.

The AD converter 7 converts the output signal of the amplitude control circuit 5 into a digital signal and outputs it to the furniture 9.

In this embodiment, the amplitude of the entire burst signal is controlled based on information on the amplitude of the training signal.

In this case, if the amplitude of the training signal falls within the proper range of the fixture 9, the amplitude of the entire burst signal also falls within the proper range of the fixture 9.

For example, a signal whose amplitude fluctuates drastically due to fading may be input to this AGC circuit. In this case, if the training signal of the burst signal is input as an appropriate value, the change in amplitude due to fading will follow the amplitude fluctuation and correct it.

In this embodiment, changes in the amplitude of the input signal due to fading can be corrected by the equalizer itself since the training signal is input as an appropriate value.

Therefore, in this embodiment, it is possible to input all the signals within the range in which the appliance normally operates, without wasting any bursts.

FIG. 2 shows a second embodiment of the present invention. In this second embodiment, a delay circuit 13, a power calculation circuit 15, and an amplitude control circuit 17 are each used as a circuit for processing digital signals. There is. For this reason, an AD converter 11 is provided at the front stage.

FIG. 3 shows the embodiment of FIG. 2 in more detail.

As the delay circuit 13, an SRAM 13a is used.

The power calculation circuit 15a includes a squarer 21 and an adder 23.

The amplitude control circuit 17a includes a reciprocal calculator 25a and a multiplier 27.
Consisting of

The SRAM 13a delays the input signal and outputs the delayed signal.

The squarer 21 obtains the absolute value of the input signal, and the adder 23 calculates the power of the training signal by adding the absolute values one after another.

FIG. 4 further shows a third embodiment, in which a matched filter 33 is used as the power calculation means.

By correlating with the training signal, the matched filter 33 outputs a peak value at the beginning of the burst, and otherwise outputs zero or almost zero. Therefore, this peak value is taken as the power of the received signal.

This matched filter 33 is used in combination with a matched filter for processing a training signal in the demodulation circuit.

The present invention can be further modified in various ways.

For example, if the received burst signal has a training signal at the beginning and end of the burst, the delay circuit may be configured to perform By delaying the signal for the above period, the amplitude may be controlled so that the amplitude of the final portion of the training signal is within a range appropriate for the equalizer.

Additionally, if the received burst signal has training signals at the beginning and end of the burst, the delay circuit delays the signal for a period from the beginning of the burst to the end of the burst or longer. By doing this, even if the equalizer input controls the amplitude so that the average amplitude of the training signal of the first part and the training signal of the last part is within the range appropriate for the equalizer. good.

[Effects of the Invention] As explained above, according to the present invention, received signals affected by fading and multipath can be equalized within an extremely stable amplitude range without wasting even one burst. It is possible to realize an automatic gain control circuit that can be input to a device. By using this circuit, the equalizer operates correctly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an automatic gain control circuit according to a first embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of an automatic gain control circuit according to a second embodiment of the present invention. 3 is a block diagram showing the configuration of an automatic gain control circuit that further embodies FIG. 2, and FIG. 4 is a block diagram showing the configuration of an automatic gain control circuit according to a third embodiment of the present invention. 5 are block diagrams showing the configuration of a conventional automatic gain control circuit. 1.13.31...Delay circuit 3.15.
15a......Power calculation circuit 5.171.1
7a135......Amplitude control circuit 13a...SRAM

Claims (4)

[Claims] (1) A power calculation means to which a burst signal consisting of a training signal and a data signal is input and calculates the power of the training signal; delay means for delaying the output signal; and amplitude control means for correcting the amplitude of the output signal of the delay means based on the power obtained by the power calculation means so that the amplitude of the training signal falls within a predetermined range. and an automatic gain control circuit comprising: (2) having a first training signal in the first part, a second training signal in the last part, and having a data signal between the first training signal and the second training signal; power calculation means that receives the burst signal and calculates the power of the second training signal; delay means that receives the burst signal and delays the burst signal by a processing time required by the power calculation means; amplitude control means for correcting the amplitude of the output signal of the delay means based on the power obtained by the power calculation means so that the amplitude of the second training signal falls within a predetermined range; Gain control circuit. (3) having a first training signal in the first part, a second training signal in the last part, and having a data signal between the first training signal and the second training signal; a power calculation means that receives a burst signal and calculates the average power of the first training signal and the second training signal; a delay means for delaying the burst signal; and a delay means for correcting the amplitude of the output signal of the delay means based on the power obtained by the power calculation means to obtain an average of the first training signal and the second training signal. An automatic gain control circuit comprising: amplitude control means for keeping the amplitude within a predetermined range; (4) The automatic gain control circuit according to any one of claims 1 to 3, wherein the power calculation means is a matched filter.