JPH03280669A - Synchronizing signal level detection circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention is applicable to, for example, a video tape recorder (hereinafter referred to as V
This invention relates to a synchronization signal level detection circuit (referred to as TR).

(Prior Art) A block diagram of a commonly used synchronization signal level detection circuit is shown in FIG. 3(a). This circuit constitutes a peak hold circuit. The television signal from the input terminal 11 enters the positive phase input terminal of an operational amplifier 12 (hereinafter referred to as OP, Amp). OP.

The output terminal of Aml:) 12 is connected to the cathode side of diode 130. The anode side of the diode 13 is connected to the output terminal 16 and the inverting input terminal of ○P and AmD12. Further, a hold capacitor 14 and a resistor 15 are connected in parallel between the inverting input terminal of OP and Ampl 2 and the reference potential point (ground). Resistor 15 is capacitor 14
connected to prevent the charge from becoming saturated.

The operation of this synchronizing signal level detection circuit will be briefly explained.

The above circuit detects the minimum level (i.e., synchronization signal level) of the input television signal at the input terminal 11 using the time constant of the capacitor 14 and the resistor 15, and detects its minimum peak (i.e.,
negative peak) is output to the output terminal 16. If the potential of the input terminal 11 is V and the potential of the output terminal 16 is 0, then V i
<V.

At this time, the diode 13 is in an on state as shown in the equivalent circuit shown in FIG. 3(b), and a discharge current if flows from the capacitor 14 until Vi=■O. When ■i〉■0 or vi=vo, the diode 13 is turned off and the charging voltage of the capacitor 14 (negative peak of the input signal) is output to the output terminal 16 as shown in the equivalent circuit shown in FIG. Ru.

In this way, the minimum level of the input signal is held in the capacitor 14 and taken out at the output terminal 16.

By the way, tapes are played back at high speed on a VTR.

When playing back at a tape running speed different from the recording speed, such as special playback such as slow playback, for example, in the case of high-speed playback,
In a helical scan VTR, the video head scans multiple video tracks during one scan on the tape as shown in Figure 4(a), so the reproduced FM signal is as shown in Figure 4(b). It is not continuous and is divided into multiple parts.

Therefore, the S/N ratio becomes extremely poor in the divided portion. Therefore, in a VTR that records television signals by FM modulation, the FM
The divided portion of the television signal after 4111 has a level lower than the synchronization signal level.

Therefore, when the synchronizing signal level detection circuit shown in FIG. 3 is used for a television signal demodulated during special playback, it will be affected by the S/N degraded portion.

This will be explained using FIG. 5. If the synchronization signal is as shown in FIG. 5(a) under normal conditions, the synchronization signal level detected by the circuit of FIG. 3 will be as shown in FIG. 5(b). However, if a signal with a partially degraded S/N ratio is input during special playback as shown in Figure 5(C), the detected synchronization signal level will change depending on how the time constant of the resistor 15 and capacitor 14 is set. come. When the time constant is increased, as shown in Figure 5(d), it becomes extremely stable against minute level fluctuations in the input signal, but if affected by the S/N degradation part during special playback, the normal state will occur. It will take a considerable amount of time to return. Furthermore, if the time constant is made small, it will react sensitively to minute level fluctuations in the input signal and become unstable, as shown in Figure 5(e), but the S/N deterioration during special playback will It takes almost no time for things to return to normal even if they are affected by this.

(Problems to be Solved by the Invention) As described above, in the conventional synchronization signal level detection circuit, V
There has been a problem in that it is very difficult to stably detect the synchronization signal level both when performing normal playback and when performing special playback with TR.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization signal level detection circuit that can always detect a stable synchronization signal level during normal playback and special playback of a VTR.

[Structure of the Invention] (Means for Solving the Problems) The synchronization signal level detection circuit of the present invention first detects the synchronization signal level of the input signal using a peak hold means having a small time constant (fast following the input signal). Detection of
Using this signal, the detection means detects the synchronization signal of the input signal. Next, using this synchronization signal as a trigger, the input signal is sampled and held by a sample and hold means, and the synchronization signal level is detected by passing this sampled and held signal through a low-pass filter having a time constant larger than that of the peak-hold means. It is something to do.

(Operation) In the present invention, first, the synchronization signal level of the input signal is detected by a peak hold circuit with a small time constant, and the synchronization signal of the input signal is detected based on this signal.

This allows you to know the approximate position of the sync signal, and by using this signal to sample and hold the input signal (i.e., the sync signal level is held at this time), the sync signal period is expanded equidynamically to the sync signal period. , converts the input signal into a signal with only the synchronization signal level. Since this converted signal does not have unnecessary parts such as video signals, a stable synchronization signal level can be obtained by passing this signal through a low-pass filter with a large time constant and averaging the signal level.

(Embodiment) FIG. 1 shows the configuration of a synchronization signal level detection circuit according to an embodiment of the present invention.

In FIG. 1, a television signal is input to the input terminal 42. This television signal is branched into three branches and input to a peak hold circuit 44, a comparator 46, and a sample hold circuit 48. The peak hold circuit 44 has the same structure as that shown in FIG. 3(a), and is a peak hold circuit that detects the minimum level of the input television signal with a time constant. After adding an offset value to the output of the peak hold circuit 44 in an offset adding circuit 45,
This signal is supplied to one input terminal of the comparator 46, and based on this signal, the synchronization signal of the television signal supplied to the other input terminal is detected. In addition, the comparator 46
A dropout signal indicating the dropout period of the input television signal is inputted from the input terminal 41 to the input terminal 41, and the output of the comparator 46 is invalidated when the input television signal disappears. The synchronization signal detected by the comparator 46 is input to a sample pulse generation circuit 47. The sample pulse generation circuit 47 generates as its output a pulse of a certain width triggered by the synchronization signal from the comparator 46. This constant width pulse is input to the control section of the sample and hold circuit 48 as a sample pulse. The sample and hold circuit 48 detects the synchronization signal level by sampling and holding the input television signal from the terminal 42 using sample pulses. The synchronization signal level of the television signal sampled and held by the sample-and-hold circuit 48 is averaged by a low-pass filter 49 and then output to an output terminal 43. The time constant of the low-pass filter 49 is set larger than the time constant of the peak hold circuit 44.

Next, the operation of this embodiment will be explained. The peak hold circuit 44 is configured in the same manner as shown in FIG. 3(a), and its time constant is set to a small value so that its output does not change in response to level fluctuations of the input signal as shown in FIG. 5(C), that is, FIG. 2(a). is shown in Figure 5 (e
), it follows quickly. After adding a certain offset value formed by an offset addition circuit 45 to the output of the peak hold circuit 44, this is used as a reference level and compared with the level of the input television signal by a comparator 46, thereby determining the synchronization signal of the input television signal. To detect. FIG. 2(C) shows the synchronization signal detected by the comparator 46. The output of the comparator 46 is disabled by a dropout signal, as shown in FIG. 2(b), representing a lack of input signal. Comparator 4
Although the synchronization signal detected in step 6 can quickly follow level fluctuations of the input television signal, it is unstable due to noise. Therefore, the sample pulse generation circuit 4 uses the synchronization signal detected by the comparator 46 as a trigger.
At step 7, a pulse of a constant width as shown in FIG. 2(d) is created that can sample the synchronization signal level of the input television signal. This pulse operates the sample and hold circuit 48 to sample and hold the synchronization signal level of the input television signal. As a result, the time width of the synchronization signal level of the television signal composed of the synchronization signal section and the video signal section is expanded. FIG. 2(e) shows the output of the sample and hold circuit 48. Even if there is some level fluctuation in this output, by averaging the signal level with the low-pass filter 49, it can be extracted at a stable level as shown in Figure 2 (f) (Figure 2 (f) )
. The time constant of the low-pass filter 49 at this time must be larger than the time constant of the peak hold circuit 44 because the purpose is to average level fluctuations in synchronization signal units.

[Effects of the Invention] According to the present invention, the synchronization signal level can be stably detected even when the S/N ratio of the television signal is partially degraded, such as during special playback of a VTR.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a synchronization signal level detection circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram explaining the operation of the embodiment of FIG. 1, and FIG. 3 is a conventional synchronization signal level detection circuit. FIG. 4 is an explanatory diagram of a reproduced signal during special reproduction of a VTR, and FIG. 5 is a waveform diagram illustrating problems with the conventional circuit of FIG. 3. 12... operational amplifier, 13... diode, 14...
... Capacitor, 15 ... Resistor, 41 ... Dropout signal input terminal, 42 ... Television signal input terminal, 43 ... Synchronization signal level output terminal, 44 ... Peak hold circuit, 45 ...Offset addition circuit, 46...Comparator, 47...Sample pulse generation circuit, 48...Sample hold circuit, 49...Low pass filter.

Claims (1)

[Claims] Peak hold means for detecting the minimum level of the input television signal with a certain time constant; and a peak hold means for detecting the minimum level of the input television signal with a certain time constant; detection means for detecting a synchronization signal from the detection means; sample-hold means for sampling and holding the synchronization signal level of the input television signal for a certain period of time based on the synchronization signal from the detection means; A synchronization signal level detection circuit comprising: a low-pass filter having a time constant and smoothing the synchronization signal level from the sample and hold means.