JPH03280718A - Digital control frequency synthesizer - Google Patents

Digital control frequency synthesizer

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Publication number
JPH03280718A
JPH03280718A JP2082666A JP8266690A JPH03280718A JP H03280718 A JPH03280718 A JP H03280718A JP 2082666 A JP2082666 A JP 2082666A JP 8266690 A JP8266690 A JP 8266690A JP H03280718 A JPH03280718 A JP H03280718A
Authority
JP
Japan
Prior art keywords
frequency
phase
output signal
control
controlled oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2082666A
Other languages
Japanese (ja)
Inventor
Shigenori Kodama
児玉 重則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2082666A priority Critical patent/JPH03280718A/en
Publication of JPH03280718A publication Critical patent/JPH03280718A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To reduce the control step by setting a frequency division with an external control signal or a digital-digital converter. CONSTITUTION:Frequency dividers 1, 2 frequency-divide an input signal f1 of an input terminal 10 to 1/N, 1/M by using a control signal of control terminals 18, 19. A frequency mixer 3 mixes an output frequency f1/N of the frequency divider 1 and an output frequency f0 of a voltage controlled oscillator 6, a phase comparator 5 compares the phase of the output frequency f1/N-f0 of a filter 4 with the phase of the output frequency f1/N of the frequency divider 2, outputs a frequency control signal of the voltage controlled oscillator 6 to form a phase locked loop. when the phase locked loop is locked normally, since the frequency to the phase comparator 5 is equal, the relation of f0+(1/N-1/M)f1 is established to form a synthesis circuit having a frequency mixture ratio of (1/N-1/M) thereby decreasing the minimum step of frequency control.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はディジタル制御周波数合成器に関し、特に周波
数合成方式の電圧制御発振器における、その周波数合成
比が外部ディジタル信号によって制御可能なディジタル
制御周波数合成器に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a digitally controlled frequency synthesizer, and particularly to a digitally controlled frequency synthesizer whose frequency synthesis ratio can be controlled by an external digital signal in a voltage controlled oscillator using a frequency synthesis method. Concerning vessels.

〔従来の技術〕[Conventional technology]

従来、外部から周波数合成比を制御する方式の周波数合
成器の構成は、第3図の回路構成図に示すように、入力
端子10がら入力信号f!を入力し、制御端子18から
1/Nの分周比の制御信号で分周器12を制御する。一
方、出力端子17の所望の出力信号f、とすると、この
出力信号f。
Conventionally, the configuration of a frequency synthesizer in which the frequency synthesis ratio is externally controlled is as shown in the circuit configuration diagram of FIG. 3, in which the input signal f! is input, and the frequency divider 12 is controlled by a control signal with a frequency division ratio of 1/N from the control terminal 18. On the other hand, if the desired output signal f of the output terminal 17 is assumed, then this output signal f.

を制御端子19がら1/Mの分周比の制御信号で分周器
13を制御する。この2つの分周器12゜13のそれぞ
れの出力信号の周波数f t / N  とfo/Mの
同一周波数同士が位相比較器14に位相比較され、低域
ろ波器15を経由して電圧制御発振器16の発振周波数
で。、ずなわち、f。
The frequency divider 13 is controlled by a control signal having a frequency division ratio of 1/M from the control terminal 19. The same frequencies f t /N and fo/M of the output signals of these two frequency dividers 12 and 13 are phase-compared by a phase comparator 14, and are subjected to voltage control via a low-pass filter 15. At the oscillation frequency of oscillator 16. , that is, f.

M/N f 1の位相を制御していた。ここで、周波数
合成比はM/Nである。周波数の制御ステップはMおよ
びNの値で変化するがM=N+1の時制御ステップは最
小となる、この時にNの値が]だけ変化するど、周波数
合成器の周波数変化は(])式%式% (1) (11式のように周波数合成比は、約1/N2変化する
。ずなわぢ5.従来の周波数合成器の制御可能な周波数
制御ステップの最小値は約1/N1であり、この制御ス
テップをより小さくするためにはNの値を大きくする必
要があった。
The phase of M/N f 1 was controlled. Here, the frequency synthesis ratio is M/N. The frequency control step changes depending on the values of M and N, but when M = N + 1, the control step is the minimum.At this time, the value of N changes by ], but the frequency change of the frequency synthesizer is expressed as (]) % Equation % (1) (As shown in Equation 11, the frequency synthesis ratio changes by approximately 1/N2. 5. The minimum value of the controllable frequency control step of the conventional frequency synthesizer is approximately 1/N1. In order to make this control step smaller, it was necessary to increase the value of N.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のディジタル制御周波数合成器は、周波数
合成器の制御可能な周波数制御ステップの最小値は約1
/N2となっているので、この制御ステップをより小さ
くするためにはNの値を大きくする必要があり1回路規
模が大きくなり、また位相同期回路の応答が遅くなり、
過渡的な変動が無視できなくなる欠点を有してい′1−
16〔課題を解決するための手段〕 本発明のディジタル制御周波数合成器は、周波数合成方
式により任意の周波数の出力信号を得る電圧制御発振器
を有するディジタル制御周波数合成器において、外部か
ら入力される信号の周波数分周比を設定する2つの制御
信号を出力する制御手段と、前記2つの制御信号のそれ
ぞれにより分周比を設定する第1−および第2の分周器
と、前記第1の分周器の分周出力信号と前記電圧制御発
振器の出力信号とを入力して周波数変換する周波数混合
器と、前記周波数混合器の低域出力信号を取り出す低域
ろ波器と、前記低域ろ波器の出力信号と前記第2の分周
器の分周出力信号とを入力して位相比較を行う位相比較
器とを有1−1前記位相比較器の制御信号を前記電圧制
御発振器に入力して位相同期ループを形成する。
In the conventional digitally controlled frequency synthesizer described above, the minimum value of the controllable frequency control step of the frequency synthesizer is approximately 1.
/N2, so in order to make this control step smaller, it is necessary to increase the value of N, which increases the size of one circuit and slows down the response of the phase locked circuit.
It has the disadvantage that transient fluctuations cannot be ignored.'1-
16 [Means for Solving the Problems] The digitally controlled frequency synthesizer of the present invention is a digitally controlled frequency synthesizer having a voltage controlled oscillator that obtains an output signal of an arbitrary frequency by a frequency synthesis method, in which a signal input from the outside is a control means for outputting two control signals for setting a frequency division ratio of the first and second frequency dividers; a frequency mixer that inputs and frequency-converts the frequency-divided output signal of the frequency converter and the output signal of the voltage controlled oscillator; a low-pass filter that extracts the low-frequency output signal of the frequency mixer; a phase comparator that inputs the output signal of the frequency divider and the divided output signal of the second frequency divider and performs phase comparison; 1-1 inputs the control signal of the phase comparator to the voltage controlled oscillator; to form a phase-locked loop.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1、図は本発明の第1の実施例の回路構成図である8
分周器1および分周器2は、入力端子〕、0の入力信号
f1を各々制御端子18.19の制御信号により1/N
、1/Mに分周する回路である。
First, Figure 8 is a circuit configuration diagram of the first embodiment of the present invention.
Frequency divider 1 and frequency divider 2 convert input signals f1 of input terminals] and 0 into 1/N by control signals of control terminals 18 and 19, respectively.
, 1/M.

周波数混合器3は、分周器1の出力信号の周波数fx/
Nと電圧制御発振器6の出力信号の周波数fOを周波数
混合し、各々の和と差の周波数成分を有する信号を出力
する。低域ろ波器4は周波数混合器3の出力の低周波側
を通する波器である。
The frequency mixer 3 adjusts the frequency fx/of the output signal of the frequency divider 1.
N and the frequency fO of the output signal of the voltage controlled oscillator 6 are frequency-mixed, and a signal having the sum and difference frequency components is output. The low-pass filter 4 is a filter that passes the low frequency side of the output of the frequency mixer 3.

位相比較器5は低域ろ波器4の出力の周波数f。The phase comparator 5 detects the frequency f of the output of the low-pass filter 4.

/N−foと分周器2の出力の周波数f1/Mの位相を
比較し、電圧制御発振器6の周波数制御信号を出力し、
位相同期ループを形成する。したがって入力周波数をf
lとし、出力周波数をfOとすると、位相同期ループが
正常に同期している時には、位相比較器5への周波数が
等しくなるので、fo + (1/N  1/M)fl
の関係が成立する。
/N-fo and the phase of the frequency f1/M of the output of the frequency divider 2 are compared, and a frequency control signal of the voltage controlled oscillator 6 is outputted,
Forms a phase-locked loop. Therefore, the input frequency is f
l and the output frequency is fO. When the phase-locked loop is normally synchronized, the frequencies to the phase comparator 5 are equal, so fo + (1/N 1/M)fl
The relationship holds true.

このように、周波数混合器と、2つの分周器の分周比N
とMの値を制御して、(1/N−i/M)の周波数合成
比を有する周波数合成回路を構成することができる。し
たがってM=N+1−のとき合成比は1./N(N+1
>となり、この時には周波数制御の最小ステップは約2
 / Nとなる。
In this way, the frequency mixer and the frequency division ratio N of the two frequency dividers
By controlling the values of and M, it is possible to configure a frequency synthesis circuit having a frequency synthesis ratio of (1/N-i/M). Therefore, when M=N+1-, the combination ratio is 1. /N(N+1
>, and in this case, the minimum step of frequency control is approximately 2
/ N.

次に本発明の第2の実施例を第2図の回路構成図により
説明する。第2図において、分周器1゜2、周波数混合
器3、低域ろ波器4、位相比較器5、電圧制御発振器6
、入力信号f1の入力端子]0、出力信号f。の出力端
子]7は第1の実施例と同じ構成である。第2の実施例
では分周器12の分周比N、Mの制御信号はディジタル
−ディジタル変換器7 (ROM)により制御される。
Next, a second embodiment of the present invention will be described with reference to the circuit configuration diagram in FIG. In FIG. 2, a frequency divider 1°2, a frequency mixer 3, a low-pass filter 4, a phase comparator 5, a voltage controlled oscillator 6
, input terminal of input signal f1] 0, output signal f. The output terminal] 7 has the same configuration as the first embodiment. In the second embodiment, the control signals for the division ratios N and M of the frequency divider 12 are controlled by a digital-to-digital converter 7 (ROM).

すなわち、外部から入力される制御信号7Aにより所望
の周波数合成器の動作条件情報が入力されると、あらか
じめ記憶されているこの条件の分周比N、Mが読み出さ
れて、分周器]、2が設定される。これ以降の動作は第
1、の実施例と同じである。
That is, when the desired operating condition information of the frequency synthesizer is inputted by the control signal 7A inputted from the outside, the pre-stored frequency division ratios N and M of this condition are read out, and the frequency divider] , 2 are set. The subsequent operations are the same as in the first embodiment.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は周波数混合器と2つの分周
回路の分周比NとMの値を制御L (1/N−1,/M
)の合成比を有する周波数合成回路を構成し、この分周
比N、Mの値を外部からの制御信号、又はあらかじめ記
憶されているディジタル−ディジタル変換器により設定
することにより、従来例の周波数合成比の最小ステップ
が1/Nであったのに対して、大幅に制御ステップを小
さくできる効果がある。
As explained above, the present invention controls the values of the frequency division ratios N and M of the frequency mixer and the two frequency divider circuits L (1/N-1,/M
), and by setting the values of the dividing ratios N and M using an external control signal or a pre-stored digital-to-digital converter, the frequency of the conventional example can be changed. While the minimum step of the synthesis ratio was 1/N, this has the effect of significantly reducing the control step.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例の回路構成図、第2図は
本発明の第2の実施例の回路構成図、第3図は従来のデ
ィジタル制御周波数合成回路の回路構成図である。 1.2・・・分周器、3・・・周波数混合器、4・・・
低域ろ波器、5・・・位相比較器、6・・・電圧制御発
振器、7・・・ディジタル−ディジタル変換器、10・
・・入力端子、17・・・出力端子、18.19・・・
制御端子。
Fig. 1 is a circuit diagram of a first embodiment of the present invention, Fig. 2 is a circuit diagram of a second embodiment of the invention, and Fig. 3 is a circuit diagram of a conventional digitally controlled frequency synthesis circuit. be. 1.2... Frequency divider, 3... Frequency mixer, 4...
Low-pass filter, 5... Phase comparator, 6... Voltage controlled oscillator, 7... Digital-digital converter, 10.
...Input terminal, 17...Output terminal, 18.19...
Control terminal.

Claims (1)

【特許請求の範囲】[Claims] 周波数合成方式により任意の周波数の出力信号を得る電
圧制御発振器を有するディジタル制御周波数合成器にお
いて、外部から入力される信号の周波数分周比を設定す
る2つの制御信号を出力する制御手段と、前記2つの制
御信号のそれぞれにより分周比を設定する第1および第
2の分周器と、前記第1の分周器の分周出力信号と前記
電圧制御発振器の出力信号とを入力して周波数変換する
周波数混合器と、前記周波数混合器の低域出力信号を取
り出す低域ろ波器と、前記低域ろ波器の出力信号と前記
第2の分周器の分周出力信号とを入力して位相比較を行
う位相比較器とを有し、前記位相比較器の制御信号を前
記電圧制御発振器に入力して位相同期ループを形成する
ことを特徴とするディジタル制御周波数合成器。
A digitally controlled frequency synthesizer having a voltage controlled oscillator that obtains an output signal of an arbitrary frequency by a frequency synthesis method, comprising: a control means for outputting two control signals for setting a frequency division ratio of a signal input from the outside; A frequency is determined by inputting first and second frequency dividers whose frequency division ratios are set by each of two control signals, and the frequency division output signal of the first frequency divider and the output signal of the voltage controlled oscillator. A frequency mixer for conversion, a low-pass filter for taking out a low-frequency output signal of the frequency mixer, and an output signal of the low-pass filter and a frequency-divided output signal of the second frequency divider are input. A digitally controlled frequency synthesizer comprising: a phase comparator that performs phase comparison; and a phase-locked loop is formed by inputting a control signal of the phase comparator to the voltage controlled oscillator.
JP2082666A 1990-03-29 1990-03-29 Digital control frequency synthesizer Pending JPH03280718A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2082666A JPH03280718A (en) 1990-03-29 1990-03-29 Digital control frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2082666A JPH03280718A (en) 1990-03-29 1990-03-29 Digital control frequency synthesizer

Publications (1)

Publication Number Publication Date
JPH03280718A true JPH03280718A (en) 1991-12-11

Family

ID=13780757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2082666A Pending JPH03280718A (en) 1990-03-29 1990-03-29 Digital control frequency synthesizer

Country Status (1)

Country Link
JP (1) JPH03280718A (en)

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