JPH03280720A - A/d converter - Google Patents

Abstract

PURPOSE:To facilitate error correction by incorporating a ROM storing a correction data correcting a capacitance error of a capacitor array. CONSTITUTION:When a capacitance error of capacitors 10a-10d is detected and a ground level is given to a 2nd electrode of a capacitor array 10 and a switch 15 is at an L level, a correction potential is obtained and stored in an EPROM 21. When the switch 15 is set to an H level, the switch is closed and a Vf is applied to a capacitor 18, the switch is opened to distribute the charge stored in the capacitor to vary the voltage Vf and the correction potential is stored in the EPROM 21. On the other hand, when a reference level is given to the 2nd electrode of the capacitor array 10, while the switch 15 is set to an L level, the correction potential is obtained and the correction potential to the capacitor is obtained from the switches 11, 13a-13d.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a charge redistribution type A/D converter having binary weighted capacitances A to A.

(Example) Prior Art FIG. 4 is a circuit diagram of a conventional charge redistribution type A/D converter, and shows the case of a 4-bit configuration.

In the case of a 4-bit configuration, the binary weighted capacitance array (1) is composed of five capacitors (la)" (Re) with capacitances of 8C, 4C, 2C, C, and C, respectively. J.J.
The first electrodes of each capacitor (1a) to (1e) are connected in common and grounded via a switch (2), and the second electrodes are respectively connected to switching switches f(3a) to (3e). be done. One of each changeover switch (3a)--(3e) is connected to the changeover switch (4), and the other is connected to the changeover switch (4).
connected to. , This changeover switch (4) has the reference voltage ■, inputted to one side, and the analog signal V□ inputted to the other H. , - each switch (3a) - (3e),
(4) and (2) are switched and controlled according to a switching control signal SC from a control logic (5) to be described later.

The 171r pole side of the capacitor array (1) is connected to the switch (2
) and to the inverting input side of the differential amplifier (6). The non-inverting input side of the differential amplifier (6) is grounded, so that if the potential Vx on the first electrode side of the capacitors A1 and A (1) is negative, the differential amplifier (6) The output of r
l'', and if positive, it becomes 1'OJ. [2] Then, the output of the differential amplifier (6) is input to the control logic (5), and the digital data p. A UT is created. Furthermore, in the control logic (5), a switching control signal ・sc,=sc, is created based on the output state of the differential amplifier clock, and each switch (3
a> to (3e>), (4) and (2).

Next, the operation of the circuit will be explained.

FIG. 5 is a timing diagram of the switch operation of FIG. 4.

Here, each switch (3a> to (3e) and (4) is switched to the L side as shown in FIG. 4 when each switching control signal SCl" is "rl", and to the L side when it is "0. It is assumed that the switch (2) is activated when the switching control signal S Cn is "1.".

First, during the zumbling period, the switching control signal SC,=-3C,
becomes 11'' and each switch (3/l)''-<3e)(
4) is switched to the 11 side and the switch (2) is turned on, the analog signal V IN is applied to the second electrode side of each of the 7 sensors (1a) to (1e), and each Capacitor (la) = (1e) Ni'r 8 CVIW, 4
CVow, 2 CVIW, CVll, l.

The amount of charge of CV and H is accumulated. Then, during the hold period, the switching control signal SC, ~□SC@ becomes 0, and each switch (3a) = (3e) is switched to the L side, and when the switch (2) is turned off, each capacitor (1a )〜・
(IC)'s second [pole side is pulled down to ground potential,
The potential on the first electrode side in the bloating state becomes 1. At this time, the total amount of charge accumulated in the capacitors (1a) to (1e) is 16CV□d, and this amount of charge is held.

Next, when the switch (3a) is switched to the L side again during the MSB determination period, the second electrode of the capacitor (1a) is
is applied, and the amount of charge in bold is distributed to each capacitor (1a) as -(le) during the hold period. This charge distribution is such that the potentials between the two electrodes of capacitors (1a) to (1e) are equal (7), and the potential of the second electrode of capacitor 1a is transferred to capacitors (ff, 13> and (le
) to the potential of the second electrode of 1. ■It is done so that it becomes higher. Therefore, since the capacitance of the capacitor (1a) and the total capacitance of the capacitors (1b) to (1e) are equal to each other, the potential (2) on the first electrode side is -2+yi+V. /2
Then, this Vx is compared with the ground potential in the differential amplifier (6〉).
If it is higher than 2, Vx becomes negative and the differential amplifier (6
) is "1.", and the control logic (5) determines that the MSB is "11". Conversely, analog signal V8. ．． isvlI
If [7 is low for /2, ■work becomes positive and MSB becomes "
0. It is determined that The control logic (5) determines the MSB and generates the switching control signal @'SCI at :#, and when the MSB is rl, the switching control signal SC3 is set to rl.
", and when it is "0.", it is set to "0." in the next period (B2 determination period).

MSB is 11. If it is determined that, during the continuation<B2 determination period, the switch (3a) remains on the H side and the switch (3b) is switched to the H side. Then V! is -v1yo+V m
/ 2 + V */ 4 Tonari, Ko(r) V x
(7) Depending on the sign or negative, the second bit (
B2) is determined. That is, if V x is higher than 3vyo/4, ■.

becomes negative and B2 is judged as ``1yo, ■8 is 3V.

If it is lower than /4, ■8 becomes positive and B2 becomes rO.

On the other hand, if the MSB is determined to be "0", the switch (3a) is switched to the L side and the switch (3b) is switched to the H side in the subsequent B2 determination period. Therefore, vx is −V
t w + V t/ 4 B2 is determined depending on the sign of this 1.

Hereinafter, the third bit (
B3) and LSB are determined in the same manner as B2. Therefore, by switching each switch (3a) to (3e) in order, ■8 is brought closer to the ground potential, and the final switch (
The states 3a) to (3e) are digital data D. It will represent UT. Therefore, the control logic (5) summarizes the MSB-LSB obtained serially in each determination period, and
BIT's digital data D. 0? Bind and output.

Such a charge redistribution type A/D converter is, for example, IE
E E J, 5olid 5tate C1rcui
ts, Vol, 5C-10, &6, 'A11-
MO5ChargeRedistributionA
analog-to-digital conversion
on Techniques-Partl”.

(8) Problems to be Solved by the Invention In the above-mentioned A/D converter, capacitance play (1)
Since the relative precision of the capacitance of each capacitor (1a) to (1e) is important, a plurality of unit capacitors with uniform capacitances are formed and these unit capacitors are connected in parallel according to a predetermined capacitance ratio. and each capacitor (la) ~ (
1e). For example, if the capacitance of a unit capacitor is C, 8, 4, and 2 unit capacitors are connected in parallel to form capacitors (1a), (lb), and (IC).

However, even when unit capacitors are connected in parallel to form each capacitor (1a) to (1e), each capacitor (1a) to (1e) may be
There is a problem in that an error occurs in the capacitance of (1e) and the linearity decreases. In particular, when attempting to obtain high resolution by increasing the number of bits, the influence of linearity is large, and there is a risk that the distortion rate will increase even though the resolution is high.

Therefore, the linearity is improved by correcting the capacitance using laser trimming and correcting the data itself using digital correction, but these corrections require expensive manufacturing equipment and large-scale logic circuits. This will lead to higher costs.

On the other hand, in the differential amplifier (6) that compares the 1st %j of capacitance play (1): pole side potential ■8 with the ground potential, -V
, /2 to V/2, therefore, two power supplies, one on the + side and one on the one side, are required to operate the differential amplifier (6). Such A/D converters are usually integrated circuits, and the fact that they require multiple power sources is an obstacle when integrated into ICs.

It is also possible to operate the differential amplifier (6) with a single power supply, but since the input range of the differential amplifier (6) is 1/2 that of dual-source operation, the input range of the analog signal is limited. There is a problem that becomes 1/2.

Therefore, the present invention uses a simple correction circuit to prevent linearity from decreasing due to element variations, and also provides a high-precision A/P that can operate with a single power supply without reducing the input range of analog signals. The purpose is to provide a D converter.

(2) Means for solving the problem The present invention was made in order to solve the above problem σ,
Its features include a capacitor array in which a plurality of binary-weighted capacitors are arranged in parallel, and a first reference potential is applied to one electrode of the capacitor array, and the converted voltage is applied to the other electrode. means for applying an analog signal of a value, means for applying the first reference potential to the other electrode side of the capacitor array, and means for applying the first reference potential to the other electrode side of the capacitor array for each capacitor. means for providing a second reference potential with a high potential or a third reference potential with a low potential, and a comparison circuit y for comparing the potential on one electrode side of the capacitor array with the first reference potential; Based on the comparison results of the comparator circuit, digital data is created sequentially from 1) to 2, and the storage capacity is stored from each means.・A control circuit that switches and controls the supply of each potential in (1), a correction capacitor installed in parallel with the above capacitor), and a correction that corrects the capacitance error of each capacitor in the capacitor array. a storage circuit that stores data; and a correction circuit that applies a potential to the correction capacitor according to the output of the comparison circuit and correction data read from the storage circuit to correct the potential on one electrode side of the container array. After applying the first reference potential and analog signal to both electrode sides of the capacitor array, one electrode side of the capacitor array is brought into a floating state, and the first reference voltage is applied to the other electrode side. When a potential is applied, if one electrode side of the capacitor array has a low potential with respect to the first reference potential, the second reference potential is applied, and if the potential is high, the third reference potential is The purpose is to sequentially supply the capacity to each of the containers , y1 to y.

(*) Effect According to the present invention, by learning a specific potential to the correction capacitor based on the correction data stored in the memory circuit, the positive or negative charge according to the correction data is corrected. # to capacity for
It is accumulated. Therefore, the potential on one electrode side of the capacitance value array increases or decreases depending on the amount of charge accumulated in the correction capacitor. error is corrected.

Further, analog signal values are compared between the third reference potential and the second reference potential, centering on the first reference potential which is an intermediate potential between the second reference potential and the third reference potential. I,
By setting the second reference potential to the voltage level and the third reference potential to the ground potential, it is possible to operate the comparator circuit in the range W and R, and the analog signal value comparison range is from the ground potential to the ground potential. up to the source potential.

(f) Example An embodiment of the present invention will be described with reference to the drawings.

Figure 1 is a circuit diagram of the A/D converter of the present invention (4 pins).
- Indicates the case of configuration.

The capacitor array 0,0) is composed of four capacitors with a capacity of 4C, 2C, C, and C<10a)=(10d), the 111th L pole is commonly connected, and a switch is connected to this first electrode. 11), a voltage (V, /2) which is 1/2 of the reference voltage v3 is applied to I7E. 1 ndenza for each (10
The second electrodes of a) to (10d) are connected to a changeover switch (1), respectively.
3a) to (13d), and these selector switches (
One of the switches 13n) to (13d) is connected to the changeover switch (14), and the other is connected to the changeover socket (15). Analog signals V IN and V7/2 are applied to the vJ changeover switch (14), and one of them is applied to the changeover switch (14).
3a)--(13d) are supplied to the capacitor. And one side of the changeover switch (15) has ■. is applied and the other is grounded. Each of these switches (13
A) to (13d), (14), (15), and (11) are switched and controlled in accordance with a switching control signal SC from control [1]7 (16) having the same configuration as that in FIG.

The first electrode side of the capacitor array (10) is a differential amplifier (17)
is connected to the inverting input side of the inverter, and its potential V is compared with v1/2 applied to the non-inverting input side. Therefore, if the T position ■ on the first electrode side of the capacitor array <lO> is lower than V, /2, the output of the differential amplifier (17) is rl, and if it is higher, r□,
The control 1"-ff chic (16) is the same as the control "1"-ff chic (5) in FIG. 4, and the explanation thereof will be omitted.

In addition, a correction capacitor (18) is connected in parallel to the blind lid array (10), and this -7 capacitor (18) is connected in parallel to the blind lid array (10).
) is connected to a correction data calculation circuit (20) via a D/A conversion circuit (19). Correction data calculation circuit (20)
is an EPROM (E
rasable Programmahle ROM
) (Zi) is connected, and the output of the differential amplifier (17) is also connected, and the correction potential ■
□, is configured to apply to the capacitor (18).

Therefore, the potential V errors on the i1E electrode side of the capacitor array (10) due to variations in the capacitance of each ':2 capacitor (1, Oa) to (10e) can be corrected. EPROM (21)
The correction data D□7 stored in E PRO
Crowded with M (21). Therefore, the correction data D
There is no need to provide IlEv again, and the peripheral circuitry for using the A/D converter can be simplified.

Here, the correction data D□7 is stored in the E P ROM (21).
In addition to this, EEPROM (Electronic
trically Erasable Program
mable ROM) and OT P ROM (One
If it is a nonvolatile memory that can write data such as Time Programmable ROM
It can be used instead of on the F ROM (21).

Next, the error detection operation will be explained.

FIG. 2 is a timing diagram of switch operation during error detection operation. During this error detection operation, the switch (1
4) is fixed to the L side, that is, the switching control signal SC4 is fixed to "0", and the analog signal VIN is not input.

The correction data D□7 for correcting errors of each capacitor (10a) to (10c) differs depending on whether the potential on the second electrode side of the capacitor play (10) is the reference potential V or the ground potential. , two data are given to each capacitor (10a) to (10c).

First, when detecting an error in the capacitor (1a), if the reference potential V is applied to the second electrode side of the capacitor array (10), the switching control signal SC5 becomes 11°, and the switch (15) becomes H. in the state where the switching control signal sc,
, sc become "1", the switch (11) is turned on, and the switch (10a) is switched to the H side. At this time, the switching control signals sc, , sc, and SC1 are "0", and the switches (13b) to (13d) are on the L side. continue,
After applying an arbitrary potential Vf to the capacitor (18), the switch (11) is turned off to bring the first electrode side of the capacitor array into a floating state.

Therefore, the switching control signal SCI is set to "0" and the switching control signal SC! , SCI, SC1 as ' I J ,
Switch (13a) to L side, switch o3b) ~ (1
3d) to the H side. Then, the capacitor (10a
) The electric charge accumulated in the capacitors (1b) to (1e
), and the error of the capacitor (10a) is distributed to the capacitor (18). That is, the capacitor (10a
) capacity (4C) and capacitors (10b) to (10d)
If the sum of the capacitances (2C+C+C=4C) is equal, the charge accumulated in the capacitor (10g) is transferred to the capacitor (10g)
Vx does not change even if distributed to b) to (10d), but if there is an error in the capacitance of the capacitors (10a) to (10d), v8 changes by that error. Therefore, the capacitor (
18> by varying the potential (Vf) applied to ■8
is made equal to the initial potential (V, /2). The amount of variation at that time becomes the correction potential ΔVah for the capacitor (10a), and this correction potential ΔVah is converted into a digital value and stored in the EPROM (21).

On the other hand, when the ground potential is applied to the second electrode side of the capacitor array (10), the switching control signal SC5 becomes r is repeated. Therefore, the capacitor (10
A correction potential ΔVal for a) is obtained, and E P RO
It is stored in M(21).

Next, when detecting an error in the capacitor (10b), if the reference potential is applied to the second electrode side of the capacitor array (10), the switching control signal SC6 becomes "1" and the switch (15) is set to the H side. , the switching control signals sc, s
c, becomes 11'', the switch (11) is turned on, and the switch (13b) is switched to the ``H side''.At this time,
The switching control signals sc, , sc, , sC6 are 10'', and the switches (13a), (13c), (13d) are L.
It's on the side. Subsequently, after applying Vf to the capacitor (18), the switch (11) is turned off, and the switching control signal S is then turned off.
Let C8 be r□, and switch control signals sc, , sc
,,sc, is set to ``1.'' and the charge accumulated in the capacitor (10b) is distributed to the capacitors (10c) and (10d).Then, in the same way as the error detection operation of the capacitor (10a), vx is set to the initial potential. (V, /2), and the amount of variation is the capacitor (1b)
is stored in the EFROM (21) as a correction potential Δvbh.

On the other hand, when the reference potential is applied to the second electrode side of the capacitor array (10), the switching control signal SC1 becomes r□, and the above-mentioned Δvbh
The same operation is repeated to obtain the capacitor (
13b) is obtained.

Below, in the same way, Tesui y f (11), (13
Switch a) to (13d) - [-1) De the (], O
Obtain correction potentials ΔVeh and ΔVcl− for e).

Next, we will explain the operation of the circuit. Figure 3 is a timing diagram of the switch operation in Figure 1.
, each switch (13a)~=(1,3e)(I4)(
1, 5) and (jl), the switching control signal SC, ``SC, KA' I J node S is the same as in the case of Fig. 3.
H@,'0. ,1'7) To! Assume that the switch is switched to the L side and the switch control signal SC, is ON when it is "1.".Here, the switch control signal SC, becomes "J" during the operation period, and the switch (1, 3d> is fixed to the H side.

During the lean-bring period, the switching control signal SC, -5C6
rl'', the switch (11) is turned on, each switch (13a)'' (13e) is switched to the H side, and v, I2 and ■8 are applied to each capacitor (10a) to (10d), Each conde>・()(10a) −<10d
) to 4C (VIN VR/2) and 2C respectively
(V□-V, I2), C(V, V=/2
) , C(VIN S), /2)<7)'%E load is accumulated.

In the subsequent -rMsB determination period, the switch (11) is turned off, the switch (14) is switched to the H side, and 6/2 is applied to the second electrode of the reception array (10). In the knee period, the switch (11) is turned on and the first electrode side of the hair array (10) is in the turned on state:
Therefore, the charge value is not accumulated in the capacitor A1-A (10) during the summing period and is held. :"Two charges are distributed to each :I capacitor (10a)" (1Oa), so V is V, I2 + Cvm/2-V I
N) Yell. So, :, and (8) are compared with Vl/2 and -TTMSB is determined. That is, if ■ becomes higher than Vll/2, V8 becomes lower than ■ and I2, and the differential amplifier (
The output of 17) is 11. Therefore, the control logic ("5) determines that the MSB is 1゛1", and conversely, VIW is v l/2
J, low C, V, is ■8. /2, and the output of the differential amplifier 17) becomes r□.

Therefore, MSB was judged as 10''.

If the switching control signal SC,i is determined to be 11, then it will be 1.If MSB is r□J, r□,
becomes. Until this MSB is determined, the switching control signal S
C, can be dorara. (The period indicated by the broken line in Fig. 2) Next, during the B2 judgment period ゛C, the switch (13a) is
7 side, and if M S B is rl, V is applied to the second electrode of the terminal (1 Oa),
If B is rO□ and k], the second electrode of the 11-denser (10a) is grounded. MsB is 'I J throat S VxhaV, I2-t-(V m/2 + V +t/4
V IN ), and second pitch 1=(B 2 ) is determined from the output of the differential amplifier (17). That is, V
If I N is higher than 3VIl/4 (N-), then ■, is V, I
2. The output of y' button (17) becomes '
X, t&-vT)B 2ka"i,,4 tjudgment-ph,V+r+ka3If lower than VR/4, ■1
becomes higher than V and I2, and the output of the differential amplifier (17) is determined to be "0.". CB2 is determined to be rg. At this time, the capacitor (18) has
(V ILEV - V */24 - ΔV ah) is applied, and the potential correction of (2)8 is performed.

On the other hand, MSB is 'OJ O)toa'XhX is vll
/2+(■-/4 VIN), and V,, becomes V1/
If it is higher than 4, ■8 is v l/2 J: lower &tteB2ka' 1,, conversely ■, if N is lower than Vll/4, Vx is higher than v, I2, and B2 is 10. When it is determined that the capacitor (18) has V, /2
+ΔVal (V++zv=V, /2+ΔVal) is applied to rail 7, switching control signal SC, is B2 (7) judgment 1+
- Therefore, if ]32 is 11'', it will be maintained at 11 degrees after the next B3 judgment period, and B2 will be 10. If so, it is maintained at 10.

1℃ during the B3 judgment period and the LSB judgment period),
The switches (13a) (13e) operate in the same way as the switch (12a) between B2 size judgment tJI [2, 3rd pitch I□
(B 3 ) and I25B are determined, and the husband's? Correction potentials Δν′ t)) i , Δ−Vhl, ΔVch, ΔVe corresponding to the capacitors (10b) (10e)
l is applied to the capacitor (18). The correction potential of J' is applied by adding 5,11 to 31 according to the determination result of the upper bit and applying it to -[-:lnden (,!-<18). In other words, the correction data is 1" 1 circuit (20)
is based on the judgment result of each bit and adds the correction data of 1゛[each = j〉・Denji-(10a)・～be10e）17
, and the added value is vY.

It is configured so that the value equivalent to I2 is added 12 and sent to the capacitor (18) via the D/A converter, and switches (13p) to (13c) are placed on the H side during the business card period. , a capacitor to which a potential of V/2 is applied (
One sum of the correction potentials 10a) to (10c) is applied to the capacitor (18). Therefore, τ correction is applied to the capacitors (10a) to (10c) in each determination period, and a digital signal with good linearity is obtained with respect to the input analog signal (2). , JA can be obtained.

In this embodiment, a case of a 4-bit configuration is illustrated, but a 5-bit configuration can be achieved by adding a capacitor or by combining with an A/D converter using other methods, such as a comparison method using a resistor string. The above can be easily accomplished.9 (G) Effect of the Invention According to the present invention, since the ROM containing the correction data for correcting the capacitance error of the capacitor array is built-in, it is easy to correct the error. It is possible to improve the linearity and reduce the distortion rate. In addition, since there is no need to detect errors in the capacitor array every time an A/D conversion operation is performed,
The rise of the A/D converter becomes extremely fast, peripheral circuits for error detection can be omitted, and a reduction in circuit scale can be expected. Therefore, an A/D converter with excellent linearity can be realized without requiring a complicated and large-scale circuit configuration.

Furthermore, since the comparison operation of the differential amplifier can be performed in the range from the ground potential to the reference potential, it is possible to operate with a single power supply, and the input range of the differential amplifier is sufficient, allowing the circuit to It is possible to prevent reduction in dynamic range.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the A/D converter of the present invention, Figure 2 is a timing diagram of error detection operation, Figure 3 is a timing diagram of A/D conversion operation, and Figure 4 is a conventional A/D converter. Circuit diagram, 5th
The figure is an operation timing diagram. (1), (10)-, capacitive array, (la)~(
le), (10a) to (10d)... Capacitor, (2), (11)... Switch, (3a) to (3e
), (4), (13a) to (13c), (
14), (15)=-changeover switch, (5),
(16)...Control logic, (6)(17)...
Differential amplifier, (18)... Capacitor, (19>...
-D/A conversion circuit, (20)...Correction data calculation circuit, (21)...E F ROM.

Claims (3)

[Claims] (1) A capacitor array in which a plurality of binary-weighted capacitors are arranged in parallel, and a first reference potential is applied to one electrode of the capacitor array, and an analog signal of the converted value is applied to the other electrode. means for applying the first reference potential to the other electrode side of the capacitor array; and means for applying the first reference potential to the other electrode side of the capacitor array for each capacitor at a higher potential than the first reference potential means for applying the second reference potential or a third low potential reference potential; a comparison circuit for comparing the potential on one electrode side of the capacitor array with the first reference potential; and based on the comparison result of the comparison circuit. a control circuit that creates digital data in order from the most significant bits and switches and controls the supply of each potential from each of the means to the capacitor array; a correction capacitor arranged in parallel with the capacitor array; a memory circuit that stores correction data for correcting the capacitance error of each capacitor; and a potential that is applied to the correction capacitor in accordance with the output of the comparison circuit and the correction data read from the memory circuit so that the potential on one electrode side of the capacitor array is a correction circuit for correcting, and after applying the first reference potential and the analog signal to both electrode sides of the capacitor array, one electrode side of the capacitor array is brought into a floating state, and the other electrode side is set in a floating state. When the first reference potential is applied to the first reference potential, if one electrode side of the capacitor array has a lower potential than the first reference potential, the second
If the reference potential becomes high, the third reference potential is sequentially supplied to each capacitor of the capacitor array.
/D converter. (2) The A/D converter according to claim 1, wherein the first reference potential is an intermediate potential between the second reference potential and the third reference potential. (3) An A/D converter, wherein the storage circuit is a read-only memory in which data can be written.