JPH03280722A - Digital analog conversion circuit - Google Patents

Abstract

PURPOSE:To decrease delay in an output analog voltage by revising a duty ratio by a value resulting from application of a prescribed function to a difference for one period of a pulse width modulation wave. CONSTITUTION:A microcomputer 15 outputs a setting value after setting of revision to a bus 13, calculates a difference between the setting value after revision and the setting value before revision and outputs the difference to a bus 14. Thus, a difference is set to a preset counter 7, a code latch 9 latches a low level to set a code signal line to a low level and a trigger signal is outputted to a trigger signal line 4. The clock circuit is synchronized by the trigger signal, the preset counter 7 starts counting and a high level timer signal is outputted to a timer signal line 8. Moreover, a low level is outputted to an output signal line 12 and a pulse width of a signal on the output signal line 12 is reduced for 1PWM period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PWM type digital-to-analog conversion circuit, and more particularly to a digital-to-analog conversion circuit that uses a low power PWM wave after smoothing it with a filter.

[Conventional technology]

Such a conventional digital-to-analog conversion circuit (hereinafter referred to as D
There are various types of A/A conversion circuits, but pulse width modulation (hereinafter referred to as PWM) circuits are particularly used for applications such as motor control.

Since this PWM circuit is constituted by a digital circuit, it is miniaturized, has good conversion accuracy, and is suitable for integration into an integrated circuit. For this reason, it is widely used in integrated circuits for servo control. Also, when driving a high-power motor with PWM waves, the PWM waves are applied directly to the motor, but in the case of a motor used in a mechanism that records and reproduces signals, such as a RAD motor to rotate a VTR, PWM waves are applied directly to the motor. Apply after smoothing with a filter. This is to prevent the PWM wave ripple from causing jitter in the recording/reproduction signal, the motor beat, or the emission of unnecessary radio waves.

To smooth the PWMe described above, PWM iteration 1-
A filter with a time constant of at least 10 times the period must be connected. For example, in the servo control circuit for the rotation/rad motor of the VTR described above, the PWM repetition period is about 50 [Iμs] (repetition frequency 20 [kHz]) due to hardware limitations. Therefore, the time constant of the smoothing filter is 500 μS or more. However, in the servo control of the rotation/rad motor of a VTR, the sampling period is required to be 1 [mS] or less.

Therefore, the delay due to the filter time constant cannot be ignored,
This has an adverse effect on the servo control characteristics.

FIG. 10 is a timing diagram after PWM wave smoothing for explaining an example of such a conventional technique.

As shown in FIG. 10, such a waveform has a time constant τ10T (
T is the PWM repetition period) first-order filter l/c
1 + jwτ). For example, the servo control circuit for rotation, control, and rotation is as follows:
De of PWM wave when locked.

Since the design is such that the duty ratio is around 50%, the operation when the duty ratio is around 150% will be described here.

In Fig. 10, at time O, the Teuty ratio is 50
[%] to 52[%], and in order for the average value after smoothing to sufficiently approach 52[%], a time of approximately twice τ, that is, 20T or more is required. ,1-Karuni,
Since the above-mentioned servo control sampling period], [mS] is 20 times the PWM repetition 1-frequency T=50 [μS], the delay of the filter is equal to the sampling period. For this reason, the phase wrap-around cannot be ignored, and it is not only impossible to achieve desired servo characteristics, but also causes problems such as loss of stability of the servo system.

[Problems to be Solved by the Invention 1] The conventional D/A converter circuit is configured to generate a PWM wave having a tute ratio proportional to a set value, and decimate it with a filter to obtain an analog voltage. It has become. Therefore, when changing the set value, there is a drawback that the output analog voltage is delayed by the time response of the smoothing filter.

An object of the present invention is to provide a D/A conversion circuit that can reduce the delay in the output analog voltage when changing the set value.

[Means to solve the problem]

The D/A conversion circuit of the present invention includes a pulse width modulation circuit that generates a pulse width modulation wave having a tute ratio proportional to a set value, and a pulse width modulation circuit that generates a pulse width modulated wave having a tute ratio proportional to a set value. A difference calculation circuit that generates a difference, and a period of one cycle of the pulse width modulated wave immediately after changing the set value from the first value to the second value is a value obtained by applying a predetermined function to the difference. and a circuit for changing the duty ratio.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a D/A conversion circuit showing a first embodiment of the present invention.

As shown in FIG. 1, the present embodiment starts from a PWM circuit 1 with a repetition period T1. High active P at -50 [μS]
The WM wave is output to the PWM signal line 2.

This PWM circuit 1 has a numerical value n (n==o, ], 2.
-100), P with duty ratio n [%]
Outputs WM waves. Also, the edge detection circuit 3
The rising and falling edges of the M wave are detected 17, the logic is taken, and a trigger signal is output to the trigger signal line 4. When a code signal line 10 connected to a code latch 9 (described later) is at a high level, a falling edge of the PWM wave is detected 17;
Conversely, when the signal is at low level, a rising edge is detected. The clock circuit 5 connected to the trigger signal line 4 has a period TC=
Generates a clock signal of 5 [μS] 7, and connects the trigger signal line 4
When a trigger signal is input from , the clock signal is synchronized with the trigger signal. The preset force 1 Kuntahu is a decrement counter that decreases the value by 1 in response to the clock signal from the clock signal line 6, and starts counting operation by the trigger signal from the trigger signal line 4, and when the value reaches O. Stop counting operation. A high-level timer signal is output to the timer signal line 8 only from the start of the counting operation to the stop of the counting operation. Further, the sign latch 9 is a latch that stores the sign of the preset value set in the preset counter 7, and when the sign is positive, a high level is used, and when the sign is negative, a low level is used as a code signal. Output on line 10.

The selection circuit 11 selects either the PWM wave sent to the PWM signal line 2 or the code signal sent to the code signal line 10 based on the timer signal from the timer signal line 8, and sends the output signal to the output signal line 12. Output to. Furthermore, the microcomputer 15 includes a difference calculation circuit, and while outputting the value (data) to be set in the PWM circuit 1 to the bus 13, the microcomputer 15 uses the difference calculation circuit to calculate the difference between the previous set value and the current set value. Moreover, the result is outputted to the bus 14. At this time, the absolute value of the difference is set in the preset counter 7, and the sign is set in the code latch 9. At this time, when the sign is positive, a high level is stored in the sign latch 9, and when the sign is negative, a low level is stored in the sign latch 9.

Although not shown in FIG. 1, a filter for smoothing is connected to the output signal line 12. This filter is a primary filter with a time constant τ of τ=10 TPWM=500 [μS].

In the D/A conversion circuit configured as described above, the period TC"5 [μS] of the clock signal is the time constant τ of the filter = 500.
This is a numerical value calculated based on [μS] etc., and the calculation method will be described later.

FIG. 2 is a timing diagram for explaining the operation of the conversion circuit in FIG. 1.

As shown in FIG. 2, this timing is the operation timing when changing the duty ratio of the PWM wave from 50% to 52%. In order to set the duty ratio of this PWM wave to 52%, a value of 52 is set in the PWM circuit 1. On the other hand, the microcomputer 15 outputs the changed set value 52 to the bus 13, and the difference 52-50 between the changed set value 52 and the unchanged set value 50=+
2 and outputs this difference value to the bus 14 at time tl. Therefore, the preset counter 7 is set to 2, and the code latch 9 is latched at a high level.
The code signal line 10 is set to high level.

Next, the next PWM cycle starts from time t2.

At this time, the PWM wave on the PWM signal line 2 has a duty ratio of 52.
[It is %co.] However, since the code signal line 10 is at a high level and the edge detection circuit 3 is set to detect falling edges, a trigger signal is output to the trigger signal line 4 at the falling time t3 of the PWM signal line 2. Since the clock circuit 5 is synchronized by this trigger signal, the preset counter 7 starts a time counting operation. Therefore, a high-level timer signal is output to the timer signal line 8 for 2To=10 μS from time t3.

Next, when the timer signal line 8 is at a high level, the selection circuit 11 has selected the code signal line 10, and therefore outputs a high level to the output signal line 12 from time t3 to time t4. Therefore, during the IPWM cycle from time t4 to time t, the pulse width of the PWM wave on the output signal line 12 is 2TC.
= 10 [μS] increase.

FIG. 3 is a timing diagram similar to FIG. 2 for explaining the operation of the conversion circuit in FIG. 1.

As shown in FIG. 3, this timing is the operation timing when changing the duty ratio of the PWM wave from 520% to 490%. To set the duty ratio of this PWM wave to 49%, set the PWM circuit circuit value to 49. On the other hand, the microcomputer 15 outputs the changed setting value 49 to the bus 13, calculates the difference 49-52=-3 between the changed setting value 49 and the unchanged setting value 52, and calculates this difference value. It is output to the bus 14 at time t6.

Therefore, the preset counter 7 is set to 3, the code latch 9 latches a low level, and the code signal line 10 is set to a low level.

Next, since the code signal line 10 is at a low level and the edge detection circuit 3 is set to detect rising edges, a trigger signal is output to the trigger signal line 4 at the rising time t7 of the PWM signal line 2. This trigger signal causes the clock circuit 5 to
are synchronized, so the digital counter 7 starts its timekeeping operation. Therefore, from time t7 to 3T9 d151]μ
A high-level timer signal is output to the timer signal line 8 between the two terminals.

Further, since the code signal line 10 is at a low level, a low level is outputted to the output signal line 12 from time t to time t8. Therefore, 1. from time t7 to time t. l) During the WM period, the PWM of the output signal line 12
The pulse width is decreased by 3Tc=15 [μS].

FIG. 4 is an operation timing diagram when a smoothing filter is connected to the output line shown in FIG. 1.

As shown in FIG. 4, this operation timing represents the waveform after smoothing when the output signal line 12 is connected to the output signal line 12 for smoothing in the circuit 17 described above. Such a smooth waveform is PW
When changing the M wave tutee ratio from 501% to 52%, it also changes from 521% to 49%1.
Even in the case of -, the desired voltage can be reached in about two cycles of the PWM wave, and the delay due to the filter is much smaller than that of the conventional example.

For example, when the above-described D/A conversion circuit is used in a servo control circuit for a rotary-rad motor of a VTR, the problem of phase wraparound caused by a delay caused by a filter is eliminated, and good servo characteristics can be obtained.

In addition, in the above example, the time constant τ of the filter is equal to the PWM period T.
81. Although the description has been made regarding a first-order filter that is 10 times larger than the above, even if the time constant or order of the filter is different from this example, it can be handled simply by changing the oscillation period of the clock circuit 5.

Then - as an example, the time constant τ = k T pw, .
For the case of a constant) 01st-order filter, ri1+''ωkT,, □,.

A method for calculating the oscillation period Tc of the lock circuit 5 will be explained with reference to FIG.

FIG. 5 is a characteristic diagram of the PWM wave in FIG. 1 and the waveform after passing through the ]-order filter.

It becomes like A characteristic and B characteristic. However, T PW
Since M < τ, it can actually be approximated by straight lines C and D. Also, since T p =, t <: τ, y, ξ)·2. Therefore, by substituting 'j1=Y2=Y (Tutee ratio) into the straight lines C and D, we get the following equation. This equation (1) represents the straight line C (-1 or (2)
The formula represents straight line. Therefore, the PWM wave falls at high 1/be.

In the circuit shown in FIG. 1 described above, when the set value of the PWM circuit 1 is increased by the difference m, the high level time of the PWM wave increases by mTc, and the low level time decreases by mTc. Therefore, the waveform after smoothing will rise by . On the other hand, since increasing the PWM circuit film constant value by km is equivalent to increasing the average value by 100 (100 is the resolution of the PWM wave), the following equation is obtained. T, two TP...
...(3)00, the time delay caused by the filter described in this embodiment is reduced.

Further, although the case where the set value is increased has been described here, equation (3) can be similarly obtained when the set value is decreased.

Therefore, the oscillation period T of the clock circuit 5. By setting the value of Equation (3), it is possible to correspond to an arbitrary first-order filter. Furthermore, even when the order of the filter is other than the first order, the response to the PWM wave may be approximated by a straight line, and the relationship between TC and Tpw may be derived in the same manner as in the method described above.

In short, the D/A conversion circuit of this embodiment can greatly reduce the delay caused by the PWM wave smoothing filter, and can be used for servo control, etc., which had to limit performance due to the delay caused by conventional filters. The performance can also be improved in applications.

FIG. 6 is a block diagram of a D/A conversion circuit showing a second embodiment of the present invention.

As shown in FIG. 6, in this embodiment, a PWM circuit 101 generates a PWM wave with a tutey ratio proportional to the set value of a modulo register 103 or 104, and outputs it to an output signal line 107. When this set value is n, a PWM wave with a duty ratio of n[%] is generated. The selection circuit 102 selects the modulo register 103 when the selection signal line 108 is at a high level, and selects the modulo register 104 when it is at a low level. The modulo registers 103 and 104 are both registers that hold a modulo value to be set in the PWM circuit 101. Further, the microcomputer 105 includes a difference calculation circuit as in the first embodiment described above, and sets the value to be set in the PWM circuit 101 in the modulo register 104 and the value to be set in the modulo register 104. Previous setting value - current setting value]×lO+current setting value (4) Set the value described in equation (4), and set the result in the modulo register 103. At this time, a pulse is simultaneously output to the write signal line 109. Incidentally, here, the count 10 in equation (4) is Tc'' in the first embodiment.
This is for the same reason as TPWM. Furthermore, the 0 one-shot circuit 106 is a circuit that generates a pulse with a width of one PWM wave cycle in synchronization with the PWM wave on the output signal line 107 and outputs it to the selection signal line 108. That is,
When a pulse is input from the write signal line 109, a high-level pulse is output, and at other times, a low-level pulse is output.

FIG. 7 is a timing diagram for explaining the operation of the conversion circuit in FIG. 6.

As shown in FIG. 7, this example shows the timing when changing the duty ratio of the PWM wave from 50% to 52%. First, at time t1, the microcomputer-05 sets the numerical value 52 in the modulo register 04, and based on the above-mentioned equation (4), (52-5
0) Calculate X 10+5272 and set 72 in modulo register 03. At this time, a pulse is output to the write signal line 109. Next, from time t2 to t3,
That is, in the next PWM cycle, the one-shot circuit 106 outputs a high level to the selection signal line 108. This results in
The selection circuit 102 selects the modulo register 103 from time t2 to t3, and selects the modulo register 104 after time t3.

Therefore, the PWM waveform of the output signal line 107 has a duty ratio of 72% in one cycle from time t2 to t3,
After time t3, the duty ratio becomes 52%. In short, this waveform is similar to the waveform of the pressure signal line 12 in FIG. 2 described above.

FIG. 8 is a timing diagram for explaining an example of the operation of the conversion circuit in FIG. 6, which is different from that in FIG. 7.

As shown in Figure 8, the duty ratio is changed from 520% to 4
This is the timing to change to 9[%].

The operations of the microcomputer 105, modulo registers 103, 104, etc. in this example are the same as in the case of FIG. 7 described above, so a description thereof will be omitted. In this case, the duty ratio is 22 [%] during one period of the PWM wave from time t5 to t6, and the duty ratio is 49 [%] after time t6.

FIG. 9 is an operation timing diagram when a smoothing filter is connected to the output line shown in FIG. 6. As shown in Figure 9,
Here, the duty ratio is 50% (52%) → 49
It shows the smooth waveform when changed to [%]. The smoothing filter described above is the same as the conventional example, but
In this embodiment as well, the same effects as in the first embodiment described above can be obtained.

Furthermore, in the first embodiment, when the smoothing filter was changed, it was necessary to change the clock circuit 5, but in the second embodiment, it is only necessary to change equation (4). . That is, this embodiment has the advantage that it is possible to adapt to changes in the filter by changing the program of the microcomputer 105.

In the first and second embodiments described above, an example was explained in which the pulse width of the PWM wave is changed by a value proportional to the amount of change in the duty ratio, but this approximates the response waveform of the filter to a straight line. This is based on a number of assumptions. That is, in the second embodiment, Mike r here] / computer 105
If the calculation speed is sufficiently fast, a method may be used in which the response waveform of the filter is precisely calculated. In this case, even if the time constant τ of the filter is not sufficiently large in relation to the PWM period TP, the same effect as in this embodiment can be obtained.

〔Effect of the invention〕

As explained in explanations 1 to 1 above, the D/A conversion circuit of the present invention has a circuit that increases or decreases the duty ratio according to the amount of change only during one cycle of the PWM wave when changing the duty ratio. PW the time delay due to the filter for smoothing
This has the effect of being able to be reduced to about two cycles of the M wave. In particular, since this time delay is about 1/10 of the conventional one, the characteristics can be greatly improved for servo control and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a D/A conversion circuit showing a first embodiment of the present invention, FIGS. 2 and 3 are timing diagrams for explaining the operation of the conversion circuit in FIG. 1, and FIG. The figure shows a smoothing filter connected to the output line shown in Figure 1.1. Tagi's operation timing diagram, Figure 5 is the PW in Figure 1.
A characteristic diagram of the M wave and the waveform after passing through the first-order filter, FIG. 6 shows the second embodiment of the present invention.
11 The ivy diagram, FIGS. 7 and 8 are timing diagrams for explaining the operation of the conversion circuit in FIG. 6, respectively.
Figure 9 shows a smoothing filter connected to the output line shown in Figure 6.
FIG. 10 is a timing diagram after PWM wave smoothing to explain a conventional example. 1...PWM circuit, 2...PWM signal line, 3...edge detection circuit, 4...I-
') G signal line, 5... Clock circuit, 6...
... Clock signal line, 7 ... Preset counter, 8 ... Timer signal line, 9 ... Code latch, 10 ... Code signal line, 11・・・・・・
...Selection circuit, 12...Output signal line, 13゜1
4...Bass, 15...Microphone I:L)/View evening, 101...PWM circuit, 10
2...Selection circuit, 103.104...Modulo register,...-Microcomputer, 1
06...Shop) circuit, 107...Output signal line, 1...Selection signal line, 109...
・Light signal line. Wa

Claims (1)

[Claims] 1. A pulse width modulation circuit that generates a pulse width modulated wave having a duty ratio proportional to a set value;
a difference calculation circuit that generates a difference when changing from a value to a second value, and a difference calculation circuit that generates a difference when changing the set value from the first value to the second value; and a circuit that changes the duty ratio by a value obtained by applying a predetermined function to the difference. 2. A digital-to-analog conversion circuit, wherein the predetermined function according to claim 1 is a direct proportional function.