JPH03280740A - Clock changeover circuit - Google Patents

Abstract

PURPOSE:To make a output clock signal of a changeover circuit normal and to attain the normal circuit operation by synchronizing an optional asynchronizing signal of a switching signal with a signal system to be switched and with a signal at the outside of a band of a difference of signals to be switched. CONSTITUTION:Reception circuits 1, 2 receive a subsequent clock signal and apply recovery of the reception clock synchronously therewith or phase locked loop oscillation and output output signals a, b to a changeover circuit 3 and a NOR circuit d. Then an optional asynchronizing reception circuit switching signal (c) is inputted to a D F/F5, and the F/F5 outputs a switching signal (d) to the circuit 3 by using the output of the circuit 4 as a clock pulse. The circuit 3 switches the signals a, b by using the signal (d) to obtain an output clock signal (e). Thus, the output clock signal of the changeover circuit is made normal and the operation of the circuit is made normal even when an asynchronizing switching signal is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock switching circuit, and more particularly to a clock switching circuit that switches and outputs a clock signal using an asynchronous switching signal.

[Conventional technology]

FIG. 3 is a block diagram of an example of a conventional clock switching circuit, in which outputs a and b of two receiving circuits 11 and 12 that receive dependent clocks are switched by a switching circuit 13 using an arbitrary asynchronous receiving circuit switching signal C. It has become.

[Problem to be solved by the invention]

The conventional clock switching circuit described above uses any receiving circuit switching signal as it is as a switching signal for the switching circuit.
If there is a difference between the output signals of the two receiving circuits, there is a drawback that when switching is performed between the differences, the output clock signal of the switching circuit will have cracks or cracks, making it impossible for the device to operate normally. .

[Means to solve the problem]

The clock switching circuit of the present invention includes two receiving circuits that receive dependent clock signals input from either one system or two systems and perform regeneration of the dependent clock or phase synchronized oscillation, and NOR that manually converts the output signal
0797170 that operates an asynchronous receiving circuit switching signal using the output of the circuit and the NOR circuits 1 and 2 as clock pulses.
71 circuit, and a switching circuit for switching the output signals of the two receiving circuits using the output of the 079717071 circuit. Refer to and explain.

FIG. 1 is a block diagram of an embodiment of the clock switching circuit of the present invention, and FIG. 2 is a time chart 1 for explaining the operation in FIG.

In FIG. 14, the two receiving circuits 1.2 input the dependent clock signal, perform regeneration or phase synchronized oscillation of the received clock synchronized with this, and input the output signal 4Ja, 1:) to the switching circuit 3. At the same time, the NOR circuit 4 is manually powered. Here, it is assumed that there is a difference t between the output signals a11) as shown in FIG. Input an arbitrary asynchronous receiving circuit switching signal (to the 079717071 circuit (hereinafter TDF, /F) 5, and input the output of the NOR circuit 4 to the 11' knock pulse and !-, and the DF/F5 converts the switching signal ((to the switching circuit 3.The switching circuit 3 uses this switching signal d to output the signal to the receiving circuit 1-1.
The output clock signal e is obtained by switching the two output signals a and b. In this embodiment, as shown in FIG. 2, the operation logic of the switching circuit 3 is that the switching signal d is at a low level (hereinafter referred to as L>, the receiving circuit) and the output signal a.

is selected, and when it is at a high level (hereinafter referred to as H), the output signal [) of the receiving circuit 2 is selected.

〔Effect of the invention〕

As explained above, the present invention synchronizes any asynchronous signal of the switching signal with the signal system to be switched, and
By synchronizing outside the difference range between the two switched signals, the output clock signal of the switching circuit is always normalized, so even if any arbitrary asynchronous switching signal is input manually, the device can operate normally. effective.

[Brief explanation of drawings]

FIG. 1 shows block 17 of an embodiment of the clock switching circuit of the present invention.
..., 2, Fig. 2 is a time chart for f', -, which explains the operation shown in Fig. 1. Fig. 3 is a block diagram of an example of a conventional clock switching circuit. be. 1.2.11.12...Reception circuit, 3, 13. Switching circuit, 4. NOR circuit, 5...979717071
71(1)Fren'F), a, b-receiving circuit], 2 output signal, C-asynchronous receiving circuit switching signal, d--switching signal, e--output clock signal.

Claims (1)

[Claims] Two receiving circuits that receive dependent clock signals input from either one system or two systems and reproduce the dependent clock or perform phase synchronized oscillation, and a NOR circuit that receives the output signals of these two receiving circuits as input. , a D flip-flop circuit that operates an asynchronous receiving circuit switching signal using the output of this NOR circuit as a clock pulse, and a switching circuit that switches the output signals of the two receiving circuits using the output of this D flip-flop circuit. Clock switching circuit.