JPH03280741A - Clock extraction circuit - Google Patents

Abstract

PURPOSE:To improve the general-purpose performance of the circuit by applying phase-locked operation to a signal from an optional frequency signal source and using a tuner so as to extract a stable clock. CONSTITUTION:An input signal from a frequency signal source 1 is inputted to a comparator circuit 21 in a digital PLL circuit 2, in which phase-locking is implemented. A variable frequency divider 22 in the circuit 2 revises a frequency division ratio corresponding to the input signal frequency and inputs its output to the comparator circuit 21. The circuit 2 applies phase locking to an optional frequency. Then an output signal of the comparator circuit 21 is inputted to a fixed frequency divider 3, where the signal is frequency-divided and phase fluctuation is suppressed in the signal by a tuner 4 and a resulting clock is extracted. Thus, the general-purpose performance of the circuit is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock extraction circuit, and more particularly to a clock extraction circuit for extracting a clock component from a received signal in a device synchronized to a frequency signal source.

[Conventional technology]

Conventionally, this type of clock extraction circuit has been created as a dedicated circuit for extracting a clock component from a specific frequency signal source.

[Problem to be solved by the invention]

The conventional clock extraction circuit described above is a dedicated clock extraction circuit for each frequency signal source, so if the frequency of the signal source is different, the same circuit cannot be used, and a new dedicated circuit must be created. Therefore, it has the disadvantage of lack of versatility.

[Means to solve the problem]

The clock extraction circuit of the present invention includes a comparator that receives a signal from an arbitrary frequency signal source as one input, and a variable frequency divider that can change the division ratio according to the frequency of the output signal of the comparator. a digital PLL circuit that uses the output signal of the variable frequency divider as the other input of the comparator; a fixed frequency divider that divides the frequency of the output signal of the comparator; and a clock that is derived from the output signal of the fixed frequency divider. and a tuner that extracts and outputs the extracted information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the clock extraction circuit of the present invention.

In FIG. 1, first, an input signal from a received frequency signal source is phase-locked to one input of a comparator 2 in a digital PLI circuit 2.

Here, digital P1, variable frequency divider 22 in L circuit 2
is capable of changing the division ratio according to the input signal frequency, and its output is used as the other input of the comparator 21.

This P1. ,, In the I-circuit 2, phase synchronization can be applied to any frequency without limiting it to a specific frequency.

The output signal of the phase-synchronized comparator 21 is a digital P
Frequency f of master clock 5 that controls L L circuit 2
Since jitter (phase fluctuation) depending on O occurs, various problems arise when synchronizing the device using the normal signal as a reference.Therefore, in this embodiment, the output signal of the comparator 21 (
Frequency f. /2) is input to the fixed frequency divider 1- and the frequency 1-
1. Further, this frequency-divided signal is subjected to noise suppression by a tuner 1) and extracted as a clock. In addition,
The frequency division ratio of the fixed frequency divider 3 is usually selected to a value that facilitates the implementation of the tuner 4. [Effects of the Invention] As explained above, according to the tarokk extraction circuit of the present invention, Since it is possible to phase synchronize signals from arbitrary frequency signal sources and extract a stable L = clock using a tuner,
This has the effect of increasing the versatility of the circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the clock extraction circuit of the present invention. ]... Frequency signal source, 2... Digital PLL circuit 43... Fixed frequency divider, 4... Tuner, 5... Master clock, 2]... Comparator, 22...・Variable frequency divider.

Claims (1)

[Claims] The output signal of the variable frequency divider is composed of a comparator whose one input is a signal from an arbitrary frequency signal source, and a variable frequency divider whose frequency division ratio can be changed in accordance with the frequency of the output signal of the comparator. a digital PLL in which the other input of the comparator is
A clock extraction circuit comprising: a fixed frequency divider that divides the output signal of the comparator; and a tuner that extracts and outputs a clock from the output signal of the fixed frequency divider.