JPH0328083B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frequency synthesizer having means for modulating a high frequency signal based on a low frequency signal written in advance in a memory to obtain a high frequency signal with desired sideband waves. .

(Prior art) An MRI device (magnetic resonance imaging device) superimposes a linear magnetic field gradient on a static magnetic field to give a magnetic field with a different strength depending on the position. Tomographic images at different positions are obtained by changing the resonance frequency. Therefore, many high-frequency signals with different frequencies are required,
A frequency synthesizer is used as a high-frequency power source.

The following specifications are required for frequency synthesizers used in MRI equipment.

(1) Oscillate with a stable frequency and variable range.

(2) Amplitude modulation can be performed to create an excitation signal.

(3) The relative phase of temporally oscillating signals can be controlled.

A frequency synthesizer shown in FIG. 6 is a device that satisfies the above requirements. In the figure, 1 is a frequency synthesizer for transmission to apply a high-frequency magnetic field to the subject, which outputs the center frequency of the high-frequency signal.
It is separated into ωt and cos ωt. 3 is low frequency A
(t) Waveform memory (A) that stores the waveform of sin pt in the form of a digital signal, 4 is also a low frequency A
The waveform memory (B) stores the waveform of (t) cos pt in the form of a digital signal, and the output A(t) sin pt of the waveform memory (A) 3 is stored in the waveform memory (B) in the DA converter 5. )4 output A(t) cos pt is DA converter 6
, each is converted into an analog signal.
Sin ωt of the output of the 90° phase shifter 2 is modulated by A(t) sin pt of the output of the DA converter 5 in the multiplier 7, and similarly, cos ωt of the output of the 90° phase shifter 2 is modulated by A(t) sin pt of the output of the DA converter 5.
A(t) cos pt of the output of the converter 6
is modulated at The outputs of multiplier 7 and multiplier 8 are added by adder 9 to output a lower sideband (LSB) signal as shown in the following equation.

sin ωt・A(t) sin pt+cos ωt・A(t) cos pt=A(t)cos(ω−p)t Since MRI equipment requires high-frequency signals with many different frequencies, the waveform memory, which is RAM, (A)
3 and waveform memory (B) 4, waveforms A(t) sin pt and A(t) cos pt, which are different each time, are downloaded from a higher-level control unit (not shown) each time the MRI apparatus scans.

(Problems to be Solved by the Invention) However, the above-mentioned device is designed to be used only when transmitting an MRI. When transmitting, it is only necessary to transmit pulses of limited length such as 90° pulses or 180° pulses, so the waveform memory (A) 3 and waveform memory (B) 4 have the length that meets the requirements. The waveform is downloaded from the CPU for each scan. Therefore, it cannot be used when receiving signals that require a long time. For this reason, the frequency synthesizer used for signal demodulation during reception requires a separately expensive purchased item to be incorporated into the frequency synthesizer, which is uneconomical.

The present invention has been made in view of the above points, and its purpose is to generate high-frequency signals for demodulation during reception of MRI using signals in the waveform memory without using an independent and expensive frequency synthesizer. The object of this invention is to realize a frequency synthesizer that can be used as a power source.

(Means for Solving the Problems) The present invention, which solves the above problems, provides a frequency synthesizer having means for modulating a high frequency signal with a low frequency signal written in a memory to obtain a high frequency signal with desired sideband waves. , a memory in which a minimum amount of waveform data for each frequency of a low-frequency signal of the required frequency is written in advance, and a waveform data readout address to be generated from the memory by a frequency setting signal given from the outside. a reading means; an address return mark memory in which an address return mark indicating the repetition timing of the read address corresponding to the amount of waveform data of each frequency written in the memory is written in advance; and an address written in the address return mark memory. The present invention is characterized by comprising an address return command generation means for giving an address return command to the waveform data reading means to instruct repeating the read address based on the return mark.

(Operation) A start address corresponding to the frequency of the waveform written in the memory is output in response to the frequency setting signal, and the waveform data in the memory is read out from the position of the start address by the reading means. At the end of the address length of the waveform data determined by the frequency, an address return command is generated by the address return mark written in the address return mark memory, and the reading position of the waveform data in the memory is returned to the start address position to continue reading. , outputs a continuous low frequency waveform,
Modulates a high frequency signal and outputs a sideband signal.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, the same parts as in FIG. 6 are given the same reference numerals. 11 is a register (A) into which the value of the necessary transmission frequency is written by the frequency setting signal;
12 is memory by the frequency setting signal of register (A)
(A) 13 is a μPU (microprocessor unit) that outputs a table reference signal, and memory (A) 13 is a program table in which the start address of each frequency written in the waveform memory (described later) is written in correspondence with the frequency. It is. 14 is a register (B) into which the start address generated in the memory (A) is written, and at the same time generates an interrupt to the address controller 15. The address controller 15 has an 18-bit internal counter and sets the start address. 16 is a memory in which the low frequency sin pt waveform is written from 200Hz to 40KHz every 200Hz
(B), 17 shows the low frequency cos pt waveform from 200Hz to 200Hz.
Memory (C) written every Hz up to 40KHz, 1
8 is an address return mark memory (hereinafter simply referred to as memory (D)) written in memory (B) 16 and memory (C) 17. The output of the memory (D) 18 is selected by the multiplexer 19 to output a return mark, and the return mark is input to the address controller 15. 20 and 21 are data selectors that determine which of the DA converter 5 and DA converter 6 the sin pt output from the memory (B) 16 and the cos pt output from the memory (C) are input to, and 22 is an adder. 9 output
Multiplier 23 is a signal source for amplitude modulating SSB.
Amplitude modulates the SSB signal and sends it to the MRI machine using RF
supply the signal.

Next, the operation of the embodiment configured as described above will be explained. First, the purpose and principle of this circuit will be explained. As an example, it is assumed that the frequency synthesizer according to this embodiment is configured with the following requirements.
That is, the output frequency ω ₀ ±40 kHz (however, ω ₀ is the center high frequency frequency), the frequency interval is 200 Hz, and the read interval of the memory (B) 16 and the memory (C) 17 is 2.5 μs. Since it is also used as a receiving synthesizer, it is necessary to continue outputting it for a relatively long time, and in order to save memory space, the waveform data written for each frequency (200 types up to 40kHz every 200Hz) is This is until one point before the repetition point of the waveform. After that, continuous waves are output by repeating the same waveform.

The configuration of the waveform data written in the memory (B) 16 is as explained below. Low frequency signals of up to 40kHz are recorded in 200Hz steps, and the readout is
This is done every 2.5 μs. It is necessary to prepare the waveform data until the repetition point is reached, and the number of data (address length) for each frequency is as shown in FIG. In the figure, the low frequency signal
At 200Hz, the period is 5ms and the clock is 2.5μs, so the repetition point is the least common multiple of 5ms, and the address length is 5ms/2.5μs = 2000. In this way, the address length is determined. Therefore, as shown in the figure, for example, 200Hz, 400Hz, and 40kHz correspond to one cycle,
Data for 3 cycles at 600Hz and 199 cycles at 39.8kHz are written. The resolution of each data is 8 bits, and the address is 18 bits.

8-bit depth (resolution) data is sin, cos
The function is as shown in Fig. 3. The data written in the memory has the most significant bit as a polarity indicator, with "+" being 1 and "-" being 0. Therefore, the data is represented by 7 bits and is a number quantized from -128 to +127. This data is obtained using the following formula.

sin [(360° x repetition period/signal period) x {(read address - start address)/address length}] In this way, a low frequency signal can be obtained by reading data of a certain length, but this You need to repeat it for the length. For this reason, a return mark is provided one address before the start address of each frequency plus the address length, and after the return mark, the waveform is repeated from the start address and continues. For example, in Figure 3,
In the case of 200Hz, the start address is 0 and the return mark is generated at 1999, and in the case of 400Hz, the start address is 2000 and the return mark is generated at 2999. Since the address return mark can be represented by one bit of data, the following measures are taken to economize on the amount of memory required. Figure 4 A is memory
(D) A diagram showing the position where the address return mark of 18 is written, B is the multiplexer 19
It is a connection diagram. The memory (D) 18 used for the address return mark is the same 8-bit memory as the memory (B) 16 and the memory (C) 17. Since the data depth of the memory is 8 bits, the lower 3 bits of the address are assigned to each of the 8 bits of the data depth as shown in the figure, and together with the remaining 15 bits, the address is set. Update. That is, when it advances from 0 to 7, 15 bits of 1 advance, and the 8 data on the horizontal axis in Figure A are transferred to multiplexer 19 in Figure B.
input to eight data lines _D0 to _D8 . The multiplexer 19 is a switch and has eight input terminals D ₀ to D ₈ and one output terminal, and it sequentially switches according to the input of the lower 3 bits, and when the address return mark is input to the input terminal, it outputs the signal to the output terminal. Output address return command.

Memory configured as above (B) 16, memory
The operation of this embodiment including (C) 17 and memory (D) 18 will be explained. A frequency setting signal is written into the register (A) 11 by input from the outside. At the same time, an interrupt occurs in μPC12. This interrupt also occurs for a setting signal that is the same as a frequency setting signal that has already been written, and initializes the phase of the generated frequency signal. Upon receiving the interrupt, the μPC 12 refers to the program table in the memory (A) 13 for the frequency of the setting signal and writes the start address determined for that frequency into the register (B) 14. At the same time, an interrupt is generated in the address controller 15.

The address controller 15 reads the start address from the register (B) 14, sets it in the internal counter, and stores the start address in the memory (B) 16, memory (C) 17, and
(D) Output to 18 as an address. Memory (B) 16
The sin data shown in Figure 3 is written to the memory (C).
The cos data shown in FIG. 3 is written in 17.
The internal counter of the address controller 15 starts updating at a constant cycle (2.5 μs) and outputs a read clock with a cycle of 2.5 μs. Memory (B) 16 and memory (C)
Reference numeral 17 reads out the stored waveform data from the start address position using the readout clock and outputs it. As mentioned above, the lower 3 bits of the address are sequentially switched by the multiplexer 19 from the address counted on the 8-bit data line of the memory (D) 18, and the upper 15 bits are the address counted on the 8-bit data line of the memory (D) 18.
The return mark is searched for using the address No. 18. The return mark is placed one address before the waveform data starts repeating.
When this is detected, it is sent to the address controller 15 as an address return command signal, and the address controller 15 receives the memory (B) 16, memory (C) 17,
Return all addresses in memory (D) 18 to the start address. By repeating this and reading out the same waveform from the same memory, a continuous frequency waveform is obtained.

Frequency data is written into the memory (B) 16 and memory (C) 17 for the number of cycles determined by the address read cycle. This state is expressed in analog form as shown in FIG. In the figure, addresses 0 to 2000 are 200Hz waveform, addresses 2000 to 3000
is a 400Hz waveform, and 3000 to 5000 is a 600Hz waveform. The waveform synthesized in this way is stored in memory (B) 1.
6 is input as sin pt, and memory (C) 17 is input as cos pt to data selectors 20 and 21. The data selectors 20 and 21 are μPU based on the frequency setting signal.
The output sides of sin pt and cos pt are determined based on the signal from 12, and the outputs are input to DA converters 5 and 6. The operation from the DA converters 5 and 6 to the adder 9 is the same as that in FIG. 6, so a description thereof will be omitted. The SSB signal output from the adder 9 is amplitude modulated by the signal A(t) from the amplitude modulation signal source 22 in the multiplier 23,
A(t)cos(ω ₀ −p)t, or A(t)sin(ω ₀ +
p) Output to the MRI apparatus as t.

As explained above, since the method uses a return mark to repeatedly read out the waveform data written in the memory, it has the following advantages.

(1) It can continuously generate the same frequency for a long period of time, and can be used during reception, which requires about 10 times the time of transmission, and requires only one high-frequency power supply that outputs the center frequency.

(2) Conventionally, amplitude information is also written in the waveform memory, and different information is required for each scan.
It took time to set up before scanning, but
In this embodiment, since the amplitude is modulated by an analog signal, setup as a synthesizer is not necessary.

(3) To achieve the same purpose, the data written to the memory should be limited to one cycle of the low frequency signal,
A method that makes the read cycle variable, or searches the output data by itself without using a return mark,
(For example, detecting a situation where the same data continues)
A method of finding a repetition point and returning an address can be considered, but compared to these methods, this method can be implemented with a relatively small amount of hardware.

Note that the present invention is not limited to the above embodiments. For example, it is sufficient to have only one memory in which waveform data is written. In that case, the data selector, adder, and 90° phase shifter are no longer required, and the DA
One converter and one multiplier are enough, but USB and
A filter is required to select the LSB. Further, each of the memory (B) 16, memory (C) 17, and memory (D) 18 may be a ROM or a RAM.

(Effects of the Invention) As explained in detail above, according to the present invention, a long-time low frequency signal can be obtained even during reception, and one synthesizer (fixed frequency high frequency power supply) is used for both transmission and reception. It is now possible to operate the system economically, which has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.
Figure 2 is a diagram showing the address length of the low frequency signal written in the memory, Figure 3 is a diagram of the data written in the memory (B) 16 and memory (C) 17, and Figure 4 is a diagram showing the address length of the low frequency signal written in the memory.
The figure is an explanatory diagram of the return mark, and A is memory (D) 1.
Figure 8 is a diagram of the return mark written in 8, B is a diagram explaining the operation of the multiplexer, and Figure 5 is the memory (B).
FIG. 6 is an explanatory diagram showing an analog representation of the waveform data of SIN PT written in 16, and FIG. 6 is a diagram of a conventional frequency synthesizer. 1... High frequency power supply, 2... 90° phase shifter, 3... Waveform memory (A), 4... Waveform memory (B), 5, 6... DA converter, 7, 8, 23... Multiplier, 9... Adder , 11...
Register (A), 12...μPU, 13...Memory (A) (program table), 14...Register (B), 15...
Address controller, 16...Memory (B) (waveform data), 17...Memory (C) (waveform data), 18...Memory (D) (address return mark), 19...Multiplexer, 20, 21...Data selector, 22
...amplitude modulated signal source.

Claims (1)

[Claims] 1. In a frequency synthesizer having means for modulating a high frequency signal with a low frequency signal written in a memory to obtain a high frequency signal with a desired sideband, Memory 1 in which a minimum amount of waveform data is written
6, 17, and a waveform data reading means 15 that generates a read address based on a frequency setting signal applied from the outside and reads waveform data from the memories 16, 17.
and an address return mark memory 18 in which an address return mark indicating the repetition timing of the read address is written in advance in accordance with the amount of waveform data of each frequency written in the memories 16 and 17; 2. A frequency synthesizer comprising: address return command generation means 19 for giving an address return command to waveform data reading means 15 to instruct repetition of a read address based on the address return mark.