JPH03282926A - Floating-point numerical arithmetic unit - Google Patents

Abstract

PURPOSE:To obtain a floating-point numerical arithmetic unit capable of executing the operation of a single precision numerical data at twice the speed of a conventional arithmetic unit by adding the comparatively small number of hardware to a computing element capable of directly processing double precision numerical data. CONSTITUTION:In the 1st operation mode for computing double precision numerical data, a floating-point value is computed by the 1st code computing means 59, the 1st exponential part computing means 2 and a mantissa part computing means 1. In the 2nd arithmetic operation mode for computing single precision numerical data, a floating point is computed by either one of the 1st and 2nd code computing means 59, 60 and the means 1. In a 3rd arithmetic operation mode for simultaneously computing two different single precision numerical data, two floating point values are computed by the 1st and 2nd means 59, 60 and the means 1. This constitution makes it possible to execute single precision numerical arithmetic operation at twice the speed of the conventional arithmetic unit only by adding the comparatively small number of hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an addition/subtraction device that processes floating point numerical data, that is, a floating point arithmetic device.

(Prior art) In signed absolute value representation, a floating point value has an exponent part,
It is expressed by the mantissa and the sign of the mantissa. For example I
The double-precision number D (64 bits) and single-precision number S (32 bits) of the EEE754 standard are expressed as follows.

D= (-1)"Xi, fx2°-1023sho
or 1 (lbit)f:ooo...0
0~111...11 (52bit) e-0~2047 (11bit)S-(
-1) Sxi, fx2°-127s: Oor 1
(lbit)f: 000...00~11
1...11 (23bit) e-C1~255 (8bit) Here, S is the sign of the mantissa, and when D (or S) is positive, it is 0.
When 1 is negative, it is 1. f is the decimal part of the mantissa, and is normalized so that the integer part, which is a hidden bit, is 1. e is the exponent and the bias value is a double precision number of 102
3. It is expressed as a single-precision number with an offset of 127 added to the original exponent. The format is shown in FIG. 12 (+1) and (b).

Floating-point numerical operations are much more complex to process than integer numerical operations, and therefore require more time to execute. In hardware implementation, there is a trade-off between execution speed, accuracy, and cost. Increasing the speed and precision of calculations requires a large-scale calculation unit.

In particular, increasing the precision of the mantissa part increases the bit width and complicates the arithmetic processing, so the mantissa arithmetic unit occupies most of the entire arithmetic unit and is relatively expensive. On the other hand, in the exponent part arithmetic unit and the sign part arithmetic unit, the number of bits does not increase much even if the precision is increased. Furthermore, since the calculations are simple, they occupy a small proportion of the entire calculation unit.

FIG. 16 shows an example of a conventional double precision/single precision floating point arithmetic device. In the figure, this arithmetic device includes sign arithmetic means 100. It has an exponent part calculation means 101 and a mantissa part calculation means 102, both of which are implemented with arithmetic units having a bit width sufficient to directly handle double-precision numerical data. Therefore, regardless of double-precision numerical data or single-precision numerical data, one set of data can be input every clock at the highest speed, so one set of data can be input every clock.
It is possible to obtain two calculation results.

In this arithmetic device, the exponent part calculation means 101 is, for example, an exponent part comparator 103. It is composed of an exponent part selector 104, an adder/subtractor 105, and an inflator 106, and calculates the exponent part by inputting a signal E having a bit width e shown in FIGS. 12(a) and 12(b). Mantissa calculation device 10
2 is, for example, the mantissa exchanger 1071, the digit shifter 10
8. Inverting circuit 109. Adder 110. Complementization circuit 111
゜Normalization shifter 112. Priority encoder 1
13. It consists of a rounding circuit 114 and a renormalization circuit 115. A signal F having a bit width f shown in FIGS. 12(a) and 12(b) is input to the mantissa exchanger 107, and the mantissa is calculated.

In this way, in the conventional double precision/single precision floating point number arithmetic device, the exponent part calculation means 101 and the mantissa part calculation means 10
Both circuits are equipped with arithmetic units with a bit width large enough to directly handle double-precision data, so when double-precision data S, E, and F shown in Figure 12(a) are input, each circuit performs a predetermined process. Calculate floating point numbers by performing operations. On the other hand, single precision data S, E.

When F is input, a floating point number operation is performed using a part of the double precision arithmetic unit. Therefore, in the case of this single-precision data calculation, only half the bit width of the relatively expensive mantissa calculator is used, and hardware resources are not used effectively.

Note that the details of each circuit portion of this device are similar to those described later in the detailed description of the present invention, and therefore will not be particularly described here.

(Problem to be solved by the invention) In this way, double precision/
Single-precision floating-point arithmetic units have the problem that only about half the bit width of the mantissa arithmetic unit is used when calculating single-precision numerical data, and hardware resources are not fully utilized. Ta.

The present invention is intended to solve the above-mentioned shortcomings of the prior art, and it is possible to process single-precision numerical data by adding relatively little hardware to an arithmetic unit that can directly process double-precision numerical data. It is an object of the present invention to provide a floating point arithmetic device that can execute operations at twice the speed of conventional ones.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention provides a first operation that has a bit width that can handle double-precision numerical data and that performs an operation on double-precision numerical data. a second operation mode that operates on single-precision numerical data; and a third operation mode that uses divided fields and operates on different single-precision numerical data in each field. An object of the present invention is to provide a floating point arithmetic device characterized by having the following features.

(Operation) In the first calculation mode for calculating double-precision numerical data,
In the second operation mode, in which a floating point number is operated using the first sign operation means, the first exponent operation means, and the mantissa operation means, and single-precision numerical data is operated. Either one of the second sign calculation means and the first one. Floating point calculations are performed using one of the second exponent calculation means and the mantissa calculation means 1. Furthermore, in a third calculation mode in which two different sets of single-precision numerical data are calculated at once, the first... both the second sign calculation means and the first
．． Two sets of floating point number operations are performed by both the second exponent part calculation means and the mantissa part calculation means.

(Embodiment) FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in the figure, this device includes a mantissa calculation means 1,
A first exponent part calculation means 2 for double precision/single precision, and a second exponent part calculation means 31 for single precision numerical data only.
Single-precision first sign part calculation means 59. and a second sign section calculation means 60 dedicated to single-precision numerical data.

The mantissa calculation means 1 includes a mantissa comparator (a magnitude comparator) 4.
Mantissa exchanger 51 digit matching circuit (Nokrel shifter) 6.
Bit inverter7. Adder 8. Priority encoder9. and a normalization circuit 10. Each of these circuits is divided into a first field and a second field, but can also operate in a mode in which the first and second fields are connected. Note that the first part of each circuit. The division into the second field can be easily done with a small amount of 7X-ware.

The first exponent part calculation means 2 includes a first exponent part comparator 11, a first exponent part calculation unit 12 . First exponent selector (selector) 1
3, all of which implement the number of bits that can handle double-precision numerical data.

The second exponent part calculation means 3 includes a second exponent part comparator 14, a second exponent part calculation unit 15. It consists of a second exponent part selector 16, which is equipped with at least the number of bits that can handle single-precision numerical data.

The first sign section calculation means 59 includes a first sign section calculation unit 62 which is equipped with a number of bits that can handle double-precision numerical data, and the second sign section calculation means 60 includes a bit number that can handle at least single-precision numerical data. Second exponent part calculator 6 that implements the number
Consists of 3.

Next, the operation of the above device will be explained.

First, a first calculation mode for calculating double-precision numerical data will be described. The apparatus shown in FIG.
The double-precision numerical data shown in a) is input. The mantissa is input to the mantissa calculation means 1, which connects the first field and the second field, and is calculated. The exponent part is
The first exponent calculation means 2 is used for both double precision and single precision.

Further, the code part is calculated by a first code part calculation means 59 which can be used for double precision/single precision.

Next, a second calculation mode for calculating single-precision numerical data will be explained. Single-precision numerical data shown in FIG. 12(b) is input to the arithmetic unit shown in FIG. The mantissa part is input to the mantissa calculation means 1 which is divided into a first field and a second field. Calculated in any second field. The exponent part is double precision/
Single-precision first exponent calculation means 2. Alternatively, it is calculated by either the second exponent calculation means 3 dedicated to single precision.

Further, the code part is formed by a double-precision/single-precision first code part calculation means 59. Alternatively, it is calculated by either the second code part calculation means 60 dedicated to single precision.

Finally, the third step is to perform calculations on two different sets of single-precision numerical data.
The case of calculation mode will be explained.

The arithmetic device shown in FIG. 1 includes a first . Two second different sets of single-precision numerical data are input. The mantissa is input to the mantissa calculation means 1 which is divided into a first field and a second field, each independently calculates the first set of single-precision numerical data in the first field, and calculates the first set of single-precision numerical data in the first field. In this step, the second set of single-precision numerical data is operated. The exponent part is calculated by a double precision/single precision first exponent part calculating means 2. and a second exponent calculation means 3 dedicated to single precision. The code section includes a double-precision/single-precision first code calculation means 59. and the second sign section calculation means 60 dedicated to single precision.

In this way, in the third calculation mode, two different sets of single-precision numerical data can be calculated in parallel, so the calculation speed for single-precision numerical data is substantially doubled compared to conventional devices. Note that the addition of hardware for this purpose includes a second sign part calculation means 60° for single-precision numerical data with a small number of implemented bits, a second exponent part calculation means 3, and a mantissa part calculation means 1 to the first. Only a small amount of hardware is required to split into the second field.

The mantissa calculation means 1 generally performs 1) digit alignment processing of the mantissa, 2) true addition/subtraction processing of the mantissa, 3) rounding, 4) normalization processing, etc. Depending on the configuration and processing order of the processing means, various configurations of the mantissa calculation means can be considered.

Next, an apparatus according to an embodiment of the present invention will be described in more detail with reference to FIG. 2 and subsequent drawings showing the configuration of each part in FIG. 1 in detail.

In the apparatus shown in FIG. 2, in floating-point number operations, the exponent part, the mantissa part, and the sign of the mantissa part can be calculated by different circuits. Figure 2 shows the mantissa calculation means 1
．． Exponent part calculation means 2, 3, and sign part calculation means 59.
60. This example uses IEEE75
Complies with 4 standards.

The mantissa calculation means 1 of this embodiment is configured to determine the presence or absence of increment due to rounding before performing true addition/subtraction processing, and to simultaneously perform rounding processing and true addition/subtraction processing.

The device has a first operand (mantissa part Fl, exponent part El, sign S1 of the mantissa part) and a second operand (mantissa part F2. exponent part E2. sign S2 of the mantissa part) expressed in signed absolute value representation. ), an addition/subtraction control signal 68 .indicating whether true addition/subtraction is to be performed. Rounding mode signal 69 indicating rounding mode. A signal 61 indicating the calculation mode is input.

The format of the mantissa part is shown in FIG. The mantissa part has an overflow bit v, and the hidden bit N of the integer part.

Guard pit representing the value one bit below the least significant digit)G,
A rounding bit R representing a value one bit below G, and a sticky bit St, which is the logical sum of all bits below R, are expanded.

The addition/subtraction control signal 68 is a signal indicating whether true addition or true subtraction is to be performed, and the sign (+:
0. -:1) and the operation mode (addition: 0, subtraction: 1). The rounding mode signal 69 is a signal indicating the type of rounding process. Note that FIG. 14 shows an example of the rounding mode.

Further, the calculation mode signal 61 is a signal representing each mode of double-precision calculation, single-precision calculation, and single-precision double-speed calculation (for single-precision, single-precision double-speed calculation: 11 for double-precision calculation).

First, each block of the apparatus will be explained using FIG. The exponent part comparison circuit 11.14 compares the exponent part E of the first operand.
Exponent part EH2, EL of the second operand from HI, ELI
2 is subtracted to obtain the exponent part magnitude comparison signal 33.35 and the exponent part difference signal 32.34. The exponent part comparison circuit 11 is used for single precision/double precision, and in the case of double precision number arithmetic, the exponent parts are compared in the exponent part comparison circuit 11. The exponent comparison circuit 14 is a single-precision comparator, and when performing single-precision double-speed arithmetic, the comparators 11 and 14 perform processing independently. Further, in the exponent part selector 13, the larger exponent part 27 is selected based on the exponent part size comparison signal 33.

The exponent selector 16 selects the larger exponent part 31 based on the exponent part size comparison signal 35.

The mantissa comparison circuit 4 compares the mantissa part F1 of the first operand and the mantissa part F2 of the second operand, and generates the mantissa part magnitude comparison signals 36, 36 . Find 37.

FIG. 5(a) is a detailed diagram of the mantissa comparator 4, and FIG. 5(b) is a detailed diagram of the mantissa comparator 4.
) is the data input format.

This circuit has a two-stage tree structure. The first stage is
Six 8-bit comparators 7o and one 5-bit comparator 7o
It is composed of a comparator 71.

Each comparator compares the magnitude of each field in 8-bit or 5-bit units (for example, input A).

A 2-bit signal indicating A>B, BAA) is output. The second stage consists of two 3-bit comparators 72.
and one 7-bit comparator 73.

The 7-bit comparator 73 receives all outputs from the first stage, compares the mantissa parts of the double-precision numerical values, and outputs a comparison signal 36'. The two 3-bit comparators calculate the mantissa parts FHI and FH2, and FLI and FL2 of the single-precision numbers input in the first and second fields, respectively.
A comparison signal 36.37 is output.

The mantissa exchanging circuit 5 receives an exponent magnitude comparison signal 33.35 and a mantissa magnitude comparison signal 36-. 36.37, the first and second operands are compared in size, and the mantissa part of the operand with the larger absolute value is used as the mantissa part 19H, 19L.
, the smaller one is output as the mantissa parts 20H and 2OL. The logic of the size comparison is as follows.

(1) If the sizes of the exponent parts are different, the operand with the larger exponent part is set to Holland 19H, 19L. (2) If the sizes of the exponent parts are the same, the operand with the larger mantissa part is used as the operand. 6 is a detailed diagram of the mantissa exchanging circuit 5. In FIG.

The mantissa exchanging circuit 5 includes a selector 74 and a selector υ control circuit 75. selector [yo, 1st field, 2nd field
It is divided into fields, and the first fields or the second fields are exchanged.

The control circuit 75 receives the operation mode signal 61. An exchange control signal 55.56 is output using the exponent part magnitude comparison signals 33, 35 and the mantissa part comparison signals 36, 36, 37. In the case of double-precision arithmetic, the first field and the second field are exchanged together, and in the case of single-precision or (A single-precision double-speed arithmetic), they are exchanged independently.

The digit alignment circuit 6 shifts the mantissa parts 20H and 2OL to the right by the number of the difference signal 32 or signal 34 of the exponent part, and shifts the mantissa part 1
The digits are aligned to 9H and 19L, and the mantissa parts are 21H and 21L. Also, it generates a steady bit in parallel. FIG. 7 is a detailed diagram of the digit alignment circuit 6. Digit alignment circuit No. 6 is composed of a right-angle shifter 76 that can be divided into a first field and a second field, and two stick-by-soto generators 77. When performing double-precision arithmetic, the first field and the second field are concatenated, and the bit string shifted out from the first field is shifted into the MSB of the second field. MSB of 1st field
0 is shifted in.

The sticky bit is obtained as the logical sum of the bit strings reshifted out from the shifter of the second field. When performing single-precision or single-precision double-speed operations.

The shifter is used by dividing it into a first field and a second field according to an operation mode signal 61. 1st field, 2nd field
0 is shifted into the MSB of both fields. Further, the sticky bit is obtained as the logical sum of the bit strings shifted out from each of the first field and the second field.

The inversion circuit 7 inputs the mantissa parts 21H and 2 when performing true subtraction.
This is a circuit that performs bit inversion of 1L. 1st field,
In order to independently control the inversion of the second field, it is configured as an exclusive OR array divided into two.

The rounding look-ahead circuit 40 receives a specific portion of the mantissa and the addition/subtraction control signal 68 . Rounding mode signal 69. Depending on the sign of the first operand and the value of the exchange control signal 55.56, the first rounding judgment and normalization are necessary, which indicates whether or not incrementing by rounding is necessary, assuming that normalization is not required after the operation. If it is assumed that there is, perform a second rounding judgment indicating whether increment by rounding is necessary (1 if necessary)
.

Whether or not to increment by rounding can be determined using three bits: the least significant digit of the normalized mantissa, the bit immediately below it, and the logical sum of all bits below it. 15th
The figure shows the increment decision logic for each rounding mode. Also, although the position at which rounding is to be performed cannot be determined until after the calculation, the position is determined for both true addition and subtraction in Figure 8 (c
) There are only two options. Therefore, it is sufficient to assume both cases, find a solution for each case, and select it later.

The rounding look-ahead circuit 40 has the first rounding look-ahead circuit 40 shown in FIG. 8(a).
and a circuit that performs a second rounding determination.

During double-precision arithmetic, the first . Perform a second rounding determination. In the case of single-precision arithmetic or single-precision double-speed arithmetic, the first . A second rounding judgment is performed, and the first . Perform a second rounding determination.

The main adder 41 receives the mantissa part Fl of the first operand, the mantissa part F2 of the second operand, and so on. Addition/subtraction is performed on the first rounding determination value, and solutions 46H and 46L are obtained assuming that no normalization occurs after rounding.

The main adder 42 receives the mantissa part F1 of the first operand, the mantissa part F2 of the second operand, and so on. Addition/subtraction is performed on the second rounding determination value, and solutions 47H and 47L are obtained assuming that normalization is necessary after rounding.

FIG. 9 is a detailed diagram of the main adder 41. The main adder 42 and the main adder 41 have the same configuration except that the addition position of the rounding determination signal is different.

The main adders 41 and 42 are three-man power adders, and the first stage full/half adder array 78 performs C3A (carry 5
aved adder) to add three input values. The second stage 79 is a CLA every 4 bits.
(carrylookahead adder), and C5A (carrylookahead adder) every 12° or 16 bits.
lect adder) to perform the final addition at high speed. The main adders 41 and 42 can be divided into a first field and a second field according to the calculation mode signal 61. During double precision arithmetic, both fields are concatenated and used. Also, single precision.

When performing single-precision double-speed calculations, it is divided and used.

The solution selection circuit 43 is a selector that selects the correct solution among the two solutions obtained by the two main adders. The selection circuit can control the first field and the second field independently. In the case of double precision arithmetic, the first field, the second
Select fields together. The logic of selection is as follows.

(1) When addition is performed, if the overflow bit V of the solution of the first adder is 1, the solution of the second adder is selected, and if it is 0, the solution of the first adder is selected.

(2) If subtraction is performed, the hidden value of the first adder's solution) If N is 1, the first adder's solution is selected; if N is 0, the second adder's solution is selected.

The priority encoder 9 outputs the number of steps to be shifted in the normalization process, 38.39. Figure 10 (
a) is a detailed diagram of the priority encoder 9; The priority encoder has a two-stage tree structure. The first stage 80 consists of eight 8-bit priority encoders 81 and outputs 3 bits of encoded results for every 8 bits. The second stage 82 consists of two 4-bit priority encoders 83 and outputs 2 bits of the encoded result every 4 bits.

The priority encoder 9 receives the calculation mode signal 61
It can be divided by In the case of double speed calculation, as shown in FIG. 10(b), the mantissa part 23 (V.

55 bits (excluding the St bit) are input, and a 6-bit encoded result 38 is output. Single precision.

In the case of single-precision double-speed arithmetic, it is divided and used, as shown in Figure 10 (b).
), the mantissa parts 23H and 23L of two single-precision numbers
(V, 26 bits excluding the S t bit) are input. Here, 23L is shifted by 3 bits and input into the second field as shown in FIG. 10(a), and a 5-bit encoded result of 38°39 is output.

The normalization circuit 10 is a circuit for normalizing the calculation results 23H and 23L so that the hidden bit N becomes 1. FIG. 11 is a detailed diagram of the normalization circuit 10. The normalization circuit 10 includes a 1-bit right shifter 84 and a left barrel shifter 85.
It consists of The normalization circuit 10 receives the calculation mode signal 6
It is divisible by 1. In the case of double precision arithmetic, they are used in conjunction; when the V bit is 1, they are shifted to the right by 1 bit, and when the V bit is 0, they are shifted to the left by the value of the shift signal 38. In the case of single-precision or single-precision double-speed arithmetic, the field is divided into a first field and a second field, and depending on the value of V in each field, a 1-bit right shift or a shift signal 38. and shifted to the left by a value of 39. In either case, 0 is L
Shifted into SB.

The exponent calculators 12 and 15 are circuits that adjust the exponent by the amount shifted by normalization. The exponent part calculator 12 is dual-purpose for single precision/double precision, and in the case of double precision arithmetic, the exponent part calculator 12 calculates an exponent 57. In other words, if it is shifted to the right by 1 bit due to normalization, it is incremented,
When shifted to the left by n bits, n is subtracted from the exponent 27. In the case of single-precision and single-precision double-speed arithmetic units, exponent operator 1
2.15, the exponents 57.58 for the first field and the second field are calculated in the same way.

The sign part calculators 62 and 63 calculate the sign part S of the first operand.
This is a circuit that calculates the sign 64.65 of the solution from 1. The solution code 64.65 is obtained using the following logic.

(1) When true addition is performed: The sign of the solution is equal to Sl. (2) When true subtraction is performed: When the solution is not 0 and no exchange of mantissas occurs: It is equal to 81.

If the solution is not 0 and the mantissa exchange occurs: If the inverted solution of 81 is 0 and the rounding mode is negative rounding: If the negative answer is 0 and the rounding mode is other than negative rounding: Positive Next, the operation of the embodiment shown in FIG. 2 will be explained. First, a first calculation mode for calculating double-precision numerical data will be described.

In calculating double-precision numerical data, the mantissa calculation means 1 operate in conjunction. The exponent part is processed by the exponent part calculation means 2. Further, the code part is processed by the code part calculation means 59. The arithmetic device shown in FIG.
The double-precision numerical data shown in a) is input. The mantissa parts Fl and F2 are input in the format shown in FIG. 13(a). First, the exponent parts EHI and EH2 are compared by the exponent part comparator 11, and an exponent difference signal 32 is obtained.

Further, the larger exponent part 27 is selected according to the comparison result. The mantissa parts Fl and F2 are compared in a mantissa comparator 4. Based on the results of each comparison, the mantissa part of the operand with the larger absolute value is outputted from the mantissa exchanger 5 as the mantissa part 19. In the digit alignment circuit 6, the mantissa part 20 of the smaller operand is shifted to the right according to the value of the exponent difference signal 32. At this time, sticky bits are generated in parallel. When performing true subtraction, the mantissa inverter 7 inverts the mantissa 20. The lower 5 bits of the mantissa are input to the rounding look-ahead circuit 40, and the sum is used to calculate the first . Perform a second rounding determination.

The mantissa part 19.22 and the rounding judgment value 45 are input to the main adder 41.42, and normalization is necessary with the first operation result 46 assuming that normalization is unnecessary. A second calculation result 47 is calculated assuming that. The solution selection circuit 20 selects the correct solution 23 based on the values of the V and N bits of the first calculation result 46. The selected solution 23 is input to the priority encoder 9, and the number of shifts 38 required for normalization is determined. The selected solution is shifted by the number of shifts 38 in the normalization circuit 10 and normalized. Further, the shift number 38 is input to the exponent part calculator 12, and the exponent 57 of the solution is calculated. The sign part is obtained from the sign part S1 of the first operand in the sign part arithmetic unit 62.

Next, the case of the third calculation mode, which is single-precision double-speed calculation, will be explained.

In addition, in the case of the second calculation mode that performs single-precision calculation,
Since this is essentially the same as in the case of single-precision double-speed calculation, the only difference being the number of data to be processed simultaneously, the explanation will be omitted.

In the case of single-precision double-speed arithmetic or single-precision arithmetic, the mantissa calculation means 1 is divided and used.

The exponent part is calculated by exponent part calculation means 2. Each is processed by the exponent calculation means 3. Further, the code part is a code part calculation means 59
．． Each is processed by the sign part calculation means 60.

Single-precision numerical data shown in FIG. 12(c) is input to the arithmetic unit shown in FIG. 2. As for the mantissa part, the first set and the second set of data are input into the first field and the second field of the mantissa calculation means, respectively, in the format shown in FIG. 13(C). First, the exponent part E of the first set
HI and EH2 are compared by an exponent part comparator 11, and an exponent difference signal 32 is obtained. Furthermore, the larger exponent part 27 is selected based on the comparison result. The mantissa parts FHI and FH2 are compared in the mantissa comparator 4. Exponent part size comparison signal 3
3. In response to the mantissa comparison signal 36, the mantissa of the operand having the larger absolute value is outputted from the mantissa exchanger 5 as the mantissa 19H. Similarly, the second set of exponent parts ELI, EL2
are compared by the exponent part comparator 14, and an exponent difference signal 34 is obtained.

Furthermore, the larger exponent part 31 is selected based on the comparison result. The mantissa parts FLI and FL2 are compared in the mantissa part comparator 4. Exponent part magnitude comparison signal 35° Mantissa part comparison signal 37
Accordingly, the mantissa part of the operand having the larger absolute value is outputted from the mantissa exchanger 5 as the mantissa part 19L. In the digit alignment circuit 6, the mantissa parts 20H and 2OL are the exponent difference signals 32.
．． It is shifted to the right according to the value of 34. At this time, stick bits for each field are generated in parallel. When performing true subtraction, the mantissa parts 21H and 21L are inverted. The mantissa part is input to the rounding look-ahead circuit 40, and the mantissa part 1
A first to second rounding determination signal 44 for the first set of operands is determined by the sum of the lower five bits of 9H and 22H. Similarly, the first . A second rounding determination signal 45 is obtained. These mantissa parts 19H, 22
The values of H, 19L, 22L and the rounding judgment value 44°45 are input to the main adder 41.42, and the first field,
First calculation results 46H, 46L assuming that normalization is unnecessary for the second field, and second calculation results 47H, 47L assuming normalization is necessary for the second field.
is calculated.

The solution selection circuit 43 selects the correct solution of the first field based on the values of the V and N bits of the calculation result 46H. Similarly, the correct solution for the second field is selected based on the values of the V and N bits of the calculation result 46L.

The selected solutions 23H and 23L are input to the priority encoder 9 and the number of shifts required for normalization is 39.38.
is required. The selected solution 23H123L is shifted and normalized by the number of shifts 39°38 in the normalization circuit 10. Further, the shift number 39.38 is input to an exponent part calculator 12.15, and the exponent of the solution is calculated. The sign part is obtained from the sign parts SHI and SH2 of the first operand in sign part operations 662 and 63, respectively.

In this way, the mantissa calculation means 1 is set to the first . By dividing it into a second field and operating it independently, two different sets of single-precision numerical data can be processed simultaneously.

FIG. 3 is a block diagram showing another embodiment of the invention. The structure of the mantissa calculation means 1' is different from that of the above embodiment,
The present invention is characterized in that the rounding process and the complementing process do not occur at the same time, so that the rounding process and the complementing process after the calculation are performed in the same circuit. In this embodiment, floating point operations are performed as follows.

First, based on the comparison result of the exponent parts El and E2, the mantissa part Fl,
Replace F2. The mantissa part 2o is digit-aligned by a digit-alignment circuit. Further, when performing true subtraction, the mantissa part 21 is inverted.

The mantissa parts 19.22 are added by the main adder 48. 49 is an inverter, and 50 is an incrementer, which performs complement processing when the result of subtraction is a negative number. Further, if the result of the calculation requires incrementing by rounding, the increment is performed by the incrementer 50.

This calculation result 23 is normalized by the normalization circuit 10.

FIG. 4 is a block diagram showing still another embodiment of the invention. The mantissa calculation means 1' has a classical configuration, which is different from the embodiment described above. In this embodiment, floating point operations are performed as follows.

First, based on the comparison result of the exponent parts El and E2, the mantissa part Fl,
Replace F2. The mantissa part 20 is subjected to digit alignment by a digit alignment circuit 6. Further, when performing true subtraction, the mantissa part 21 is inverted.

The mantissa parts 19.22 are added by the main adder 48. 51 is a complement circuit, which is composed of an inversion circuit and an incrementer. The complement circuit 51 performs complement ratio processing when the result of true subtraction is a negative number. This result 23 is normalized in a normalization circuit 10 and incremented in a rounding circuit 50 if necessary. Reference numeral 52 denotes a renormalization circuit, which shifts one bit to the right and performs normalization again when a carry occurs due to rounding.

Even if the mantissa calculation means 1 has a configuration as shown in FIGS. 3 and 4, each component of the mantissa calculation means 1 is This field can be divided into a second field and a second field, each of which can be operated independently, and two different sets of single-precision numerical data can be processed simultaneously.

As mentioned above, by adding a small amount of circuitry to enable the mantissa calculation means to be divided into the first and second fields, it is possible to double the calculation execution speed for single-precision numerical data. I can do it. Various configurations of the exponent calculation means may be considered in addition to the configuration mentioned in this embodiment. However, since the exponent calculation means occupies a small proportion of hardware in the entire calculation device, the object of the present invention can be achieved regardless of the configuration.

[Effects of the Invention] As described above, according to the present invention, by adding a small amount of hardware, relatively expensive mantissa calculation means can be fully utilized, and single-precision calculations can be performed at twice the speed of conventional methods. It is possible to obtain a high-speed floating point arithmetic unit capable of executing.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing a floating point arithmetic device according to the present invention, FIGS. 2 to 4 are block diagrams showing each embodiment of the device of the present invention, and FIGS. 12 is a diagram showing the format of double-precision floating-point numbers and single-precision floating-point numbers based on the IEEE754 standard. FIG. 13 is a diagram showing the mantissa part. A diagram showing the format of No. 14. FIG. 15 is a diagram for explaining the embodiment device shown in FIG. 2, and FIG. 16 is a block diagram showing the configuration of a conventional floating point arithmetic device. 1... Mantissa part calculation means 2... First exponent part calculation means 3... Second exponent part calculation means 59... First sign part calculation means 60... Second sign part calculation means

Claims (1)

[Claims] (1) Has a bit width that can handle double-precision numerical data, and divides the field into a first calculation mode that operates on double-precision numerical data and a second calculation mode that operates on single-precision numerical data. 1. A floating-point number arithmetic device, characterized in that it has a mantissa arithmetic means that operates in a third arithmetic mode in which different single-precision numerical data are arithmetic in each field.