JPH03282953A - Semiconductor device having device selecting circuit - Google Patents

Abstract

PURPOSE:To easily select a relevant semiconductor device from a microprocessor and to make it unnecessary to use an additional hardware for selection by setting up a reference address in a selecting circuit. CONSTITUTION:When the inverse of RESET signal 107 is turned to low, an MPU 100 and a memory 101 are initialized, an AR control circuit 101-7 outputs the address of a device selecting information storing area and device selecting information is outputted to an MD bus 101-8 synchronously with the output of the address. When address information latched in an AL 101-3 coincides with device selecting information stored in an AR 101-2, a coincidence circuit 101-5 activates a SEL signal 101-6 and a bus control part 101-9 outputs the data of the address stored in the PROM 101-1 to an AD bus 106. The MPU 100 fetches data from a bus 106 at a prescribed timing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer system, and particularly to a device selection method.

[Conventional technology]

In recent years, the performance of microprocessors has improved significantly with improvements in process technology, etc., and large-scale microcomputer systems are being built around these microprocessors, including memories, peripheral input/output devices, and the like. Typically, in such a system, a device select circuit is installed between the microprocessor and the memory and peripheral input/output devices, and this device select circuit logically selects the required memory and peripheral input/output devices.

FIG. 12 is a block diagram showing a conventional example of this type of device selection method, and FIGS. 13 and 14 are timing charts showing the operation of the conventional example of FIG. 12.

The microprocessor 700 (hereinafter referred to as MPU 700) receives a row active read signal 700-2 (hereinafter referred to as RD70) that specifies data read timing.
0-2 signal), a row active write signal 700-3 (hereinafter referred to as W
R700-3) and performs data input/output processing, arithmetic processing, and control of the entire microcomputer system. Memories 701 and 702.

703 and 704 store data and programs processed by the MPU2O5. The latch circuit 705 is MP
Latch address information from U700. The device select circuit 706 is a fixed circuit consisting of a combination of logic gates, and a chip select signal (hereinafter referred to as C
8 signals 706-1 to 706-4) 706-1 to 7
Activate 06-4. address data bus 70
7 (hereinafter referred to as AD bus 07) includes an MPU 700, a latch circuit 705, and memories 701 and 702.

703 and 704, and an address bus 708 (hereinafter referred to as A bus 708) connects a latch circuit 705, a device select circuit 706, and memories 701, 702, and 70.
3.

704 is connected.

Next, regarding the operation of the conventional example shown in Fig. 12, Fig. 13 and 1
This will be explained with reference to FIG.

(1) MPU 700 has memories 701 and 702
, 703, 704 (first
Figure 3).

The MPU 700 raises the ALE signal 700-1 at the leading edge of timing T1 in the read process.

Next, the MPU 700 outputs address information to the AD bus 707 at the latter half of timing T1. Thereafter, the ALE signal 700-1 falls at the trailing edge of timing T1. Device select circuit 706 activates a predetermined C8 signal based on address information on A bus 708. The RD signal 700-2 output during the period of timing T3 is C
The S value numbers 706-1 to 706-4 are valid only for the active memory, and this memory outputs data at the address indicated by the address information on the bus 708 to the AD bus 707. The Mp tJ 700 takes in data from the AD bus 707 at a predetermined timing during a period of timing T3 when the data output to the AD bus 707 becomes valid.

(2) MPU 700 has memories 701 and 702
, 703, 704 (14th
figure).

The MPU 700 raises the ALE signal 70G-1 at the leading edge of timing T1 in the write process. Next, address information is output to the AD bus 707 at the latter half of timing T1. After that, at the trailing edge of timing T1, the ALE signal 70
The MPU 700 lowers the 0-1 signal and outputs data to the AD bus 707 in the second half of the -[2 timing. The select circuit 706 activates a predetermined O8 signal based on the address information on the A bus 108. timing T3
The WR signal 700-3 output during the period is the C8 signal 706.
-1 to 706-4 are valid only for active memories. The MPU 700 writes AD bus 0 to the address pointed to by the address information of the A bus 708 for this memory.
7 data is written in synchronization with the rising edge of the WR signal 700-3.

[Problem to be solved by the invention]

The conventional device selection method described above is based on the MPU700
This is done by a device select circuit 706 provided between the memory and peripheral input/output devices, and as the number of memories and peripheral input/output devices used increases, the number of decoders, latches, drivers, etc. that make up the device select circuit 706 increases. Requires a lot of additional hardware
There is a drawback that it impairs the economic efficiency of the system and causes a decrease in reliability due to an increase in the number of parts.Since the select circuit 706 is a circuit fixed on the board, it is necessary to change or add a part of the circuit. For example, when adding a latch or decoder to expand memory, or changing a decoder to move an address to another address for device allocation, there is also the disadvantage that additional changes to the circuit cannot be easily made. be.

[Means to solve the problem]

A semiconductor device with a device select circuit according to the present invention is a semiconductor device having a memory section including at least a rewritable non-volatile memory, and includes a reference address register for holding device select information, and a device select circuit set in advance at the time of initialization. An address register control circuit that causes information to be held in a reference address register, an address holding circuit that holds address information from a microprocessor for selecting the semiconductor device, and data held by the reference address register and the address holding circuit are compared. When a match occurs, a comparison circuit outputs a match signal, and when the comparison circuit outputs a match signal, an address holding circuit allows the microprocessor to access the address in the memory section corresponding to the address information held. and a bus control unit that allows the bus to operate.

[Effect]

Since the semiconductor device has a built-in select circuit, by setting a reference address in the select circuit, the corresponding semiconductor device can be easily selected from the microprocessor, and latches, decoders, drivers, etc. No additional hardware is required, the microprocessor and memory are directly connected, and an extremely compact system configuration is possible.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows memories 101 and 102 which are a first embodiment of a semiconductor device with a device select circuit according to the present invention.

103 and 104 are used, FIG. 2 is a block diagram showing details of the memory 101 in FIG. 1, and FIG. 3 is a block diagram showing the PROM in FIG. 2.
An explanatory diagram showing the functions of 101-1, Figures 4 and 5 are
3 is a timing chart showing the operation of the memory 101 shown in the figure.

Microprocessor 100 (hereinafter referred to as M P LJ 100)
) is initialized by the RESET signal 107, and the address latch enable signal 100-1 (
(hereinafter referred to as ALE signal 100-1), read signal 100
-2 (hereinafter referred to as RD double signal 00-2), write signal 100-3 (hereinafter referred to as WR signal 100-3), address data bus 106 (hereinafter referred to as AD bus 0
6) and outputs the address to the memories 101 and 10.
2, 103, 104, AD Babasu 06
Data is exchanged with the memories 101, 102, 103, and 104 via the memory 101, 102, 103, and 104.

In this embodiment, memories 101, 102, 103
.

Since the memory 104 has a similar configuration, the memory 101 will be explained with reference to FIGS. 2 and 3.

The rewritable read-only memory 101-1 (hereinafter referred to as PROM 101-1) is MPU1.
It has a program storage area that stores programs executed by 0G, and a device selection information storage area that stores device selection information (FIG. 3(a)).
The register 101-2 (hereinafter referred to as AR101-2) holds device selection information during operation of the microcomputer system. The AR control circuit 101-7 is F
The device select information held in the ROM 101-1 is transferred to the AR 101-2. The address latch 101-3 (hereinafter referred to as A 1101-3) latches address information of the AD bus 06. −
The number circuit 101-1 compares the content held by the AR 101-2 with the address information latched in the ALlol-3, and only when a match is detected, outputs the select signal 101.
-6 (hereinafter referred to as SEL signal 101-6) is activated. It has a bus 111110 section 101-9 that controls the exchange of data between an internal data bus 101-8 (hereinafter referred to as MD bus 01-8) and AD bus 06 when the SEL signal 101-6 is active. The microcomputer can access F ROM 101-
1 (FIG. 3(b)).

Next, the operation of the memory 101 of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 4, 5, and 6.

(1) Transfer of device selection information held by PROM 101-1 to AR 101-2 (FIG. 4).

The RESET signal 107, which is active
When it becomes low during the period T from t1 to time t1, MPU
100 and memories 101, 102, 103, 10
4 is initialized. In period ■, A Rl
l1ll il1 circuit 101-7 is MA bus 01-4
p ROM 1 that holds device selection information in
Outputs the address of the device select information storage area in 01-1. In synchronization with this, device selection information is output to the MD bus 01-8. A R101-2 captures the rising timing when the RESET signal 107 becomes inactive at time t1, and activates the MD bus 01.
-8 device selection information is imported.

(2) After the device selection information is stored in AR101-2, that is, after the reset is released, MPLJ100
(FIG. 5).

M p u ioo is timing T in read processing
ALE signal 10G-1 rises at the leading edge of 1. next,
In the latter half of timing T1, the address information is AD Babasu 06.
ALF signal 100- is output at the trailing edge of timing T1.
Lower 1. A L 101-3 is timing T
The address information of the AD bus 06 is latched by capturing the fall timing of the ALE signal 100-1 at the end of the ALE signal 100-1. - The number circuit 101-5 compares the address information latched in ALlol-3 and the device select information held in ARlol-2, and if they match, activates the SF[- signal 101-6. Make it. The bus control unit 101-9 has an R signal that becomes active for a period of timing T3 only when the SEL signal 101-6 is active.
FROM 101-1 instructs address information held by AL 101-3 in synchronization with D signal 100-2.
The data at the address of A
Output to D bus 06.

The MPU 100 takes in the data of the AD bus 06 at a predetermined timing within the T3 timing when the data output to the AD bus 06 becomes valid.

FIG. 6 is a block diagram showing a computer system in which a second embodiment of the memory of the present invention is used, FIG. 7 is a block diagram showing details of the memory 401 in FIG. 6, and FIG. An explanatory diagram showing the functions of PROM 401-1 of
FIGS. 9, 10, and 11 are timing charts showing the operation of the memory 401 in FIG. 6.

In this embodiment, the memory section 401-1 is F ROM 401
-11 and data memory 40 that can be written and read at any time
1-12, including AR401-2 and ARIIJ
1M] circuit 401-7 sends two select signals to the matching circuit 401-5, and the two select signals 401-6 and 401-10 held by the minus number circuit 401-5 (hereinafter referred to as S E I-L signal 401-6, 8 ELM signal 4
01-10), and the bus control unit 401-9 controls the PROM 401-1 based on the SELL signal 401-6 and the SELM signal 401-10. This is different from the example.

(1) Transfer of device selection information held by the memory unit 401-11 to the AR 401-2.

The transfer method is the same as in the first embodiment, but the memory section 4
From 01-11, PROM select information and data memory select information are sequentially read out and stored in AR401-2.

(2) After the PROM selection information and data memory selection information are stored in the AR401-2, that is, after the reset is released, the operation for reading the MPU 10G (
Figure 10).

M P Ll 100 is AL at the leading edge of timing T1.
The E signal 100-1 is raised, address information is output to the AD bus 06 at the latter half of timing T1, and then the ALE signal 100-1 is lowered at the trailing edge of timing T1. The address latch 401-4 latches the address information of the AD bus 06 in response to the fall of the timing T1. Latched address information and A R40
1-3, and if they match the PROM selection information, the 5ELL signal 401-6 is activated. Furthermore, if the address information matches the data memory select information, the SELM signal 401-10
Activate.

5ELL signal 401-6 or SELM signal 401-1
If 0 is active, MPU 100 in period T3
The RD signal 100-2 output from 5E becomes valid and
When the LL signal 401-6 is active, A L 40
F ROM 401- pointed to by the address held by 1-3
11 data is on MD bus 01-8, S F L
When Y signal 401-10 is active, A L 40
Data memory 401- pointed to by the address held by 1-3
12 data are output to the MD buses 01-8, respectively, and the AD buses 06 are output under the control of the bus control unit 401-9.
is output to.

The MPU 100 takes in data from the AD bus 06 at a predetermined timing within timing T3 when the data output to the AD bus 06 becomes valid.

(3) When writing data to the data memory 401-12, Mpu ioo raises the ALF signal 100-1 at the leading edge of timing T1, and outputs address information to the AD bus 06 at the latter half of timing T1. . Thereafter, the AIE signal @100-1 falls at the trailing edge of timing T1. Capturing the falling edge of timing T1, AL 401-3 latches the address information of AD bus 06. Latched address information and A R4
When the address information matches the data memory select information, the SELM signal 401-10 is activated. The MPU 100 outputs write data to the AD bus 06 from the second half of the subsequent timing T2.

When the SELM signal 401-10 becomes active, the bus control unit 401-9 enables the WR signal 100-3 output in period 3, and transfers the write data output to the AD bus 06 to the MD It is written into the data memory 401-12 pointed to by the address information in the AL 401-3 through the bus 01-8 in synchronization with the rising edge of the WR signal 100-3.

〔Effect of the invention〕

As explained above, by incorporating a device select circuit into a semiconductor device, the present invention eliminates the need for additional hardware such as latches, decoders, drivers, etc. between a microprocessor, memory, and peripheral input/output devices. The processor and memory can be directly connected, making it possible to create a very compact system configuration, and also improve the reliability and economic efficiency of the entire system. , it is also possible to write to PROM in memory, so when adding an address space or allocating a device requires moving the address, the software rewrites the device select information, and allocating the device moves the address to the address space. It also has the effect of making it possible to map to any address in .

[Brief explanation of the drawing]

FIG. 1 shows memories 101 and 102 which are a first embodiment of a semiconductor device with a device select circuit according to the present invention. 103 and 104 are used, FIG. 2 is a block diagram showing details of the memory 101 in FIG. 1, and FIG. 3 is a block diagram showing the PROM in FIG. 2.
An explanatory diagram showing the functions of 101-1, Figures 4 and 5 are
A timing chart showing the operation of the memory 101 shown in FIG. 6 is a timing chart showing the operation of the memory 101 in FIG.
02, 403, and 404, FIG. 7 is a block diagram showing details of the memory 401 in FIG. 6, and FIG. 8 is a block diagram showing the memory 401 in FIG.
Explanatory diagram showing the functions of ROM 401-1, Fig. 9, Fig. 1
0 and 11 are timing charts showing the operation of the memory 401 in FIG. 6, FIG. 12 is a configuration diagram showing a conventional example of this type of device selection method, and FIGS. 3 is a timing chart showing the operation of a conventional example. 100...MPU. 100-1...Al-E signal, 100-2...RD and other signals 100-3...WR signal, 101, 102, 103, 104, 401,
402, 403. 404--Memory, 101-1. 101-2. 101-3. 101-4. 101-5. 101-7. 101-8. 101-9. 106...A 40l-11...PROM. 401-2...AR. 401-3...ALL 401-4...MA bus 401-5...-several circuits, 401-7...AR control circuit 401-8...MD bus 401-9...bus control Circuit D bus.

Claims (1)

[Claims] 1. In a semiconductor device having a memory section including at least a rewritable non-volatile memory, a reference address register for holding device select information, and referencing device select information set in advance at the time of initialization. An address register control circuit that is held in the address register, an address holding circuit that holds address information from the microprocessor for selecting the semiconductor device, and data held by the reference address register and the address holding circuit are compared and a match is made. a comparison circuit that outputs a match signal when the comparison circuit outputs a match signal; and a bus that allows the microprocessor to access the address in the memory section corresponding to the address information held by the address holding circuit when the comparison circuit outputs a match signal. 1. A semiconductor device comprising: a control section.