JPH03282959A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To allow time values counted up respective timers to accurately coincide with each other by providing respective processor modules with timers and simultaneously initializing respective timers by the same initializing signal. CONSTITUTION:Respective processor modules 1a to 1n are provided with respec tive timer parts 11 to be accessed by respective processors 12. These time parts 11 are simultaneously driven by using a timer signal outputted from a timer signal generator 13 connected to respective modules 1a to 1n in common and current time values counted up by respective timer parts 11 are stored in respec tive regesters 3b. On the other hand, respective timer parts 11 are simultaneously initialized by a timer initializing signal which is common to the system. In the system with the above constitution, all the current time values obtained by respective timer parts 11 are equal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Configuration of the Invention (Field of Industrial Application) The present invention relates to a multiprocessor system that can reliably and accurately manage individual timers in a plurality of processor modules.

(Prior Art) A conventional general multiprocessor system has a plurality of processor modules la, for example, as shown in FIG.
Commonly connect lb and ~in to system bus 2 and ζ
Furthermore, a timer module 3 and a shared memory 4 are connected to this system bus 2.

The timer module 3 measures a predetermined timer signal using its timer signal source 3a to obtain the current time, and each of the processor modules la, lb, ~in uses the current time on the system bus 2. The data are stored in registers 3b that can be accessed through the respective registers 3b. The processor modules la, lb, ~1n that wish to know the current time measured by the timer Φ module 3 access the register 3b of the timer module 3 via the system bus 2, and write the information in the register 3b. The stored current time information will be read out individually.

However, when a plurality of processor modules simultaneously require the current time, they issue bus access requests to the system bus 2 at the same time and attempt to access the register 3b, which naturally causes contention.

Then, only the processor module for which the right to use the system bus 2 has been selectively set can read the current time from the register 3b, and the other processor modules are forced to wait until the right to use the bus is set. Become. Of course, even if the processor modules are using the shared memory 4 via the system bus 2, the processor module that requires the current time will be forced to wait until it is granted the right to use the bus.

Therefore, in such a case, even though the current time is required, register 3b cannot be accessed until the right to use the bus is set, so as a result, the current time cannot be accessed in real time. you won't be able to get it.

Such problems occur more frequently as the system bus 2 is used more frequently, and it becomes increasingly difficult to obtain the current time in real time.

In addition, in the system configured as described above, data access efficiency is improved and each processor module la, l
In order to reduce the frequency of access to the system bus 2 from the processor modules la, ln,
In many cases, cache memories are provided between each of the system bus 2 and the system bus 2. Each cache memory provided in this manner is normally controlled so that the consistency of its data is maintained.

However, in a system equipped with this type of cache memory, the current time measured by the timer module 3 as described above is stored in each processor module la.
, 1b, to 1b respectively. Since the current time measured by the timer module 3 changes every moment, each processor module la,
The current times stored in the cache memories lb and .about.lb will become invalid at the next instant. Therefore, when it becomes necessary to refer to the current time next time, the timer module 3 is again accessed via the system bus 2.
It is necessary to access register 3b of .

That is, regarding the current time measured by the timer module 3, the above-mentioned cache memory does not work equally effectively, and in the end, even if the cache memory is provided, the above-mentioned problems cannot be solved to the same extent.

In order to eliminate such problems, for example, as shown in FIG.
n respectively the timer signal source 3a and register 3b described above.
A system has been considered in which a timer unit 11 is provided, and each processor 12 of each processor module la, lb, to 1n internally obtains the current time from the timer unit 11. According to the system configured in this way, each processor module la, l
Since the processors 12 of B and 1n only have to access the timer section 11 in each module individually, the problem caused by the contention of the system bus as described above, that is, the time required for access to obtain the current time, is avoided. No problems like this will occur.

However, each processor module 1a, 1b, ~I
Initialization of the timer section 11 provided in each of the processor modules la, lb, to In is performed separately for each processor module la, lb, to In. Moreover, the current time measured by each timer section 11 is obtained by independently measuring each timer signal. Therefore, due to timing errors in initialization settings and errors in each timer signal source, each processor module l
Errors are likely to occur in the current times measured by the timer units 11 of a, lb, and ~In.

Therefore, a plurality of processor modules la, lb, ~
1n, even if each of the processors 12 accesses the timer unit 11 in the module at the same time, there is no guarantee that each of these processors 12 will obtain exactly the same current time. Therefore, there are problems when using the above-mentioned timer to debug a multiprocessor system or record the times at which various events occur.

(Problem to be Solved by the Invention) As described above, in the conventional bus-coupled multiprocessor system, multiple processor modules access timer modules connected via the system bus to obtain current time information. However, there is a problem in that it is often impossible to accurately read the current time due to delays caused by bus contention.

Moreover, such a problem could not be solved even by using a cache memory.

On the other hand, if each processor module is provided with a portion of its timer, the above-mentioned problems can be resolved, but on the other hand, it is difficult to accurately match the current time measured by each portion of the timer. And in the end,
There is a problem in that it is not possible to obtain accurate current times among multiple processor modules.

The present invention has been made in consideration of these circumstances, and its purpose is to provide a multiprocessor system with a simple and highly practical configuration in which the current time can be accurately obtained from each of a plurality of processor modules. Our goal is to provide the following.

[Structure of the Invention (Means for Solving the Problems) The present invention relates to a multiprocessor system configured by interconnecting a plurality of processor modules, wherein each of the processor modules is accessible from the processor. Each timer is provided, and each of these timers is simultaneously initialized using the same timer initialization signal, e.g., a system reset signal, and the same timer signal, e.g., a system clock signal, or by dividing the frequency of this system clock signal. This is characterized in that each of the two signals is driven using the following signals.

Furthermore, apart from each of the above-mentioned timers, a reference timer is provided that operates constantly regardless of whether the system is in operation or not.
The present invention is characterized in that when initializing each of the timers, the current time measured by the reference timer is saved in a register that can be accessed from each of the processor modules.

The present invention is characterized in that the time saved in the register is used to calculate the current time with respect to the time measured after the timer is initialized.

(Function) According to the system configured as described above, the timers provided in each processor module are simultaneously initialized using a system reset signal when the system is started, and thereafter, the system clock signal is commonly used. Since each of the timers is driven by each timer, the time measured by each timer provided in each processor module can always be made equal to each other.

Therefore, when a processor in a processor module needs to refer to the current time, it can read the current time directly from the timer in that processor module without going through the system bus, which eliminates bus access conflicts like in conventional systems. There will be no access delay due to this.

As a result, even if multiple processors need to refer to the current time at the same time, each processor can obtain the current time at the same time.

Further, according to the above-described configuration, since the system bus is not used for accessing the current time, the frequency of use of the system bus is reduced, and the problem of bus traffic is alleviated. As a result, it becomes possible to prevent the performance of the entire system from deteriorating.

(Embodiment) A multiprocessor system according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the system of the first embodiment, where la, lb, ~1n are processor modules connected to the system bus 2, and 4 is a processor module connected to the system bus 2.・Module l
This is a shared memory shared by a, lb, and ~In.

However, the feature of this system is that each of the processor modules la, Ib, to 1n is provided with a timer part 11 that is accessed by the processor 12 thereof, and these timer parts 11 are The modules 1a, 1b, . The point is that each is stored in the register 3b. Further, the timer sections 11 provided in each of the processor modules 1a, lb, to 1n are initialized all at once using a timer initialization signal common to the system, for example, a system reset signal. There is.

That is, the timer signal generator 13 generates a timer signal (
For example, the system clock signal or its frequency divided signal) is generated for each processor module la, lb,
The timer sections 11 provided at the respective terminals 1 to 2 are initialized all at once in response to an initialization signal such as a system reset signal, and then count the timer signals. By counting this timer signal, the register 3b in the timer unit 11 of each processor module la, lb, to 1n increments the held data indicating the current time by [1].

The initialization signal may be a system reset signal that is issued once when the system is started, or may be a reset signal that is generated by a processor module according to a predetermined program.

According to the system configured in this manner, the timer sections 11 provided in each of the processor modules la, lb, ~in are initialized all at once at a common timing, and then simultaneously receive the same timer signal. Since the current time is determined by counting, the current times obtained by each of these timer sections II are all equal. Moreover, if each processor 12 needs the current time, it can access the timer unit 11 provided in that processor module independently from other processors, so the current time can be referenced in real time. becomes possible.

Therefore, it is possible to effectively utilize it for purposes such as creating an accurate time chart of the processing contents of each processor 12 for the purpose of depacking.

Furthermore, according to such a system configuration, there is no need to access the system bus 2 to reference the current time, so even if multiple processors 12 need to reference the current time at the same time, there is no bus contention as in conventional systems. never occurs. In other words, each processor can access the current time independently without interference from other processors. As a result, even when performing database management that frequently refers to the current time, each processor 12 can refer to the current time in real time.

Furthermore, even if a cache memory is provided between each of the processor modules 1a, lb, ~1n and the system bus 2, each processor 12 can operate as described above without depending on the function of the cache memory. The current time can be determined in real time, and problems with conventional systems can be effectively resolved.

By the way, in the above-mentioned system, the timer sections 11 provided in each of the processor modules la, lb, -in respectively measure the elapsed time from the time when the system reset signal is received.

However, as a system specification, it is often desired to obtain the current time as standard time rather than the elapsed time described above.

In such a case, the system may be configured as shown in FIG. 2, for example.

The system shown in FIG. 2 is backed up by a backup power supply to the system bus 2, always generates a timer signal of a predetermined period regardless of whether the system is in operation or not, and measures this timer signal to determine the current time. The present invention is characterized in that it is provided with a reference timer 14 for obtaining . The reference timer 14 includes a timer signal source 3a that generates the timer signal of the predetermined cycle, and a first register 3b that stores the current time obtained by regularly measuring the timer signal, and The second register 3c is configured to compare and store the current time when the timer initialization signal (system reset signal) is received.

In addition, each processor module la, 1b, ~In is,
Although FIG. 3 shows an example of a configuration in which the timer unit 11 and the processor 12 are connected via an internal bus, and the local memory 15 is further connected to the internal bus, basically the structure is similar to that shown in FIG. The system is configured similarly to the example system shown.

However, in a system configured in this way, the timer units 11 provided in each processor module la, lb, ~1n are initialized all at once in response to a system reset signal, and then receive a common timer signal. The current time common to each module is determined by measuring the time of each module at the same time. Compared to each timer unit 11 that performs such a time measurement operation, the reference timer 14 receives a system reset signal obtained in the register 3b when each timer unit 11 is initialized. The current time To is saved in the second register 3c and is saved therein. This second register 3c is provided so that each processor module la, lb, ~in can access it as appropriate via the system bus 2, and each processor 12 has a system stored in the second register 8c. The time Te at the time of reset can be read out for reference as appropriate.

Here, each of the processor modules la, lb, ~
The current time measured by the timer section 11 of 1n is a system-specific time after being initialized by the system reset signal described above. On the other hand, the time measured by the reference timer 14 can be said to be an absolute time because it is constantly measured regardless of whether the system is in operation or not. The time Tc at the time of initialization by the system reset signal described above is stored in the register 8c of the reference timer section 14.

Therefore, when a processor module 1a, 1b, to 1n needs absolute current time, the processor 1
2 accesses the reference timer 14 via the system bus 2 and reads out the initialization time Tc saved in the register 3c. Then, the current time To measured by the timer section 11 of the processor module is read out, and the absolute current time is determined from this time information.

Note that the absolute current time is calculated as [To + Te] when the unit systems of the above-mentioned times To and Tc are the same.

The absolute current time obtained in this way is always advanced because the current time To obtained by the timer section 11 is advanced by the time difference even if the timing at which each processor 12 accesses the register 3c is different. Accurate and absolute current time is required.

In addition, each of the above-mentioned processor modules 1a, 1b, ~In
If information about the current time To is stored in the local memory 15 of the computer, there is no need to access the timer section 11, so that the absolute current time can be determined earlier.

According to the system configured in this way, in addition to the effects of the previous embodiment, it is possible to always accurately and easily obtain the absolute current time.

It should be noted that the present invention is not limited to the embodiments described above, and it goes without saying that various modifications can be made without departing from the spirit of the invention. Needless to say, the present invention is also applicable to a system in which each processor is provided with a cache memory.

[Effects of the Invention] As explained above, according to the present invention, a timer is provided for each of the plurality of processor modules constructing a multiprocessor system, and each of these timers is initialized all at once by a common timer initialization signal. After that, the clocks are driven simultaneously using the same timer signal, so that it is possible to accurately match the times measured by each timer. Since the time measured by each of these timers can be accessed and read internally for each processor module, it is possible to read the current time in real time without causing interference with other processors. A great practical effect can be achieved, such as making it possible to obtain each of these.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a multiprocessor system according to one embodiment of the present invention, FIG. 2 is a block diagram showing a schematic configuration of a system according to another embodiment of the present invention, and FIGS. 3 and 4 are diagrams for explaining the problems of the conventional system. 1a, 1b, ~1n...processor module, 2
...System bus, 3...Timer module, 3
a...Timer signal source, 3b...Register, 3c...
- Register, 4... Shared memory, 11... Timer unit, 12... Processor, 13... Timer signal generator, 14... Timer signal source, 15... Local memory.

Claims (4)

[Claims] (1) In a multiprocessor system configured by interconnecting a plurality of processor modules, each processor module is provided with a timer that can be accessed from the processor, and each of these timers is controlled by the same timer initialization signal. What is claimed is: 1. A multiprocessor system characterized in that the multiprocessor system is simultaneously initialized by the processors and driven by the same timer signal. (2) A system reset signal is used as the timer initialization signal, and a system clock signal or a signal obtained by frequency-dividing the system clock signal is used as the timer signal. processor system. (3) In a multiprocessor system configured by interconnecting a plurality of processor modules, each processor module is provided with a timer that can be accessed from the processor, and the system is controlled when the system is in operation or not. A reference timer is provided that operates steadily without any noise, and each of the timers is simultaneously initialized by the same timer initialization signal, and each of the timers is driven by the same timer signal, and each of the timers is simultaneously activated by using the timer initialization signal. A multiprocessor system characterized in that, upon initialization, the current time measured by the reference timer is saved in a register that can be accessed from each of the processor modules. (4) Claim (3) characterized in that the time saved in the register is used to calculate the current time with respect to the time measured after the timer provided in each processor module is initialized. The multiprocessor system described in .