JPH03282963A - Interruption address correcting processing system - Google Patents

Abstract

PURPOSE:To simplify the correcting processing of an interruption address by transferring the contents of a correction value register to a scalar unit at the time of generating a program exception, and allowing the scalar unit to correct an old program status word value. CONSTITUTION:A decrement IAMA (correction value) control part 16 is provided with a control instruction pending signal ON/OFF latch 18 to be set up by the input of a control signal or reset by the end of the control instruction. In an increment IAMA control part 17, the contents of a correction value register 19 are increased only in a normal execution mode. When a debugging mode is held at the end of the control instruction, the register 19 is cleared to zero. This is because only decrement is executed during the period of the debugging mode and the contents should be canceled. Thus, the contents of the register 19 are updated, and when a program exception is generated, the contents of the register 19 at that time are informed to the scalar unit 101, which corrects an old program status word value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an interrupt address correction processing method for dealing with the occurrence of a program exception in a parallel processing computer having a scalar unit, a vector unit, and a main storage device.

The purpose of this invention is to easily perform correction processing when correcting interrupt addresses when parallel processing is executed.

A correction value register is provided that indicates the length of the vector instruction that was not executed when an interrupt occurred, and a control instruction pending signal is also provided. (ii) when a vector instruction is supplied to the vector unit, the contents of the correction value register are changed in a first direction; and (ii) when the vector instruction is completed while the debug mode is on, the contents of the correction value register are When a program exception occurs, the content of the above correction value register is used to update the old program status.
Configure to correct word values.

[Industrial application field]

The present invention relates to an interrupt address correction processing method for dealing with the occurrence of a program exception in a parallel processing computer having a scalar unit, a vector unit, and a main memory.

In so-called vector computers, instructions are executed in parallel between vector instructions and scalar instructions, or between vector instructions, and when a program exception occurs with a vector instruction, the old program status It is not possible to predict whether the instruction address of word C (abbreviated as PSW) indicates the next instruction in which the two exceptions occurred. For this reason, the old PSWO value is corrected, but its control is complicated.

[Conventional technology]

In parallel processing computers such as the vector calculator mentioned above.

Because parallel execution is performed between instructions, when a program exception occurs in a certain instruction, the old PSW does not necessarily indicate the next instruction that caused the exception.

Therefore, in order to make it easier to debug programs, a debug mode is provided, and in this mode, when three exceptions occur, the old PSW is controlled to point to the next instruction after the instruction that generated the exception. . In this debug mode, parallel execution of scalar instructions and vector instructions is prohibited.

When vector instructions are transferred from the scalar unit to the vector unit, the PSW is updated and buffered within the vector unit.

When an exception occurs in a certain vector instruction, it becomes necessary to return the addresses of the unexecuted vector instructions from the old PSW. This old psw correction value (l A
M A: In5tructionAddress
The control for decrementing/incrementing Modify Amount is complicated.

[Problem to be solved by the invention]

The debug mode is defined by a bit in a vector control register (hereinafter abbreviated as VCR) in the vector unit, and the VCR is updated by vector control instructions.

Therefore, there are the following problems.

■ When debug mode is OFF, that is, in normal execution mode, multiple instructions may finish at the same time, so IAMA
cannot be incremented.

■ Since the control command may switch the debug mode 0N10FF, in the decrement control unit for IAMA, even if the value of the VCR is not in the debug mode, if there is a control command waiting to be executed in advance,
Need to be decremented.

■ When the debug mode is OFF, that is, in the normal execution mode, if the program interrupt code indicates a completion type exception (for example, an arithmetic exception), the instruction up to the instruction address indicated by the old PSW must be completed. . However, from the instruction that caused the completion type exception, the old PSW
If there is a control instruction before the instruction indicated by , this control instruction cannot be executed. This is because the control instruction may switch the debug mode ON10 FF, and if it switches here, the control will be severely disabled. to become difficult to
This is because the control command is executed after all preceding commands have been completed, and this completion condition also includes late-breaking processing. Therefore, correction of the PSWO value by IAMA may be necessary even in the 9 normal execution mode.

The present invention takes the above-mentioned points into consideration and aims to facilitate correction processing when correcting interrupt addresses when parallel processing is executed.

[Means to solve the problem]

FIG. 1 is a diagram illustrating the principle of the present invention with reference numeral 101 in FIG.
is a scalar unit, 102 is a vector instruction 1-. 1
03 represents the main memory, and the vector unit 102
11 is a vector instruction input stage, which receives a vector instruction supplied from the scalar unit O1. Reference numeral 12 denotes a vector instruction buffer for buffering the received vector instructions. 13 is a command management vibe section, which includes load/store vibes 13-1 and 9.
It is provided with a multiplication/division/addition/subtraction pipe 13-2 and a mask pipe 13-3 used for mask processing. 14 is a vector instruction termination stage, which executes necessary processing when any one vector instruction is terminated.

Furthermore, 15 is a vector control register, and the bit in it controls the debug mode (
Hereinafter, the non-normal execution mode, advance mode, advance control mode, or ADVANCE-ON) is indicated. mode).

16 is the decrement IAMA@m section.

When a vector command is accepted, an instruction is given to decrement the contents of a correction value register (IAMA register) 19, which will be described later, under predetermined conditions. 17 is inkmelint IA
M, 6Jll? Part 11 instructs to increment the contents of the correction value register 19 under predetermined conditions when the vector command is completed.1B is a control command pending signal on/off latch; The control command pending signal is kept on until the control command is received by the command input stage 11 and completed. 19 is a correction value register.

20 is a 1 selection circuit which changes the contents of the correction value register 19 by (i) clearing to zero, (ii) incrementing by +6 (since the vector instruction is 6 bytes), (i)
n) -6 decrement is selected. Further, ADVANCEON10FF in the figure is a signal indicating whether the above-mentioned non-normal execution mode or normal execution mode is present.

[For production]

■ Decrement In the IAMA control unit 16, a control command pending signal on/off latch is set upon input of a control command and reset upon completion of the control command (hereinafter, 5QPENDING may be displayed as ON when the latch is on) It has 18. The conditions under which the control unit 16 decrements the correction value register 19 are as follows.

(ADVANCE-OFF+5Q- PENDING) (Vector command input).

■ In the increment IAMA control unit 17.

Correction value register 19 only when ADVANCE-OFF
Increment. What are the conditions?

(ADVANCE-OFF)・ (end of vector instruction) It is.

■ When the control command ends, ADVANCEON
If so, the correction value register 19 is cleared to zero. This is to cancel the decrement described above, which is only being performed while 5Q-PENDING is ON.

In this way, the contents of the correction value register 19 are updated,
When a program exception occurs, the contents of the correction value register 19 at that time are notified to the scalar unit node 101 side, and the old PSWO value is corrected on the scalar unit node 01 side.

〔Example〕

Figure 2 shows that even if a control command is input and executed in the ADVANCE-OFF state, the ADVANCE-OFF state is
The figure shows the processing mode when the CE-OFF state is maintained.The figure shows the processing status of the vector instruction input stage 11 and the vector instruction end stage 14 separately in the horizontal direction, and the downward direction shows the processing status of the vector instruction input stage 11 and the vector instruction end stage 14. It represents the direction (
below.

The same applies to Figures 3 to 7).

In the illustrated case, one animal is initially in the ADVANCE-OFF state, and (i) decrement every time a vector command is received in the vector command input stage 11) IAMA control unit 1
6 decrements the contents of the correction value register 19, and (i
i) Every time a vector instruction ends in the vector instruction end stage 14, the IAMA@ll1 unit 17 increments the contents of the correction value register 19.
Although SQ-PEMD ING is turned on due to the supply of SQ-PEMD ING, the processing for the correction value register 19 remains unchanged, and the above control command is executed. ADVANCE
Since there is no change in the -OFF state, the processing for the correction value register 19 is unchanged from the beginning.

FIG. 3 shows a processing mode when the ADVANCE OFF state is changed to the ADVANCE-ON state by a control command. In this case.

As can be seen by comparing with FIG. 2, since the ADVANCE-ON state is entered by the execution of the control command, the prohibition of parallel processing is lifted.

Since the contents of the correction value register 19 eliminate the need to correct the old PSWO value, the contents of the correction value register 19 are cleared to zero and left as they are.

Figure 4 shows that even if a control command is input and executed in the ADVANCE-ON state, the ADVANCE-ON
The processing mode when the E-ON state is maintained is shown. In the illustrated case, one horse is in the initial ADVANCE-ON state, and (1) even if a vector command is received at the vector command input stage 11, the contents of the correction value register 19 are not decremented, and (ii) the vector Even if the vector instruction ends in the instruction end stage 14, the contents of the correction value register 19 are not incremented. Then, a control command (SQ-INST) was supplied during the process.

The control command pending signal on/off latch 18 is turned on (SQ-PEND ING).

(ii) From now on, every time a vector instruction is received in the vector instruction input stage 11, the decrement IAMA control unit 16 decrements the contents of the correction value register. 17 is correction value register 1
Continue not incrementing 9. The above control command is executed, but in the case shown in Figure 9, the above ADVANCE-ON state does not change even after this execution. In this case, the contents of the correction value register 19 are cleared to zero, and the cleared state continues thereafter.

Figure 5 shows that the ADVANCE-ON state is ADVANCE.
- The processing mode when the state is changed to OFF is shown. In this case, as can be seen from the comparison with FIG. 4, from the time when the control instruction is executed and the state is changed to ADVANCE OFF, every time the vector instruction is completed thereafter, the increment IAMA@@ unit 17 is set to the correction value register The contents of are incremented.

FIG. 6 shows a processing mode when a program exception occurs before a control instruction (SQ-INST) is executed under the ADVANcE-OFF state.

In this case, the vector instruction before the control instruction is executed
, a completion-type, abort-type, or suppressed-type exception occurs. Therefore, the instructions after vector instruction (1) are buffered in the vector unit 102 without being executed, and are cleared during the second interrupt processing. In the case shown in FIG. 6, the correction value register 19 is not incremented after one exception occurs. As a result, the contents of the correction value register 19 are as follows.

It is from the address following vector instruction 1 to the address indicated by the old PSW. That is, only the values corresponding to vector instructions that were not executed exist in the correction value register 19. Therefore, the contents of the correction value register 19 are notified to the scalar unit 101 side, and the scalar unit 101
By correcting the old PSWO value on the side, it is possible to know the next instruction after the vector instruction vl in which one exception occurred.

In addition, as a case corresponding to Fig. 6, the control command (SQ-IN
The case where an exception occurs after ST) is executed is considered. In this case, it becomes first-order. That is, suppose that even if a control instruction is executed, the ADVANCE-OFF state remains and an exception occurs in a vector instruction after the control instruction.

This is because ADVANCE remains OFF.

This is exactly the same as the case described with reference to FIG.

Further, if an exception occurs after the control command is executed and the state changes to ADVANCE-ON, there is no need to perform correction based on the contents of the correction value register 19, as in the case shown in FIG.

Figure 7 shows the control command (
In this case, a completion-type exception occurs in the vector instruction V, which shows the processing mode when a program exception occurs before SQ-INST) is executed. When a completion type exception occurs, either the process up to the point indicated by psw is executed regardless, or the process up to the point immediately before the control instruction is executed regardless. Therefore, in the case shown in FIG. 7, the instructions immediately before the control instruction (3Q-INST) are executed, while the contents of the correction value register 19 are After that, it is decremented. Therefore, the contents of the correction value register 19 are the control command (SQ-
1N5T) to the address indicated by the old PSW.

From this, it is sufficient to notify the contents of the correction value register 19 to the scanning unit 101 side and correct the old PSWO value.

In addition, as a case corresponding to FIG. 7, the control command (SQ-I
The case where an exception occurs after NST) is executed is considered. In this case, it becomes 9th order. That is, even if the control command is executed, ADVANCE-ON remains on, and if an exception occurs under this state, this state is exactly the same as that described with reference to FIG. 4, and the correction value register 1
There is no need to perform correction based on the contents of 9.

Further, if an exception occurs after the control instruction is executed and the switch is made to ADVANCE OFF, then the entire process is equivalent to the case described with reference to FIG.

FIG. 8 is an explanatory diagram illustrating the configuration of an instruction unit in a vector unit; the VFS shown in FIG.

VPS, VQS, MR3, VSS, VVS.

VUS, VWS are processing stages of pipeline processing. Further, 108 represents an instruction management unit (I-unit), and SUO and SU1 in FIG. 9 represent scalar units. The configuration of each part will be briefly explained below.

■ SIJ interface control unit = 40 Receives vector instructions and scalar data from the scalar unit 101 (StJ), and controls the transmission of write data to the GR register and ER register. In the illustrated case, two SCARA units communicate simultaneously.

■ Pipeline control unit The pipeline control unit decodes vector instructions received from the scalar unit and sends them to the VS-UNIT (memory access processing unit) 109 and VB-UNIT (arithmetic processing unit) 10.
7 to execute the command. The pipeline consists of the following 9
Consists of stages.

-V F S (vector fetch stag
e): Reception of command data VPS (vector predecode)
stage): Instruction decoding and exception checking VQS (vector queue stage)
: Instruction queuing and execution start-V RS (vector read stage)
: Management of VR or MR readout period VSS (vector 5et-up stag
e): Management of execution result output-VTS (vector teri+1nates
:Management of writing period to VR or MR-VVS (vector vanish st
age): Management of convergence cycle of 5calar Write command VUS (vector unit s
vector warning stag): Handling of exception conditions - VWS (vector warning stag)
e): Maintaining exceptional conditions and updating IAMA The main components of the pipeline control section will be explained below.

a. Pipeline register: 23 to 30 This is a register that holds information such as instruction codes, data, exception conditions, and control tags for each stage of the pipeline.

b, V F S RO~1 (vector f
etch stage register): 21
, 22 are pipeline registers of the VF stage (VFS) that hold instructions and data received from the scalar unit (SU). There are 2IJl for SUO/SUI.

c, SDB (scalar data buff
er): A buffer that holds scalar data sent from the 31SU. It is separated into memory access instructions and arithmetic instructions.

■ Process the scalar data sent to the scalar write control unit SU. The components are shown below.

a. Scalar data processing unit: 34 SCALARWRITE command (SUM, F IND,
■ Post-processing of scalar data in EXTRACT)
■Execute on stage (VVS). There are two sets for SUO/SOL.

b, 5WDRO~1 (SU write dat
a register): 36, 31 SU This is a register that holds data to be transmitted. There are two sets for SUO/SUI.

■ Process Control Unit The process control unit performs instruction exception handling and vector unisoto (VU) machine change processing. SUO/5LI
There are 2 & Il each for I. The main components are shown below.

a, V CR (vector control re)
(gister): A vector control register that holds 15VU control information and interrupt codes.For example, it is 32 bits and 3 words.

VUT (vector unit tiger)
) / V WT (vector wait ti+5e
r): This is a timer that counts the processing time and execution waiting time of 39 vector instructions, for example, every 1 microsecond.

I AM A R (instruction address)
ss @odifyasount register)
: 19 (correction value register), correction value (I
This is a register for counting AMA) (see FIG. 1).

State control unit: 41 This is a VU state management mechanism. State transitions are performed based on exceptions detected by the VU, machine checks, etc. There are four states:

PROCESS State-EχCEPTION State MACHINE CHECK State CHECK
5TOP State ■ SU interface operation (received data format) For one vector instruction, the SU transfers 4 bytes of data four times in succession. In the first two times, the instruction code (
6 bytes) and control information (FCR, PSW, CR15
IV (instruction vali)
d) Transfer with the signal.

In the latter two times, information about the operands is stored in DV (data
valid) signal.

There are two types of vector instructions: VR format and ■X format. FIG. 9 shows the transfer contents determined by the command format.

(Relationship with pipeline) Figure 10 shows instruction execution and IA when ADVANCE-OFF.
Regarding MA updating, the ADD command will be taken as an example. Vl
-UNIT20 pipeline is 1'5t as shown in Figure 9
It starts from the next cycle after receiving lV. The VHS and VTS stages are variable depending on the number of vector read accesses.

The contents of the correction value register (IAMA) 19 are decremented by -6 two cycles after the command reception is completed, and needless to say, as the commands are received one after another, the value of the correction value register 19 changes to -12, -18°, etc. ...becomes. Each time an instruction is completed, the contents of the register 19 are incremented by 6 in the next cycle of the vWS stage. However, IAMA is updated only in non-preemptive control mode, and in preemptive control mode,
is always 0. Further, as described above, when the control command is transferred to the vector unit, updating is performed even in advance control mode.

FIGS. 11(A), 11(B), and 11(C) show control circuits for the correction value register. Reference numeral 18 in the figure represents the control command pending signal on/off latch shown in FIG. 1, 42 to 45 represent AND circuits, and 46 to 49 represent OR circuits.

The input signals and output signals shown in the figure have the following contents, respectively. That is.

(a) +FST3: The instruction is transferred from the scalar unit 101 to the vector unit 102 by applying Δτ, but at this time, the 4th τ fetch stage timing 3 (Fetch Sta
ge Timing3-FST3), and the signal child FST3 represents this 4th τ.

(b) 15Q-INST This is a signal obtained by decoding the operation code of the instruction when the vector instruction is transferred from the NISCARA unit 101 to the vector unit 102, and indicates that it is a control instruction.

(c) 15TART-3Q: Is the control command W y Q S shown in FIG. 10? Indicates that you started from the stage.

(d) +RUPT-CLEAR: Represents a clear signal at the end of interrupt processing.

(e) +ADVANCE-OFF: This is the same as the AD-OFF signal as explained in connection with FIG. 2, and indicates that parallel processing is possible.

(f)+DEC-IAMA: Instructs to decrement the value of IAMA.

(g) +DECREMEN'r-IAMA-3PCL: 5Q-IN when a completion type exception occurs under AD-ON
Indicates when the ST signal is waited.

(h)+DEC-IAMA-TRtJE :LA M
Represents decrementing the AO value.

(i) +1NSTRUCTTON-END: Indicates the end of the instruction.

(j) No completion type interrupt: Indicates that it is not a completion type interrupt.

(k) Not a control command that changed from +AD-〇N to OFF: Indicates that this is not a control command that instructs to change from AD-ON to AD-OFF.

(1) + I NC-I AMA-TRUE :I A
Indicates that the value of MA is to be incremented.

(m) +ADVANCE-ON: This is the same as the AD-ON signal as explained in connection with FIG. 3, and indicates that parallel processing is prohibited.

(n)+5Q-T N5T-3TART:5Q-IN
Indicates that the ST signal has started.

(0) + side-in processing completed: Indicates that interrupt processing has ended.

(p) + Machine check processing: Indicates that machine chaesok is being performed.

(Q)+5ETO: I represents setting the value of AMA to zero.

This signal is given priority over decrement and increment.

By using the above signals, FIG. 11(A)
In FIG. 11 CB) it is given to decrement I AMA, and in FIG. 11 CB) it is given to increment I AMA.

In FIG. 11(C), clearing IAMA is provided.

FIG. 12 shows a conventional general configuration of a parallel processing computer system to which the present invention is applied.

In the figure, reference numeral 101 is a scalar unit, 102 is a vector unit, 103 is a main memory, 104 is an arithmetic processing section within the scalar unit, 105 is an instruction management section within the scalar unit, 106 is a memory access processing section within the scalar unit, 1
07 is an arithmetic processing section within the vector unit.

10B represents an intra-vector unit instruction management section, 109 represents an intra-vector unit memory access processing section, and 200 represents a memory control unit.

The scalar unit 101 and the vector unit 102 generally perform processing in parallel. That is, the scalar unit 101 instructs the vector unit 102 to perform vector calculation. In the vector unit 102, the vector instructions are buffered in the instruction management section 108, and each vector instruction is pipeline processed while communicating with the arithmetic processing section 107 and the memory access processing section 109. Also within the scalar unit 101, the instruction management section 105 executes scalar instructions while communicating with the arithmetic processing section 104 and the memory access processing section 106.

In normal cases, the parallel processing described above is allowed (advanced off mode), but if necessary, the advanced on mode may be set and execution of both types of instructions mentioned above may be cleared.

Note that the memory control unit 200 shown in FIG. 12 plays a role of controlling access to the main storage device 103.

In the configuration disclosed in FIG.
When a program exception occurs, the command management unit 105 of the Scalar Uninote 101 is notified of this, an interrupt is issued to one interrupt processing execution body (hypervisor HP, VM monitor, host, etc.), and the corresponding processing is performed. be exposed. Furthermore, even if an interrupt cause occurs in scalar unit 01, corresponding processing is performed in the same way.

[Effects of the Invention] As described above, according to the present invention, it is possible to easily perform address correction (correction of IAMA value) when parallel processing of a scalar unit and a vector unit is allowed.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is an illustration of the principle of the present invention.
CE, -OFF Processing mode when continuing from F to ADVANCE-OFF, Figure 3 shows processing mode when changing from ADVANCE-OFF to ADVANCE-ON, Figure 4 shows AD, from VANCE-ON to ADVANCE-O
Processing mode when continuing to N, Figure 5 is ADVANCE
Figure 6 shows the processing when changing from -ON to ADVANCE-OFF, and Figure 6 shows the processing when an exception occurs before the SQ instruction under ADVANCE-OFF.
Processing mode when an exception occurs before the SQ instruction under VANCE-ON, Figure 8 is an explanatory diagram explaining the configuration of the instruction unit in the vector unit Figure 9 is the transfer content determined by the instruction format , Figure 10 is ADVANCE
- Explanation of instruction execution and update of IAMA when OFF, Figures 11 (A), (B), and (C) are configurations of IA'MA control, respectively, Figure 12 is a parallel configuration to which the present invention is applied. The configuration of the processing computer system is shown. In the figure, 101 is a scalar unit (102 is a vector unit), 103 is a main memory, 104.107 is an arithmetic processing unit, 105.108 is an instruction management unit, 10
6, 109 is a memory access processing unit, 200 is a memory control unit, 11 is a vector instruction input stage, 1
2 is a vector instruction processor, and 13 is an instruction management pipe section. 14 is the vector instruction end stage, 15 is the vector control register, and 16 is decrement + AMAl.
Ill? 1 part, 17 is an increment IAMA control part, 1
8 is control command pending signal on/off launch, 1
9 represents a correction value register. Combination of space ADVANCE-OFF-ADVANCE-OFF 2nd opening <Vector command input station><Hex θ command end stage> ADVANCE OFF - ADVANCE ON 0
91st stage <Vector instruction input stage> DECREMENT ■ <Vector instruction end stage> TNC MENT AD-ON ADVANCE ON -ADVANCE ON NCE- In the case of OFF, Figure 5 (-1m+λ caste) (Vector scarlet instruction end stage) AD-OFF An exception occurs before the r-SQ instruction Figure 6 (Vector instruction input stage) (Vector command end stage) OECREMENT 1 ■ AD-ONr: SQ command before command 0 vFE completed fl'J outside t
l Life Figure 7 + + + ÷

Claims (3)

[Claims] (1) Scalar unit (101) that processes scalar instructions
and a vector unit (102) that processes vector instructions.
and a main memory (103), and when parallel execution is performed between scalar instructions and vector instructions or between vector instructions and an interrupt due to a program exception occurs, the old program In a parallel processing computer having a debug mode that ensures that the status word indicates the instruction following the instruction in which the interrupt occurred, a correction value register (19) is provided that indicates the length of the vector instruction that was not executed when the interrupt occurred. A control instruction pending which is set when a control instruction including at least an instruction to turn on/off the debug mode is input to the vector unit (102) and reset when the control instruction is executed. signal is generated, and when a vector command is sent to the vector unit (102) while the debug mode is off or the control command pending signal is on, change the correction value register (19) to the first direction. , when the vector instruction is completed when the debug mode is off, the correction value register (19) is changed to the second direction, and when a program exception occurs, the correction value register (19) is changed to the second direction.
) is transferred to a scalar unit (101), and the scalar unit (101) corrects the value of the old program status word with the content of the correction value register. (2) In the parallel processing computer, the scalar unit (101) is configured to perform scalar arithmetic processing within itself and supply vector instructions to the vector unit (102). The vector unit (102) is configured to buffer the vector instructions supplied from the scalar unit (101) and execute each vector instruction under pipeline processing, and the vector unit (102) When the above program exception occurs in the vector unit (102
) notifies the scalar unit (101) of the occurrence of the exception, and then notifies the scalar unit (101) of the contents of the correction value register. Processing method. (3) The vector unit (102) has a vector instruction input stage (11) that receives vector instructions from the scalar unit (101), and a vector instruction termination stage (14) that handles termination of each vector instruction. The interrupt address correction processing method according to claim 1, wherein an instruction to correct the contents of the correction value register is controlled in response to instructions from both the stages (11, 14).