JPH03286331A - Digital signal processor - Google Patents

Abstract

PURPOSE:To directly read the data outputted from a digital signal processor DSP and to control the DSP by supplying a 2nd clock pulse having the frequency lower than that of a 1st clock pulse to a holding means in response to a switch command. CONSTITUTION:An arithmetic processing means 3 is provided to apply the arithmetic processing to the input digital signal based on a prescribed program and to output this processed signal together with a holding means which holds the output data on the means 3 and outputs the holding data in the timing synchronous with the supplied clock pulse, and a clock pulse generating means which supplies a 1st clock pulse to the holding means synchronously with the action timing of the means 3. Then the clock pulse generating means supplies a 2nd clock pulse having the lower frequency than the 1st clock pulse to the holding means in response to a switching command. In such a constitution, a control means like a microcomputer, etc., can directly read the data outputted from a DSP 2. Thus the DSP 2 is effectively used.

Description

[Detailed description of the invention] Technical field The present invention relates to a digital signal processing device.

BACKGROUND ART In recent years, DSPs (digital signal processors) have been known that can obtain outputs equivalent to circuit operations by performing arithmetic processing such as arithmetic operations on signals obtained by digitizing analog signals at high speed.

The DSP performs arithmetic processing on the input digital signal using arithmetic processing means. The arithmetic processing means basically includes, for example, a data memory for storing input digital signal data and a coefficient memory for storing a plurality of coefficient data, and sequentially reads signal data and coefficient data from the data memory and coefficient memory according to a program and multiplies them. These data values are multiplied by the multiplication device, and the value of the multiplication result is accumulated each time the multiplication is performed. The coefficient data stored in the coefficient memory is written and controlled by an external microcomputer, and is rewritten when changing the content of the arithmetic processing, for example, the filter characteristics applied to the signal obtained by the arithmetic processing. Data resulting from processing by this arithmetic processing means is outputted via an output register.

By the way, in a DSP, each component operates in synchronization with a clock pulse generated from an internal clock generator, and this clock pulse is used to process data such as audio data that requires many steps of operation in a short period of time. When dealing with , it is necessary to be fast. However, when the frequency of the clock pulse is high, data is output from the DSP at high speed, so a normal microcomputer cannot directly read the output data and rewrites the coefficient data in the coefficient memory according to the processing results of the DSP. DSP such as
The problem was that it was not possible to control the

Summary of the Invention [Object of the Invention] An object of the present invention is to provide a digital signal processing device that makes it possible to directly read data output from a DSP and control the DSP in accordance with the processing results of the DSP. be.

[Structure of the Invention] The digital signal processing device of the present invention includes arithmetic processing means for processing and outputting an input digital signal according to a predetermined program, and a processing means for holding output data of the arithmetic processing means and synchronizing with a supplied clock pulse. A digital signal processing device comprising a holding means for outputting held data at a timing determined by the operation of the arithmetic processing means, and a clock pulse generating means for supplying the holding means with a first clock pulse synchronized with the operation timing of the arithmetic processing means, the clock pulse generating means is characterized in that it supplies a second clock pulse having a lower frequency than the first clock pulse to the holding means in response to the switching command.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the digital signal processing device shown in FIG. 1, which is an embodiment of the present invention, an analog audio signal is supplied to an A/D converter 1 and converted into a digital signal. A/
A DSP 2 is connected to the output of the D converter 1. DS
P2 is an arithmetic processing unit 3 that processes supplied digital signal data according to a program, data consisting of coefficient data, signal delay time data, and a program supplied from a microcomputer 7 (described later), and a start command and a stop command for arithmetic processing. It is provided with an interface 4 that relays and supplies the calculation result to the calculation processing section 3, and an output register 5.6 that holds the calculation result output from the calculation processing section 3. Shifting when outputting data from the output register 6 is performed in synchronization with a clock pulse supplied from an MPX (multiplexer) 8. The MPX 8 is supplied with first and second clock pulses, and one of the first and second clock pulses is selectively output in response to a command from the microcomputer 7. The first clock pulse is a pulse that controls the operation timing of the arithmetic processing section 3 and is generated by the clock generator 12. The second clock pulse is a pulse that controls the operation timing of the microcomputer 7, and its frequency is lower than that of the first clock pulse. The output register 5 is supplied with a first clock pulse. D/A converters 9 and 10 are connected to the output registers 5 and 6, and the D/A converters 9 and 10 convert the supplied digital signals into analog signals. Further, the output of the output register 6 is connected to the microcomputer 7.

A microcomputer 7 is provided as a control means, and includes a microprocessor, an interface, and a R
It consists of an AM, a ROM, and a clock generator that generates a second clock pulse. Further, a keyboard 1] is connected to the microcomputer 7.

In this configuration, the digital signal supplied from the D/A converter to the DSP 2 is subjected to arithmetic processing by the arithmetic processing section 3 according to a program.

For example, the arithmetic processing unit 3 performs arithmetic processing operations on the input digital audio signal to obtain filter characteristics for sound field control, and processing operations such as detecting the average level of the input digital audio signal. The result of the arithmetic processing and the signal data at 17 are supplied to the output L register 5 or 6.

The output register 5 holds and shifts signal data in synchronization with the supplied first clock pulse. The output register 6 is normally supplied with a first clock pulse from the MPX 8. Therefore, the output registers 5 and 6 shift and output the held signal data, respectively, to the D/A converters 9 and 10.
supply to.

The microcomputer 7, for example, generates a second clock switching command at predetermined timings as shown in FIG. 2 (step S1), and this second clock switching command is supplied to the MPX 8. Although not shown, the second clock switching command is supplied to the output register 6, and the switching command disables data input to the output register 6. MPX
8 supplies a second clock pulse to the output register 6 in response to the second clock switching command. As a result, the output register 6 shifts and outputs the held signal data in synchronization with the supplied second clock pulse. This shifted signal data is synchronized with the operation timing of the microcomputer 7. Therefore, the microcomputer 7 reads the signal data from the output register 6 (step S2).
), when the reading is completed (step S3), a first clock switching command is generated (step S4). MPX 8 supplies a first clock pulse to output register 6 in response to the first clock switching command. Microphone 0 computer 7 is the first
After generating the tarock switching command, it is determined whether or not it is necessary to change the coefficient data according to the signal data read from the output register 6 (step S5). For example, if the read signal data is data indicating an input average level, if the input average level is equal to or higher than a predetermined value, the first
It is determined whether or not a coefficient data group is being used, and if the human power level is smaller than a predetermined value, it is determined whether or not a second coefficient data group having a value larger than the first coefficient data group is being used. It is to judge. If it is necessary to change the coefficient data, a new coefficient data group is read from the ROM in the microcomputer 7 and transferred to the arithmetic processing section 3 (step S6). The arithmetic processing unit 3 has a coefficient RAM 17 as described later, and the stored contents of the coefficient RAM 17 are updated by the transferred coefficient data group. As a result, the calculation result in the calculation processing section 3 and the filter characteristics of (, 7) are corrected.

FIG. 3 shows a schematic configuration of an arithmetic processing section 3 including an interface 4 and an output register 5.6 in the DSP 2. A digital signal is supplied from the A/D converter 1 to the manual register] 3. A data bus 14 is connected to the input register 13, and this data bus 14 is connected to a data memory 22 for temporarily storing a data group and one input of a multiplier 15. A buffer memory 6 for holding coefficient data is connected to the other side of the multiplier 15. The buffer memory 16 includes a coefficient RAM 17.
is connected, and a group of coefficient data is stored in the RAM 17. One piece of coefficient data is sequentially read from a group of coefficient data stored in the RAM 17 in response to a timing signal from a sequence controller 20, which will be described later, and is supplied to and held in the buffer memory 16. The coefficient data held in buffer memory 16 is supplied to multiplier 15 . An ALU (adder) 18 is provided to accumulate the calculation output of the multiplier 15.
, and the other is connected to the data bus 14 . One accumulator is connected to the calculation output of the ALU 1.8, and the output of the accumulator 19 is connected to the data bus 14. A memory control circuit 24 that controls data writing and reading from an external memory 23 is connected to the data bus 14 . The memory control circuit 24 has a delay time RA for storing a group of delay time data.
M25 is connected, and the memory control circuit 24 writes and reads input audio signal data to and from the external memory 23 so as to delay the audio signal data by each delay time data stored in the delay time RAM 25.

Further, the above-mentioned output register 5.about.6 is connected to the data bus 14.

Register 13, multiplier 15, coefficient RAM 17, ALU 1
8. The operations of the accumulator 19 and the memory control circuit 24 are controlled by the sequence controller 20.

The sequence controller 20 operates according to a processing program written in the program memory 30 and also operates according to instructions from the microcomputer 7. Further, the microcomputer 7 controls rewriting of the processing program and rewriting of coefficient data in the RAM 17 and delay time data in the RAM 25 in response to key operations on the keyboard 11.

In the DSP 2 equipped with the arithmetic processing section 3 having such a configuration, digital audio signal data is input to the manual register 13.
The data is supplied to the data memory 22 via the data memory 22 and stored therein. Note that the sequence controller 20 controls the timing of reading data from the input register 13, the timing of selectively transferring data from the data memory 22 to the multiplier 15, and the timing of reading data from the input register 13.
The timing of outputting each coefficient data from M17, the multiplication operation timing of the multiplier 15, the addition operation timing of the ALU 18, the output tag of one accumulator, etc. are determined.

By taking these timings, the audio signal data input from the data memory 22 is read out and supplied to the memory control circuit 24 via the data bus 14. The memory control circuit 24 sequentially writes the supplied signal data into the external memory 23. On the other hand, the delay time R is determined according to the timing signal from the sequence controller 20.
Delay time data is sequentially read out from the A M 25, and when a delay time specified by the delay time data has elapsed, the signal data is sequentially read out by the memory control circuit 24. Each read signal data is transferred to data bus 1.
4 to the data memory 22 and sequentially stored as delayed signal data.

Further, the audio signal data stored in the data memory 22 or the delayed signal data obtained by the above-described data delay processing are sequentially read out and supplied to the multiplier 5. On the other hand, coefficient data is sequentially read from the RAM 17 and supplied to the buffer memory 16 where it is held. The coefficient data from the buffer memory 16 and the data from the data memory 22 are supplied to the multiplier 15, and the multiplier 15 multiplies them one after another. The value obtained by this multiplication is A
In the LU 18, the value up to the previous time (the value held in the accumulator 19) is accumulated, and the result of the calculation is held in the accumulator 19. In this way, data such as early reflected sound data and filter characteristic processing data are created.

In the above embodiment, the data held in the output register 6 is sent to the microcomputer 7 at predetermined timings.
For example, the arithmetic processing unit 3
The microcomputer 7 may read the held data at the timing when a processing result is obtained.

Further, in the case of data indicating the average value of the human input signal as the data held in the output register 6 read by the microcomputer 7, the program of the DSP 2 is configured so that the arithmetic processing unit 3 creates the average value data as part of the arithmetic processing operation. Preformed.

Effects of the Invention As described above, according to the present invention, the clock pulse for outputting the held data from the holding means for holding the output data of the arithmetic processing means is synchronized with the operation timing of the arithmetic processing means in response to a switching command. from the first clock pulse to the first clock pulse.
Switching to a second clock pulse having a lower frequency than the clock pulse is performed. Therefore, the data held in the holding means can be output at a lower speed than the processing timing of the DSP. Therefore, it becomes possible for a control means such as a microcomputer to directly read the data output from the DSP, and thereby, for example, update the contents of the coefficient memory and the delay time memory according to the read data. It can be used more effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flow diagram showing the operation of a microcomputer, and FIG. 3 is a block diagram schematically showing the configuration of an arithmetic processing section. Explanation of symbols of main parts 1...A/D converter 2...DSP 3...arithmetic processing unit 4...interface 5.6...output register

Claims (2)

[Claims] (1) an arithmetic processing means for processing and outputting an input digital signal according to a predetermined program; and a holding means for holding the output data of the arithmetic processing means and outputting the held data at a timing synchronized with the supplied clock pulse; ,
a clock pulse generating means for supplying a first clock pulse synchronized with the operation timing of the arithmetic processing means to the holding means, the clock pulse generating means supplying the first clock pulse to the holding means in accordance with a switching command; 1
A digital signal processing device characterized in that a second clock pulse having a lower frequency than the clock pulse is supplied to the holding means. 2. The digital signal processing device according to claim 1, further comprising control means for reading output data from said holding means and controlling said arithmetic processing means in accordance with the read data.