JPH03288247A - peripheral controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a controller for a computer peripheral device.

[Prior Art] FIG. 2 is a block diagram showing an example of a conventional peripheral device controller.

This peripheral device controller includes a host interface block 14 that interfaces with the host device.
, a data buffer RAM 12 which is a temporary storage area for data between the host device and peripheral devices, a sequencer/DMA block 11 which controls reading and writing of peripheral devices and transfers data, and a data error detection and correction block. A controller CPU10 that interprets commands from the host device and controls the sequencer/DMA block 11, and a ROM 15 and a RAM 16 attached thereto.

Further, a bus between the host interface block 14, error correction block 13, data buffer RAM 12 and sequencer/DMA block 11 is a data buffer RAM bus 17, and the controller CPU10,
Sequencer/DMA block 11, RA for controller
The bus between M16 and controller ROM 15 is controller CPU bus 18.

[Problems to be Solved by the Invention] However, in the above conventional example, the controller CPU
0 work area RAM 16 and data buffer RAM
12, the bus system is different, and the controller C
Since the data buffer RAM 12 cannot be accessed directly from the PU10, the data buffer RAM 12 cannot be used to store programs for the controller CPU 1O, and there is a problem in that it takes extra access time even when used for data storage.

Furthermore, the conventional example described above has the disadvantage that if a functional failure occurs in the error correction block 5, the entire peripheral device controller becomes inoperable.

The present invention provides controller CPU and data buffer RA.
It is an object of the present invention to provide a peripheral device controller that can more freely utilize two M buses and can effectively deal with the occurrence of an accident.

[Means for Solving the Problems] The present invention provides a method for connecting the controller CPU bus and the data buffer RAM bus in a peripheral device controller in which the controller CPU bus and the data buffer RAM bus exist separately internally. The present invention is characterized in that it is provided with a bus switching control means for controlling the bus switching.

[Function] In the present invention, by providing a bus switching control means between the controller CPU bus and the data buffer RAM bus, devices accessing the data buffer RAM can be switched and disconnected, and peripheral devices By centrally performing memory management within the controller, the reliability of the controller is improved and its functions are expanded.

[Example] FIG. 1 is a block diagram showing one embodiment of the present invention.

Note that this embodiment adds a bus switching control means 3 to the configuration shown in FIG.
AM is omitted, and other constituent blocks are common, so individual details will be omitted.

In this embodiment, a bus switching control means 3 is connected between the data buffer RAM 4 and the error correction block 5 and the sequencer/DMA block 2, and the bus switching control means 3 is further connected to the bus 9 of the controller CPUI. It is.

This allows the controller CPUI to directly access the data buffer RAM 4 via the bus switching control means 3, and at the same time, it becomes possible to control the bus switching control means 3 to disconnect the error correction block 5 from the bus.

Therefore, the controller CPUI can directly access the data buffer RAM 4 for storing programs and data, and can also disconnect it from the bus when a failure occurs in the error correction block 5. become.

With the above configuration, the controller CPUI can directly access the data buffer RAM 4, so programs that are used only temporarily, such as for aging peripheral devices or checking functions in the manufacturing process, can be downloaded from the host to the data buffer RAM 4 and executed. Therefore, unnecessary increase in the program ROM 7 can be prevented.

Further, an error correction program is stored in the program ROM 7, and when a functional failure occurs in the error correction block 5, it can be activated to maintain the function as a peripheral device controller. This is a software correction, so it slows down the operation, but it can take action after notifying the host of such a failure, giving the host leeway to take measures to recover from the failure. , the reliability of the system is improved.

Furthermore, since the RAM for the controller CPU and the data buffer RAM are shared, the RAM for the controller CPU
M becomes unnecessary, and at the same time, the portion of the data buffer RAM used by the controller CPU can be dynamically secured, increasing the flexibility of the system.

[Effects of the Invention] As explained above, by providing the bus switching control means in the peripheral device controller, memory/device management in the peripheral device controller is controlled by the controller C.
This enables the PU to perform operations in a unified manner, and has the advantage that the data buffer RAM can be used for the controller CPU program.

In addition, the error correction block function is implemented by the controller CPU.
It is also possible to replace it with

Furthermore, it is possible to omit the work area RAM for the controller CPU.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing an example of a conventional peripheral device controller. 1... Controller CPU. 2... Sequencer/DMA block, 3... Bus switching control block, 4... Data buffer RAM, 5... Error correction block, 6... Host interface block, 7... Controller CPU ROM, 8...Data buffer R
AM/<S, 9... Bus for controller CPU. Arata Kubo for the same agent

Claims (3)

[Claims] (1) Controller CPU bus and data buffer RA
1. A peripheral device controller in which a bus for a controller CPU and a bus for a data buffer RAM are provided separately in the peripheral device controller. (2) In claim (1), the bus switching control means has a function of electrically disconnecting a faulty functional block, and alternatively executes the function of the faulty functional block by a program of the controller CPU. A peripheral device controller characterized by: (3) The peripheral device controller according to claim (1), wherein a temporarily used program is stored from outside in a data buffer RAM and executed by the controller CPU.