JPH0328985A - Microcomputer - Google Patents

Abstract

PURPOSE:To decrease the number of terminals, to miniaturize a microcomputer, to reduce cost and to make the microcomputer suitable for production with various kinds and small quantity by serially executing the output of addresses and the input/output of instructions or data. CONSTITUTION:A shift register 5 is a converting register for executing parallel/ serial conversion to the value of a program counter 4 and a shift register 6 is used for executing the serial/parallel conversion of data signals inputted from an input/output terminal 2, and further executing the parallel/ serial conver sion of the data signals to be outputted. Address signals and data signals to be serially supplied from an external part are received in terminals 1 and 2 and afterwards, these data are converted from serial data to parallel data and used. Accordingly, the number of the terminals can be decreased in compari son with a case to receive in parallel the data and the instructions, etc., can be easily changed. Thus, the microcomputer can be obtained to be compact, inexpensive and suitable for the production with the small quantity and various kinds.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a microcomputer, and is particularly suitable for low-volume, high-mix production with a reduced number of control terminals. [Prior Art] In a conventional microcomputer, the address Signals and data signals are input and output in parallel via address buses and data paths, requiring a large number of terminals. For example, a typical 8-bit microcomputer in which the address bus and data bus are separated requires a total of 24 terminals, 16 for the address bus and 8 for the data path.

One possible way to reduce the number of address bus and data path terminals is to use a 1-chip microcomputer with a built-in ROM, but since the contents of the ROM are fixed, the program cannot be dynamically changed, and the mask ROM is The type of one-chip microcomputer determines the contents of the ROM at the production stage, so it is suitable for mass production, and is not suitable for low-volume, high-mix applications.

[Problem that the invention seeks to solve]

The conventional microcomputers mentioned above have the disadvantage of having a large number of terminals because the address bus and data path perform input/output operations in parallel.On the other hand, single-chip microcomputers have the disadvantage that the number of terminals can be reduced by incorporating ROM. Since the contents of the ROM are fixed in single-chip microcomputers, the program cannot be changed dynamically, making them unsuitable for low-volume, high-mix production.

[Differences between the invention and the prior art] Compared to the conventional microcomputers described above, the present invention differs in that address output and input/output of instructions and data are performed serially through one terminal. In the microcomputer, the microcomputer has a data terminal that serially inputs and outputs the data, an address register that stores the address signal, and a data register that stores the signal representing the command and data, and a A serial/parallel conversion register is interposed between the data terminal and the data register.

[Operation of the Invention] The microcomputer according to the above configuration receives address signals and data signals serially supplied from the outside at its terminals, and then converts these data from serial to parallel for use. Therefore, the number of terminals can be reduced compared to the case where data is received in parallel, and since instructions and the like can be held in an external memory instead of in the built-in ROM, it is possible to easily change the instructions and the like.

[Means for solving problems]
[Embodiment] The gist of the present invention is to output address signals in series. FIG. 1 is a block diagram of an embodiment of the present invention.

For convenience, address signals are input and output via one output terminal 1, data signals are input and output via one human output terminal 2, and read/write signals are input and output via one output terminal 3. When the data signal is in the human power direction, a high level is output, and when the data signal is in the output direction, a low level is output. program counter 4
stores the 7 addresses of the next program instruction to be accessed, and is composed of an 8-bit counter. The shift register 5 is a conversion register for converting the value of the program counter 4 from parallel to serial, and is similarly composed of an 8-bit shift register. The shift register 6 is an 8-bit shift register used to convert a serial data signal input from the input/output terminal 2 into parallel data, and further converts the data signal to be outputted from parallel to serial. The instruction register is an 8-bit register for temporarily storing program instructions input from the outside, and the instruction decoder 8
is a circuit that decodes program instructions.

A control circuit 9 outputs various control signals 1 according to program instructions.
Forms 0 rows. The clock oscillation circuit 1l generates a timing signal 12 necessary for the microcomputer to operate normally.

Next, the operation will be explained in detail. FIG. 2 is an example of a timing chart when the program shown in Table 1 is executed.

Table 1 The above program fetches the program instruction JMPIOH (H represents HEXA DATA) stored at address O, and branches to address IOH upon execution. At address 108, the program instruction MOV
A and B are stored, and this instruction means to transfer the contents of the B register to the A register. Currently, O is stored in program counter 4,
The contents are transferred to the shift register 5 by one clock of the timing signal 12. Every clock of the timing signal l2, the shift register 5 outputs an address signal of l bits to the output terminal 1 with the MSB at the beginning.

That is, "OO" is output by eight clock signals. If "00゜' is output, it is the contents of address O'
``54'' is input from the human output terminal as a data signal, one bit at a time, with the MSB at the beginning.8
"54" is stored in the shift register 6 by the clock, and further transferred to the instruction register 7, where the instruction decoder 8 interprets the instruction. As a result, the code "54" is interpreted as a branch instruction with an operand indicating a 1-byte address, and the operand "10" is a branch instruction.
” is input one bit at a time as a data signal from the output terminal 2. When “10” is stored in the shift register 6 by an 8-bit clock, it has already been interpreted that “10” means an address. Therefore, "10" is transferred from shift register 6 to shift register 5.

Furthermore, one bit from the shift register 5 is outputted to the output terminal as an address signal. By 8 clocks”
10" is output, the instruction code at address 10 is "38'.
is manually input one bit at a time as a data signal from the human output terminal 2. The procedure explained above is shown in Figure 2 using MOVA,
The timing chart is shown until B's mechanical command "38" is manually input to the shift register 6. In the embodiment shown in FIG. 1, there is one input/output terminal 2 for data signals, but one input terminal and one output terminal for data signals are separately provided, and one shift register is provided.
By adding more, it is also possible to perform manual labor and output at the same time. Arithmetic operations can be performed by separating the input and output terminals.

[Effects of the Invention] As explained above, the present invention has the effect of reducing the number of terminals by serially outputting addresses and inputting/outputting instructions or data, and easily realizes a small and low-cost microcomputer. can do. Moreover, unlike l-chip microcomputers, the system manually inputs instructions from outside, so it is possible to dynamically change programs, making it suitable for microcomputers for systems with a wide variety of products produced in small quantities. Especially when remote control is performed in a centralized control system and many sub CPUs are connected at the end, the distance from the host CPU to the sub CPU is often long, and the number of wires between the host CPU and the sub CPU can be reduced. This has the effect of reducing total costs.

Furthermore, since the sub-CPU program is placed on the host CPU side, the program can be changed on the host CPU side depending on the situation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcomputer showing an embodiment of the present invention, and FIG. 2 is an operation timing diagram of the microcomputer shown in FIG. １・・・・・・・・・
・Address signal, 2 ・ ● ◆ ・ ・ ・ ・
・ ・３ ● ・ ・ ・ ・ ・ ● ・ ◆４ ●
● ● ・ ・ ・ ・ ● ・5、6・ ● ・
・ ・ ・ ・ 7・ ・ ・ ・ ・ ・ ・ ・ ・8 ● ◆ ●
● ● ● ◆ ● ・9・ ・ ・ ・ ・ ・
・ ・ ・10 ● ◆ ・ ・ ● ・ ・ ・1
l ・ ● ・ ・ ・ ・ ・ ・12 ・ ● ・
・ ・ ・ ・ ・Data signal, ・Read/write signal, ・Program counter, ・Shift register, ・Instruction register, ・Instruction decoder, ・Control circuit, ・Control signal, ・Clock oscillation circuit, ・Timing signal.

Claims (1)

[Claims] An address terminal that outputs address signals in series, a data terminal that serially inputs and outputs signals representing commands and data, an address register that stores the address signals, and signals representing the commands and data. 1. A microcomputer comprising: a data register for storing a serial-to-parallel conversion register; and a serial-to-parallel conversion register interposed between the address terminal and the address register and between the data terminal and the data register.