JPH0329190A - Clock signal input circuit - Google Patents

Abstract

PURPOSE:To allow one memory circuit to satisfy requests to two kinds of memory circuits by providing a clock signal input circuit with a circuit for setting up the potential of an output signal in accordance with the potential of an external clock signal at the time of turning on a power supply and switching the control function of a clock signal in accordance with the potential of the external clock signal at the time of turning on the power supply. CONSTITUTION:The clock signal input circuit is provided with an output signal potential setting circuit 100 inputting an external clock signal I1 and capable of setting up an output signal P to a high level or a low level in accordance with the potential of the external clock signal I1 at the time of turning on the power supply and a clock signal input buffer circuit 200. In accordance with the setting condition, i.e. the potential of the clock signal I1 up to the initial writing operation after turning on the power supply, of an output signal P from the circuit 100, circuit connection is automatically switched to change the control function of the clock signal I1 and the control functions of clock signals I1, I2 are simply switched in accordance with purposes. Consequently, market requests to two kinds of memory circuits can be satisfied only by one memory circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clock signal buffer circuit, and in particular,
The present invention relates to a clock signal buffer circuit that detects the potential of an external clock signal when power is turned on and switches a clock signal control function based on the detection result.

[Conventional technology] In recent years, market demands for memory have tended to become more diverse. Taking the clock signal that controls memory as an example,
There is a demand for a memory provided with a chip selection function and an output terminal control function, and a memory provided with a chip selection function of both positive and negative logic. A family of products with the same basic internal circuitry and only a different clock signal function can be created by simply changing some of the circuit connections within the clock signal driver 7 circuit.

Below, as a conventional example, a two-input clock signal buffer circuit is connected to a case having a negative logic chip selection function and a negative logic output terminal control function, and a case having a negative logic chip selection function and a positive logic chip function. The switching will be explained with reference to FIGS. 3(a), (b), and (c).

In FIG. 3(a), II, I2 are clock signals, A31 is an inverter circuit, N31, N32,
N33, B31, B32, and B33 are switch sections, CS' is an internal chip selection signal, and σ' is an internal output terminal control signal, respectively.

First, a case will be described in which a negative logic chip selection function and a negative logic output terminal control function are provided.

In this case, the switch part B31 in FIG. 3(a) is replaced by the switch part B31 in FIG.
) is the connection shown in switch section B32.

In the switch section B32, the node N31 is connected to the power supply VCC, so the node N33 is always at a low level, and the internal chip selection signal 3' becomes the in-phase signal of the clock signal I2. On the other hand, since the node N32 is connected to the clock signal It, the internal output terminal control signal στ' becomes a signal in phase with 1 when the chip is selected, that is, when rS' is at a low level. Therefore, the clock signal I2 has a negative logic chip selection function, and the clock signal 11 has a negative logic output terminal control function.

Next, we will explain the case where a negative logic chip selection signal and a positive logic chip selection function are provided. In this case, as shown in FIG.
The switch part B31 in a) is the switch part B in FIG. 3(c).
The connection is shown in 33. Clock signal 11 is at node N
Since it is connected to 31, 31' becomes a selected state of low level only when Il is high level and I2 is low level. Therefore, the clock signal It has a chip selection function of positive logic (2) and negative logic. On the other hand, node 32
Since is connected to the ground (GND) power supply, the internal output terminal control signal {circle around (2)} becomes a signal in phase with the internal chip selection signal r}''. Therefore, it is always kept at a low level in the selected state so as not to affect the operation of the memory circuit.

As is clear from the above explanation, in the conventional example, FIG.
) switch section B31 of the clock signal buffer circuit
Switch part B32 in Fig. 3(b) or Fig. 3(b)
By setting one of the connections shown in the switch section B33, two types of memory circuits with different clock signal control functions are realized. In the manufacturing process, the above-mentioned switching of circuit connections was performed using polysilicon or aluminum wiring, and a method was used to create and manufacture two types of masks for each connection during the diffusion process.

[Problems to be Solved by the Invention] In the conventional example described above, two types of masks corresponding to two types of functions are required, which may cause confusion in the diffusion process and reduce the production volume of two types of memory circuits at the time of diffusion. This had the disadvantage of requiring constant management from the beginning, and furthermore, it was necessary to estimate the diffusion technology for each of the two types of memory circuits during prototype evaluation at the hole-opening stage, which required a long development period. .

[Differences between the invention and the prior art] Compared to the conventional clock signal buffer circuit described above,
The present invention is different in that it includes a circuit that sets the potential of an output signal based on the potential of an external clock signal when the power is turned on, and that the control function of the clock signal is switched depending on the potential of the external clock signal when the power is turned on.

[Means for Solving the Problems] The gist of the present invention is to provide a clock signal input circuit which inputs first and second external clock signals and outputs an internal chip selection signal and an internal output terminal control signal, An output signal potential setting circuit is provided which receives the first external clock signal and can set an output signal to a high level or a low level depending on the potential of the first external clock signal when the power is turned on, The NOR logic output of the signal and the output signal of the output signal potential setting circuit is ORed with the second external clock signal, the output thereof is used as an internal chip selection signal, and the output is used as an internal chip selection signal, and the output signal is used as an internal chip selection signal. a clock signal buffer circuit which takes a NOR logic output of the signal and a reverse phase signal of the output signal of the output signal potential setting circuit and uses the output as the internal output terminal control signal; The external clock signal has a negative logic chip selection function, and the function of the first external clock signal changes depending on the setting condition of the output signal of the output signal potential setting circuit, and when the output signal is at a high level, the function is negative. When the logic output terminal control function is at a low level, it has a positive logic chip selection function.

[Operation of the invention] In the clock signal input circuit according to the above configuration, the output signal potential setting circuit supplies the clock signal input buffer circuit with an output signal corresponding to the potential of the first external clock signal when the power is turned on. The input buffer circuit can selectively implement a negative logic output terminal control function and a positive logic chip selection function based on this output signal.

[Embodiment] Next, a first embodiment of the present invention will be described with reference to FIG.

In FIG. 1, W is a write control signal, which is at a high level during a write operation and at a low level during a read operation. P is the output signal of the output signal potential setting circuit, Nil,
Nl2, N13, N14, N15 are nodes, All, AI2, A13, A14 are inverter circuits, Q11, Q12 are N-channel MO
Q13 represents a P-channel MOS} transistor, and Q13 represents a P-channel MOS} transistor.

First, the output signal potential setting circuit 100 will be explained. In the read operation mode, the write control signal W is set to a low level and the power is turned on. Since the write control signal W is at a low level, the MOS transistor Qll is off,
The node Nil is at a low level, and the node N12 is at a high level.

Therefore, the transistors Q12 and Q13 are both turned on, and the level of the node N13 becomes equal to the level of the clock signal 1, so that the output signal P becomes a signal with the opposite phase of the clock signal It through the flip-flops A13 and A14. When the write control signal W becomes high level in the first write operation after the power is turned on, the MOS} transistor Qll turns on,
Since the node Nti is at a high level and the node N12 is at a low level, both the MOS transistors Q12 and Q13 are turned off, and there is no conduction between the clock signal If and the node N13.

Since the inverters All and AI2 constitute a flipflop, the node Nil remains at high level and the node N12 remains at low level regardless of the level of the write control signal W, and the transistors Q12, Q13
are both turned off, and a non-conducting state remains between the clock signal II and the node Nl3.

Therefore, by the flip-flops of inverters A13 and A14, the node Nl3 maintains the level of the clock signal It before the write operation, and P remains its phase signal.

Therefore, when the power is turned on with the clock signal It set to a low level, the output signal P is set to a high level, and when the power is turned on with the clock signal II set to a high level, the output signal P is set to a low level.

Next, a description will be given of a clock signal buffer circuit 200 that is capable of switching the clock signal control function according to the setting conditions of the output signal P of the output signal potential setting circuit.

When the output signal P is high level, that is, the clock signal I
When the power is turned on with I set to low level, node N1
4 is always at a low level regardless of the clock signal I1, and the internal chip selection signal C}' becomes an in-phase signal of the clock signal I2. On the other hand, since the node Nl5 is in the opposite phase of the output signal P and is always at a low level, the internal output end control signal
It becomes an in-phase signal of f.

Therefore, the clock signal 12 has a negative logic chip selection function, and the clock signal 1 has a negative logic output terminal control function.

On the other hand, when the output signal P is at a low level, that is, when the power is turned on with the clock signal I1 at a high level, the node Nl4 has the opposite phase of the clock signal I1, so the internal chip selection signal C1' is set to the clock signal I1. Signal II is high level,
Moreover, only when the clock signal I2 is at a low level, it becomes a selected state at a low level.

Therefore, the clock signal I2 has a negative logic chip selection function, and the clock signal I1 has a positive logic chip selection function.

On the other hand, since the node Nl5 is always at a high level, the internal output terminal control signal 'in' is kept at a low level, which is the output terminal active state, and is set so as not to affect the memory circuit operation.

As described above, the present invention automatically switches the circuit connection depending on the setting conditions of the output signal P of the output signal potential setting circuit, that is, the potential of the clock signal from the time the power is turned on until the first write operation, and The control function can be changed, and the clock signal control function can be easily switched depending on the intended use.

FIG. 2 shows an output signal potential setting circuit 300 according to a second embodiment of the present invention. In FIG. 2, W is a write control signal, It is a clock signal, P is an output signal of the output signal potential setting circuit, N21 to N27 are nodes, A21 to A25 are inverter circuits, F21. F22 indicates an electrical fuse. Fuses F21 and F22 are blown by the large current. Q24 and Q25 are N with large current capability.
Channel MOS} transistors R21-R23 have high resistance. Q21 and Q22 are N-channel MOS}
The transistor Q23 is a P channel MOS transistor. The clock signal buffer circuit is the same as that shown in FIG.

The power is turned on in the read operation mode, that is, with the write control signal W set at a low level. MOS} transistor Q2
1 is off, so node N22 is high level, node N23
becomes a low level, and the NOR logic output node N24
becomes a low level, and the MOS transistor Q24 turns off. Therefore, the node N25 becomes a high level and the node N26 becomes a low level, both MOS transistors Q22 and Q23 turn on, and the level of the clock signal 1 becomes the node N27.
It is transmitted to When clock signal 11 is low level, MO
S} Since the transistor Q25 is off, the output signal potential setting circuit output signal P becomes high level. On the other hand, when the clock signal II is at a high level, the MOS} transistor Q25
is turned on and a large current flows, causing electrical fuse F2
2 is fused, and the output signal P becomes low level.

The write control signal W is generated at the first write operation after power is turned on.
goes from low level to high level, MOS transistor Q21 turns on, node N22 transitions from high level to low level, and node N23 changes from low level to high level after a certain period of delay determined by the transistor size of inverter array A23 to A25. Transition to level.

Therefore, the NOR logic output node N24 of nodes N22 and N23 is an upward one-shot pulse that is at a high level only during the period from when node N22 transitions from a high level to a low level until when node N23 transitions from a low level to a high level. Become.

While the node N24 is at a high level, the MOS transistor Q24 is turned on and a large current flows, causing the electric fuse F21 to open.
is melted. Node 24 becomes low level, N26 becomes high level, MOS} transistors Q22 and Q23 are turned off,
There is no conduction between the clock signal If and the node N27. Since inverters A21 and A22 constitute a flip-flop, node N24 is kept at a low level regardless of write control signal W, as in the first embodiment, and Q24
remains in the off state, and the electrical fuse F21 is cut, so the high resistance R21 keeps the node N25 at a low level and N26 at a high level, and the clock signal If and the node N27 remain in a non-conducting state. Become.

On the other hand, since the node N27 is at a low level due to the high resistance R22, the MOS transistor Q25 is turned off, and if the electric fuse F22 is not cut, that is,
When the power is turned on with the clock signal Il at a low level, the output signal P goes to a high level, and when the electrical fuse F22 is cut, that is, when the power is turned on with the clock signal 1 at a high level, the output signal P goes to a high level. P is high resistance R
23, it remains at a low level. It is clear that the control function of the external clock signal can be switched depending on the setting level of the output signal P of the output signal potential setting circuit 300, as in the first embodiment.

Furthermore, in this embodiment, the potential of the output signal P is set when the power is turned on for the first time for the wafer state or silk-finished product after completion of diffusion, the control function of the external clock signal is determined, and the power is then turned off. Even if the power is turned on again, the initially set external clock signal control function is maintained regardless of the level of the clock signal when the power is turned on again. This has the advantage that there is no need to set the signal level using an external circuit or the like.

[Effects of the invention] As explained above, the present invention has the first advantage compared to the conventional example.
Since there is no need to take any means to switch the circuit configuration within the diffusion process, all the diffusion processes can be consistently manufactured using one type of mask, which has the effect of simplifying the diffusion process. Second
This has the effect that it is possible to switch to a memory circuit having a clock signal with a different control function simply by changing the level setting of the clock signal when the power is turned on. For example, the circuit of the first embodiment can be switched each time according to the application, so one memory circuit can satisfy the market demand for two types of memory circuits, and the second embodiment can satisfy market demands for two types of memory circuits.
The circuit of the embodiment has the advantage that the clock signal control function can be switched during product testing and two types of memory circuits can be manufactured, allowing the production amount to be freely adjusted in accordance with market requirements. Thirdly, even at the time of memory circuit development, two types of memory circuits can be evaluated immediately by simply changing the level setting of the clock signal when the power is turned on, thereby reducing the number of development days.

The present invention can change the clock signal control function with a simple circuit configuration and has the above-mentioned effects, so it is extremely useful in actual use. It goes without saying that the present invention is not limited to the above embodiments, but can be applied to various ranges that satisfy the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a clock signal input circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing an output signal potential setting circuit according to a second embodiment, and FIGS. 3(a) to (c) is a circuit diagram showing a conventional example. 11.12...Clock signal, rS゛...Internal chip selection signal, mason 1' ・
...Internal output terminal control signal, W...Write control signal, P...Output signal of output signal potential setting circuit, B3
1-B33...Switch section, 100,3
00... Output signal potential setting circuit, 200...
・Clock signal input huffer circuit. AIl~A 14. A21-A25', A31... Inverter circuit, Q24, Q25... Large current capacity N-channel MOSFET, F21. F22・・・・Electrical fuse, R2
1~R23...High resistance,

Claims (1)

[Claims] In a clock signal input circuit which receives first and second external clock signals and outputs an internal chip selection signal and an internal output terminal control signal, the clock signal input circuit receives the first external clock signal and outputs an internal chip selection signal and an internal output terminal control signal. An output signal potential setting circuit capable of setting an output signal to a high level or a low level depending on the potential of an external clock signal is provided, and a NOR logic output between the first external clock signal and the output signal of the output signal potential setting circuit is provided. OR logic is performed with the second external clock signal, and its output is used as an internal chip selection signal, and the OR logic output of the first external clock signal and the internal chip selection signal is used as the output signal of the output signal potential setting circuit. a clock signal input buffer circuit that takes a negative phase signal and a NOR logic and uses the output as the internal output terminal control signal; the second external clock signal has a negative logic chip selection function; The function of the external clock signal changes depending on the setting conditions of the output signal of the output signal potential setting circuit, and when the output signal is high level, it is a negative logic output terminal control function, and when it is low level, it is a positive logic chip selection function. 1. A clock signal input circuit characterized by having a function.