JPH03292723A - Manufacture of silicon singe crystal thin film - Google Patents

Abstract

PURPOSE:To manufacture a silicon single crystal film with the regions surface- oriented in the same direction by a method wherein an opening and a projection are simultaneously formed in the insulating material layer on a silicon substrate so as to selective epitaxially grow a silicon single crystal on the insulating material layer and then the silicon single crystal on the opening is selectively oxidized to insulate and isolate the silicon substrate from the silicon single crystal. CONSTITUTION:An oxide film 12 as an insulating layer is formed on a silicon wafer 11 and then oxide films 13 are formed. Next, a crystal 15 is grown by SEG process and simultaneously an ELO crystal 15' to be a silicon single crystal is grown by ELO process. Successively, an Si3N4 film 17 for mask is deposited on a silicon single crystal thin film 16 by LPCVD process to be etched away for thermal oxidization. Through these procedures, the part only to be the seed crystal for the silicon single crystal growth is selectively oxidized to form an insulating part 18 so that the silicon single crystal thin film 16 and the silicon wafer 11 may be electrically insulated and isolated perfectly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a silicon single crystal thin film (SOI) on an insulating film used in a semiconductor device.

[Conventional technology] Conventionally, silicon single crystal thin films, which are essential for semiconductor devices, have been fabricated by epitaxial growth from a single crystal substrate. Growing crystals is extremely difficult.

On the other hand, in recent years, semiconductor devices have been stacked to form two layers.
There is a demand for the realization of three-dimensional integrated circuits and high-speed, high-performance devices in order to achieve higher integration and multifunctionality, and research and development in this area is actively conducted. The technology for forming the so-called S○■ structure has become important.

There are quite a variety of methods known for forming silicon thin films on insulating substrates, even if the silicon layer is not amorphous but crystalline such as polycrystalline. There are also many different types.

For example, CV
D. When depositing polycrystalline silicon by sputtering, etc.,
Depending on the substrate temperature, gas type, pressure, etc. during deposition, a silicon $ crystal thin film with an average grain size of several tens to several thousands of grains and whose orientation is not controlled is obtained.

Furthermore, the polycrystalline thin film or amorphous film is melted and solidified using thermal energy such as a laser or a rod-shaped heater.
A method for obtaining a polycrystalline thin film with a large grain size of about m or mm has also been reported (Single Crystal 5il
icon on Non-single-Non-5i
n In5u-1ators, Journal of
Crystal Growth vol, 63. N.

3, 0ctober, 1983 edited by
&, W, Culler+).

Transistor elements were made using the thin films of each crystal structure formed as described above, and the electron mobility was measured based on its characteristics. When compared with that of single-crystal silicon, it was found that grains of several μm to several mm were formed by melting and solidification. For polycrystalline silicon with a grain size distribution of several hundred to several thousand, it is about 10-3, and For amorphous silicon, it is only about 2×10−' compared to single crystal silicon.

This result shows that there is a large difference in electrical characteristics between an element made in a single crystal region within a crystal grain and an element made across a grain boundary.

In other words, the deposited film on an amorphous surface obtained by conventional methods becomes an amorphous or polycrystalline structure with a grain size distribution.
Devices fabricated using the deposited film have significantly inferior performance compared to devices fabricated using a single crystal layer. Therefore, semiconductor devices formed using such deposited films are limited to simple switching devices, solar cells, photoelectric conversion devices, and the like.

Therefore, in order to produce a high-performance semiconductor device, a semiconductor single-crystal thin film with grain boundaries removed or with controlled grain boundary positions is required.

As an example of a method for forming a 5ilL crystalline thin film on an amorphous product with grain boundaries removed, SOS (Silicon on 5ap)
fire) Y left, S I M OX (
5eparation by implantat
ion○f Oxygen) method, bonding method, oxidation separation method (USP 4.361.600j, etc.), and as a method for forming semiconductor thin films with controlled grain boundary positions, for example, JP-A-63-107016 There is something like the one disclosed in the issue.

The SO5 method uses sapphire (single crystal Al2O) as the substrate.
2), and silicon is grown heteroepitaxially on its surface.

The SIMOX method involves implanting 04 (oxygen ions) into a silicon wafer at high energy and annealing it, thereby injecting 5i into the wafer while maintaining the single crystal structure of Si on the surface.
This is a technique for forming an intermediate layer of Oz.

The above-mentioned bonding method involves bonding and annealing two silicon wafers whose surfaces are oxidized, or more specifically, a combination of one silicon wafer with oxidation and one silicon wafer that is not oxidized. By doing so, the crystalline silicon is adhered to the atomic level, and the polishing is stopped when the silicon thin film remains as a thin film.
This is a method of forming i@.

The oxidation separation method forms irregularities on the surface of a silicon wafer,
The entire surface is oxidized after masking the top and side surfaces of the convex portion. As a result, oxidation proceeds from the unmasked portion, and the entire convex portion is insulated and isolated from the substrate side by 3102.

The method described in Japanese Patent Application Laid-Open No. 63-107016 is not limited to the above-mentioned substrates, but is intended to obtain a semiconductor single-crystal thin film with controlled grain boundary positions. This method uses two types of amorphous materials with different nucleation densities to form semiconductor single crystal nuclei at desired locations, performs selective growth, and causes the grown crystals to collide with each other at desired locations. It forms grain boundaries.

[Problems to be Solved by the Invention] However, the SO5 method has the problems that the sapphire substrate is extremely expensive and that An, which is a component of the substrate, diffuses into the silicon film. .

In the case of the SIMOX method, since oxygen ions are implanted with extremely high energy and high concentration, the throughput is poor, and high temperature annealing is required, which causes stress on the substrate.

In addition, the above bonding method requires polishing most of one wafer, which increases the cost. Also, the bonding method requires polishing silicon wafers that inherently have uneven thickness, and the position of the only remaining silicon layer is high. The problem is that polishing has to be stopped at a certain point, making it extremely difficult to control.

Although the oxidation separation method can provide an SOI structure, the silicon layer is not separated into a thin film but into a bulk (mass). Even if this is polished, a Si single crystal thin film cannot be obtained because the interface between SiO2 and Si is not flat.

In the method described in JP-A-63-107016, grain boundaries are formed, which means that at least the in-plane orientations of each crystal grain cannot be aligned.

As described above, each of the above-mentioned conventional techniques has a different background, but each has several problems.

In order to solve the above-mentioned problems of the prior art, the present invention uses a relatively inexpensive silicon wafer, uses general equipment and a general process, and completely insulates and isolates any area in the plane. It is an object of the present invention to provide a silicon single crystal film formed in most of the upper regions and in which the plane orientations of the isolated regions are aligned, and a method for manufacturing the same.

[Means for Solving the Problems] In order to achieve the above object, the invention of claim 1 provides a first step of forming an insulating layer on a silicon substrate, and forming an opening in the insulating layer. a second step of forming a convex portion that can serve as a stopper for selective polishing; a third step of selectively epitaxially growing a silicon single crystal on the insulating layer from the opening; a fourth step of polishing the silicon single crystal to the convex region; and a fifth step of selectively oxidizing the silicon single crystal above the opening and insulating and separating the silicon wafer and the silicon single crystal. The invention according to claim 2 is characterized in that, in the method for manufacturing a silicon single crystal thin film according to claim 1, the region of silicon to be oxidized by selective oxidation is set to be wider than the opening. The invention according to claim 3 is characterized in that in the method for manufacturing a silicon single crystal thin film according to claim 1, the insulating layer and the convex portion that can serve as the stopper are formed of different materials.

According to a fourth aspect of the present invention, in the method for manufacturing a silicon single crystal thin film according to the first aspect, the insulating layer and the convex portion that can serve as the stopper are formed of the same material.

According to a fifth aspect of the invention, in the method for manufacturing a silicon single crystal thin film according to the first aspect, the opening has a diameter of 1 μm or more and 4 μm or less.

[Function] (1) In the il step, an insulating layer is formed on the silicon wafer.

Considering the currently used silicon semiconductor process, the insulator layer may be, for example, S10, Si3N
Is there a 4th grade, and the method of formation is CVD? There is no problem whether the silicon wafer is removed or removed by sputtering, and in the case of S102, it may be formed by oxidizing the silicon wafer.

(II) In the second step, first, an electrical insulator is deposited on the insulating layer to function as a stopper to finish the polishing in selective polishing with the silicon crystal, and a convex portion serving as a stopper is formed. Pattern as much as possible. The material of the electrical insulator may be any material as long as it can fulfill the above function, such as 5i02, Si3
N, etc., but the same material as the insulator layer formed on the silicon wafer may be used. The thickness of the electrical insulator corresponds to the thickness of the silicon single crystal thin film to be manufactured, and is determined depending on the use of the semiconductor device to be manufactured later.

Next, the insulating layer on the silicon wafer is etched to form an opening and expose the surface of the silicon wafer. This step can be easily carried out by ordinary photolithography, and the etching can be performed by either RIE or wet etching.

The size of the opening is preferably 1 μm or more in diameter. If it is less than 1 μm, crystal defects are likely to be formed during subsequent selective growth, which may cause deterioration of the electrical characteristics of the manufactured device or the crystal may not grow from the opening.

If the thickness is 1 μm or more, sufficient selectivity can be achieved during silicon crystal growth, and the growing crystal will grow as a single crystal with uniform plane orientation (that is, the same plane orientation as the substrate). Even if the opening is large, there will be no problem in terms of selectivity and crystallinity during growth, but it is a part that will later be selectively oxidized and become an oxide film, and it occupies within the silicon wafer of a silicon single crystal thin film. In order to reduce the ratio and make the material unfavorable for high integration, the opening 14 should be smaller, from 1 μm to 4 μm.
The desired size is desirable.

However, due to the device design, there is a scribe line.

There is no problem even if a silicon single crystal is grown using a device insulation isolation region or the like as an opening, and the shape of the opening is arbitrary.

The stopper and the opening may be formed in any order, and contrary to the above, no problem will arise if the stopper is formed after the opening is formed.

(III) Step i3 includes selective epitaxial growth of a silicon single crystal from the opening exposing the surface of the silicon wafer.
xial growth (hereinafter referred to as SEG).

What is important here is that conditions are set so that crystal growth does not occur on the insulating layer and single crystal epitaxial growth occurs only from the opening.

The conditions for crystal growth are as follows: First, the gas system is H2 as a carrier gas, and the Si source gas as Si CIL4゜5iHC.
Chlorosilane type or S such as J13,5iH2CfL2
A silane system such as iH4, 5i2Ha is used, and an HCfL gas having an etching effect is used as an additive gas.

Although the optimum temperature range varies greatly depending on the gas used, it is usually set in the range of 800 to 1200°C.

The pressure is preferably set within the range of several Torr to 250 Torr, more preferably 80 to 170 Torr.
range. This is because when the pressure is low, the selectivity is good, but the growth rate is slow, and when the pressure is high, the selectivity is bad. Note that the optimum pressure varies depending on the type of gas used and the temperature.

If the selective growth is further continued, the silicon crystal that has grown upward from the opening will also overgrow on the insulating layer.
rowth begins to grow. This lateral growth is particularly important for E L
O(Epitaxial Lateral Over
growth). This ELO crystal is grown until it reaches the convex portion which is the stopper.

(rV) In the fourth step, silicon selective polishing is performed from above the grown silicon wafer, and the polishing is completed on the surface of the convex portion. As a result, a silicon single crystal thin film can be obtained.

There are two types of selective polishing methods.

One is mechanical chemical polishing method (mechanochemical etching),
One is a mechanical polishing method (mechanical etching).

The former is a selective polishing method that takes advantage of the fact that when the insulating layer is made to have a density of 5iOz, a special chemical polishing liquid is mixed in and the polishing speeds of St and 5i02 are significantly different (Performance, Continuous Layering, Journal of the Japan Society of Applied Physics; Volume 56, No. 11, page 1480, etc.).

Specifically, the above method includes, for example, ethylene diamine,
This is done by polishing with a boring cloth using an alkaline solution called pyrocatechol. The above chemical polishing liquid dissolves Si as 5i(OH), but 5iOz
Since the polishing does not react with the polishing, the polishing can be completed when the S i 02 surface is exposed.

On the other hand, when the mask is made of a material such as Si3N4 whose Mohs hardness is sufficiently higher than that of Si, a mechanical polishing method can be used (Japanese Patent Application No. 63-247819). This mechanical polishing method has a hardness equal to or higher than that of Si, and S
Colloidal silica, an abrasive grain with lower hardness than i3N4
is used as an abrasive for mechanical polishing.

Since the colloidal silica has a low hardness (it cannot polish Si, N, etc.), polishing is terminated when the Si3N4 surface is exposed.

Note that any insulator that is harder than colloidal silica and that can be selectively grown can be used as a mask for mechanical polishing in the process of the present invention.

(V) In the fifth step, for example, selective oxidation method (Lacos
) selectively oxidizes the opening, which is the seed crystal for growing the silicon single crystal, and completely electrically isolates the silicon wafer from the grown silicon single crystal.

The thickness of the silicon layer thermally oxidized in this step is approximately the sum of the thickness of the insulator layer formed on the silicon wafer and the thickness of the electrical insulator as a stopper, and is approximately several thousand at most. Even if the silicon thermal oxide film grows about 55% upward and about 45% downward, it is sufficient to oxidize the silicon to a total depth of about 1 μm.

On the other hand, if the selective oxidation region is made larger than the opening at the expense of higher integration, silicon formed by ELO!
[By oxidizing the film layer, it becomes possible to isolate it from the substrate.

[Examples] Examples of the present invention will now be described in more detail with reference to FIGS. 1(a) to (h).

(First Example) In this example, the silicon wafer has a surface orientation of (10
0), is n-type, has a resistivity of 1 to 2 Ω・Cm, and a diameter of 4
An inch one was used. As shown in Figure 1(a),
In order to form an oxide film layer 12 as an insulator layer on the silicon wafer 11, the silicon wafer 11 is heated to H2: 02=3I.
It was placed in an atmosphere of l/min: 2JZ/min and thermally oxidized at a temperature of 1000° C. for 90 minutes. As a result of the thermal oxidation, the oxide film layer 12 was formed to have a thickness of about 0.3 μm.

Next, on the oxide film layer 12, a film 13 of Si and N, which is an electrical insulator, was deposited to a thickness of 0.degree. 15 .mu.m by the LPCVD method. The deposition conditions in this case are 5iH2cJ22:NH
3=20sec+80sccm, 0.3Torr, 8
Deposition was carried out at 00°C for 45 minutes.

Thereafter, in order to form a pattern as shown in FIG. 3 (see FIG. 1(b) for a cross-sectional view), the photolithography technique used in a normal semiconductor process is used to form a pattern such as the one shown in FIG.
i3N4@13 was etched. RIE was used for etching the Si3N4@. In this case, the line width of the convex portion 32 of Si3N4@13 serving as the stopper was 10 μm, and the area surrounded by the convex portion 32 was a square with one side of 50 μm.

Further, as shown in FIG. 1C, buttering is performed to form an opening 14 (33 in FIG. 3) in the oxide film 12, and dilute HF is applied until the surface of the silicon wafer 11 is exposed. A portion of the oxide film layer 12 was etched using a solution. The opening 14 formed in this way has one side of 2
It is a square pattern of .mu.m, located approximately at the center of the square line frame made of the 313 N.sub.m film 13, and the exposed portion exposed through the opening serves as a seed crystal for silicon crystal growth.

Next, as shown in FIG. 1(d), SEG is performed to obtain a grown crystal 15, and as shown in FIG. 1(e), E
LO was performed to obtain an ELO crystal of approximately 60 μm×60 μm, which is a silicon single crystal, of 15°. The growth conditions in this case are as follows.

5iH2Cu2・HCfl: H2 = 0.53j2 /min: L, S fl /m
The temperature was 990° C., the pressure was 100 Torr, and the growth time was 70 minutes.

Subsequently, as shown in FIG. 1(f), the grown EL
Selective polishing was performed on the O crystal at 15° using the mechanical polishing described above. Specifically, using a processing fluid containing colloidal silica of SiO2 (average particle size 0.1 μm),
Using a commonly used silicon wafer surface polishing device, the pressure was 3.6 kg/cm2. Polishing was performed at a temperature of 30°C to 40°C. In this way, a silicon single crystal layer @16 having a thickness of 0.15 μm and length and width of 50 μm was obtained.

Thereafter, as shown in FIG. 1(g), a Si3N4 film 17 for a mask is deposited to a thickness of 0.15 μm on the silicon single crystal thin film 16 by the LPCVD method described above.
Etching, H2O2 = 3 fl /min
: 1000℃ in an atmosphere of 2 j2 /min, 8
Thermal oxidation was performed for an hour. As a result, as shown in FIG. 1(h), only the portion that was a seed crystal for silicon single crystal growth is selectively oxidized by about 1 μm to form an insulating portion 18, and the silicon single crystal layer film 16 is selectively oxidized by about 1 μm. and silicon wafer 11
Completely electrically isolated from the

FIG. 2(a) shows LOG in a wider area than the opening 24.
Set the O3 area, and set the S i3 area for the patterning.
This is a diagram after buttering N4@25, and Figure 2 (
b) is the silicon single crystal layer @23 obtained by the ELO
3 is a cross-sectional view after selective oxidation is performed to a lower position of approximately the thickness of , and insulation isolation from a silicon wafer 22 is performed.

In this way, if the LOGO3 area is set larger than the opening, high integration will be sacrificed to some extent, but
Insulating isolation from the silicon wafer can be achieved by simply oxidizing the thickness of the silicon single crystal layer formed by ELO.

(Second Example) In this example, (111), (
It had an offset angle of 4° in the 211) direction, was n-type, had a resistivity of 2 to 3 Ω·Cm, and had a diameter of 4 inches.

As shown in FIG. 4(a), the silicon wafer 41 is
02 = 3 l/min: Placed in an atmosphere of 2 fl/min, thermal oxidation was performed at 1000°C for 150 minutes,
An oxide film layer 42 having a thickness of about 0.5 μm was formed as an insulating layer.

Next, as shown in FIG. 4(b), a photolithography process was performed twice to form a protrusion around the oxide film layer 42 on the silicon wafer 41 and an opening 43 in the center thereof. . Next, the etching is rare HF7g? (t
Wet etching was performed using

In this case, as shown in FIG.
A device fabrication area of m x 50 μm is provided, and a recess with a width of 5 μm in the center, that is, an opening for exposing the surface of the silicon wafer 11! The portion 52 was created in a line shape.

Subsequently, as shown in FIG. 4(C), SEG and ELO were performed on the surface of the silicon wafer to obtain a silicon single crystal 44. The growth conditions in this case were as follows.

S i H2Cl12: HC flood H2 = 0.50ffi/min: 2.6 Il/m
in: 1001/a+in atmosphere, temperature 103
The temperature was 0°C, the pressure was 100 Torr, and the growth time was 100 minutes.

Figure 4(d)! , :Grown silicon as shown! The crystal 44 was selectively polished in the same manner as the mechanical polishing shown in the first embodiment, to obtain a silicon single crystal thin film 45 with a thickness of about 01 μm.

Furthermore, as shown in FIG. 4(e), the silicon single crystal 4 above the linear opening 43 is
5 was selectively oxidized to form an insulating portion 46.

In this case, the LOGOS area is set to be larger than the line width, which is 10 μm, but as described in the explanation of the first embodiment, the insulating portion 4
Even though the film thickness of No. 6 was 0.3 μm, it was completely insulated and separated from the underlying silicon wafer 41.

The mask for LOGOS was formed using a Si3N4 film as in the first embodiment, and the deposition conditions and etching conditions for the Si3N film were also the same as those described above.

Also in LOGOS. The oxidation conditions were H2: 02
= 3 + 2 fL/min atmosphere, 10
00°C for 80 minutes.

[Effects of the Invention] As described above, according to the invention of claim 1, a silicon single crystal thin film having a sufficiently large area and with perfectly aligned orientations is electrically completely different from a silicon wafer. It becomes possible to form them in a separate state.

Moreover, according to the invention of claim 1, SoS and SIMOX
This method is much cheaper than other methods, such as laser melting recrystallization, in which a single crystal is formed on an insulator to produce an SOI structure, and it is possible to easily obtain an SOI substrate.

The crystallinity of the silicon single crystal thin film is also the same or higher than that of SO3, SIMOX, and laser melting recrystallization methods, and the thickness of the silicon single crystal thin film is within the plane of the silicon wafer.
Since it can be controlled uniformly in the zero range of about 1000, it is possible to form a thin film of less than 1000 Å in the subsequent process.In addition to the advantages of the SOI structure, it also has the advantage of suppressing short channel effects, improving subthreshold characteristics, and high-speed operation. It is also easy to create devices that have the characteristics of the SOI thin film effect.

Furthermore, according to the second aspect of the invention, insulation isolation from the silicon wafer can be achieved simply by oxidizing the silicon single crystal layer formed by ELO.

[Brief explanation of drawings]

1(a) to (h) are process diagrams for explaining the manufacturing method according to the first embodiment of the present invention, and FIG. 2 is a diagram showing another embodiment of selective oxidation. 2(b) is a sectional view showing the formation of an insulator; FIG. 3 is a perspective view showing an example of the pattern of convex portions and openings; 4 is a process diagram illustrating the manufacturing method according to the second embodiment of the present invention; FIG. 5 is a perspective view showing another example of the pattern of convex portions and openings; It is. 7 25...Si, N4 film. (Explanation of symbols) 11.21.41...Silicon wafer, 12.42.
... Oxide film layer, 13...; Gaseous insulator 14.24, 33.43.52... Opening, 32.5
1...Convex part, 18.26.46...Insulating part, 16.23.45...Silicon single crystal thin film, Fig. 2

Claims (5)

[Claims] (1) a first step of forming an insulating layer on a silicon substrate; a second step of forming an opening in the insulating layer and a convex portion that can serve as a stopper for selective polishing; a third step of selectively epitaxially growing a silicon single crystal on the insulating layer from the opening; a fourth step of polishing the grown silicon single crystal to the convex region by selective polishing; A method for producing a silicon single crystal thin film, comprising a fifth step of selectively oxidizing the silicon single crystal on the part and insulating and separating the silicon substrate and the silicon single crystal. (2) The silicon region to be oxidized by the selective oxidation is set to be wider than the opening.
The method for producing a silicon single crystal thin film described in . (3) The method for manufacturing a silicon single crystal thin film according to claim 1, wherein the insulator layer and the convex portion that can serve as the stopper are made of different materials. (4) The method for manufacturing a silicon single crystal thin film according to claim 1, wherein the insulator layer and the convex portion that can serve as the stopper are made of the same material. (5) The method for producing a silicon single crystal thin film according to claim 1, wherein the opening has a diameter of 1 μm or more and 4 μm or less.