JPH0329341A - Layout of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a layout of a small area by a method wherein an arrangement and wiring program assigns an optimum terminal position to a cell and a cell layout is changed so as to meet this assignment in such a way that an interconnection becomes shortest and that the number of crossings becomes minimum. CONSTITUTION:In a layout method of a semiconductor integrated circuit according to a standard cell system using an arrangement and wiring program, a cell layout of cells C1 to C7 inside a cell library 33 is changed so as to be adapted to information given by the arrangement and wiring program. After an arrangement operation and a wiring operation have been executed temporarily, the arrangement and wiring program detects a position where interconnections to the individual cells C1 to C7 are shortest and the number of crossings is minimum; this result is given to the cell library 33; the arrangement operation and the wring operation are executed again. Thereby, the number of contacts for a changeover and the wiring length are reduced; the area of a wiring region can be reduced; a layout of a small area can be obtained.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to an arrangement. This invention relates to a layout method for a semiconductor integrated circuit using a standard cell method using a wiring program.

[Conventional technology]

The current layout technology for semiconductor integrated circuits using the standard cell method involves a cell layout created by hand and the cell name of the cell. It is known that information such as cell frames, terminal names, terminal positions, etc. is registered as a library in an automatic placement and wiring program, and cells are placed and wired manually using a netlist to generate a mask pattern.

FIG. 6 is a diagram showing part of a chip layout according to the prior art. In this figure, C1 to C7 indicate each cell, and 01
~05 is the output terminal, ■1~I5 is the input terminal, 11 is the first
Layer wiring, 12 is the second layer wiring, 13 is the first layer wiring 11
and a contact portion of the second layer wiring 12.

[Problem to be solved by the invention]

In the above conventional technology, each of the cells C1 to C7 is fixed, and each terminal position depends on the cell layout, and depending on the terminal position, the wiring patterns may intersect as shown in FIG. If this continues, both wirings will be connected mechanically and electrically, so for example, one will be used as the first layer wiring 11, and the other will be made the second layer wiring 12 by forming a contact part 13 to make the layer different. There is a problem in that the area of the entire mask pattern increases, such as the need to increase the wiring density in some areas and the wiring density to increase in some areas.

The present invention was made to solve the above problem, and provides a semiconductor integrated circuit layout method that can reduce the wiring length and number of wirings in the wiring area and obtain a semiconductor integrated circuit layout with a small area. The purpose is to

(Means for Solving the Problems) A semiconductor integrated circuit layout method according to the present invention includes:
Cells in the cell library are placed, and the cell layout is transformed and placed according to the information given from the wiring program. Temporary layout of wiring program. After wiring, the position where the wiring to each cell is the shortest and the number of intersections is the least is detected, the results are given to the cell library, and the placement and wiring are performed again.

Then, when adjacent cells are wired, the placement,
According to the conditions given by the wiring program, the cell layout in the cell library is performed so that connections can be made only by cell placement.

[Effect]

In this invention, a placement and wiring program specifies the optimal terminal position for a cell, and changes the cell layout accordingly, so that the wiring is shortest and the number of intersections is minimized.

Further, when cells are adjacent to each other, connection is performed only by arranging the cells without requiring wiring.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a flowchart showing an embodiment of the invention, and FIG. 2 shows a layout according to the invention. Figure 3(a)
shows an example of a standard cell used in this invention,
FIG. 3(b) shows an example after changing the terminal position of FIG. 3(a), and FIG. 4(a). (b) is Fig. 3(a)
．． (b) is an actual layout example, and FIG. 5 is a diagram showing an example of the hardware configuration of the present invention.

In Figures 3 and 4, Figures 3(a) and 4(a)
is a default diagram of a cell according to this invention, and cell frame 2
22 and 23 indicated by cross marks above 1 are changeable terminals. In this case, it is not necessary that all the terminals can be moved to all possible positions, and each terminal 22, 23 has information as to which terminal position it can be moved to. Third
Figures (b) and 4 (b) are similar to Figures 3 (a) and 4 (a).
) shows a cell diagram after giving terminal information to the cell.

In FIG. 5, 31 is a display such as a CRT, 32
is an arithmetic unit, 33 is software library data, 3
4 is a keyboard input device, and 35 is a magnetic disk as a storage medium.

Next, a layout method for a semiconductor integrated circuit according to the present invention will be explained based on FIG. In addition, (1
) to (9) indicate each step.

First, input the netlist (1), and also input the cell name and cell frame. Cell data such as terminal names and positions from which each terminal can be pulled out is registered as a library (2).

Next, the placement and routing program uses the default form of the cell according to the netlist, performs temporary placement and routing (3), then detects the signals routed to adjacent cells, and Search the terminal information of each cell to see if it is possible to move the manual terminal to a position where it can be connected by arranging the cells (4), and if mutually possible, give terminal movement information to each cell (5) . Next, for each cell, it is detected whether the signals connected to that cell cross each other, and if they do, it is detected whether the crossing can be eliminated by moving the terminal positions. If it is possible to eliminate the intersection, it is detected whether the terminal can be moved to that position, and if all possible, terminal movement information is provided to the cell. After changing the terminal positions as described above, temporary wiring is performed again.

This scanning is repeated until there is no need to change the terminal position, and the information of the cells created by this scanning is used to perform the final placement. Perform wiring (6) Transform the cell layout from the cell data and optimal terminal position specification data (7), perform cell allocation based on the final placement and wiring obtained in step (6) (8), and perform the data is stored as layout data (9).

FIG. 2 shows a part of the layout created using the conventional standard cell method shown in FIG. 6, created according to the present invention, and the same part. By protruding terminals 01 of cell C1, terminals If, 02 of cell C2, and terminal I3 of cell C3 at appropriate positions on the side of the cell in FIG. 6, wiring to the wiring area can be eliminated. By replacing the terminals I2, I3 and I4, I5, it is possible to eliminate the need to switch the wiring due to contacts, and to provide a layout diagram with a small area as a whole.

Based on the layout created as described above and the terminal information of each placed cell, the placement is done. By allocating each cell to each cell in the wiring layout while referring to the terminal information of the cell, it is possible to obtain a layout of a semiconductor integrated circuit with a smaller area than the conventional method.

(Effects of the Invention) As explained above, the present invention allows cells in a cell library to be arranged. The cell layout is transformed according to the information given by the wiring program, and after the placement and wiring program has temporarily placed and routed, it detects the position where the wiring to each cell is the shortest and the number of intersections is the least, and the results are saved in the cell library. Since the arrangement and wiring are performed once again, the area of the wiring region can be reduced by reducing the number of contacts and the wiring length for switching back, and a layout diagram with a small area can be obtained.

Further, in the case of adjacent cells, there is an advantage that wiring can be established only by arranging the cells.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing an embodiment of the present invention, FIG. 2 is a diagram showing a layout according to the invention, and FIG.
) is a diagram showing an example of the standard cell used in the present invention, FIG. 3(b) is a diagram showing an example after the terminal position of FIG. 3(a) has been changed, and FIG. 4(a). (b) is Fig. 3(a)
．． (b) is a diagram showing an example of an actual layout, FIG. 5 is a diagram showing an example of the hardware configuration of the present invention, and FIG. 6 is a diagram showing a layout created using the conventional standard cell method. In the figure, C1 to C7 are cells, 21 is a cell frame, 22 and 23 are changeable terminals, 31 is a display, 32 is an arithmetic unit, 33 is software library data, 34 is a keyboard input device, and 35 is a magnetic disk. be. Younger brother figure 2 figure 5 ivy figure 4 figure (a) (b) younger brother figure 6

Claims (2)

[Claims] (1) In a semiconductor integrated circuit layout method using a standard cell method using a placement and wiring program, cells in a cell library are placed and placed by transforming the cell layout according to information given from the placement and wiring program.
A semiconductor integrated circuit characterized in that, after the wiring program has temporarily placed and routed, the wiring program detects the position where the wiring to each cell is the shortest and the number of intersections is the least, and provides the result to the cell library to perform the placement and wiring again. layout method. (2) A claim characterized in that when adjacent cells are wired, the cell layout in the cell library is performed in such a way that connections are made only by cell placement, according to conditions given by a placement and wiring program. (1) The semiconductor integrated circuit layout method described in (1).