JPH0329357A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To impress a stable potential on the whole of a chip by a method wherein a part on which a substrate potential is impressed is at the inside of a bonding-pad input protective circuit. CONSTITUTION:An interconnection 13 on which a substrate potential is impressed is connected to a substrate 19 at the inside of a bonding-pad input protective circuit 12. Since it is connected to the substrate 19 at the side which is inner by about 10mum of a length portion of a bonding pad 12 as compared with conventional arrangements, a distance to the center part of a semiconductor chip 11 becomes short and a resistance to the center of a chip as a remote end is reduced. Thereby, a stable potential can be impressed on the whole of the chip; carriers which are generated from the input protective circuit can be shielded.

Description

[Detailed Description of the Invention] [Industrial Application Fields] [The present invention] The present invention relates to a semiconductor memory device, and particularly to a location where wiring for applying a substrate bias is formed.

[Prior Art] Conventionally, in this type of semiconductor memory device, many transistors are formed on the same substrate, resulting in the formation of parasitic pn junctions. In order to prevent these pn junctions from adversely affecting circuit operation, a bias is applied to the substrate so that a reverse voltage is always applied.

The two specific effects are to prevent the parasitic pn junction from becoming forward biased and to expand the depletion layer at the junction, reducing parasitic capacitance and speeding up circuit operation. .

The wiring 23 giving this potential is connected to the bonding pad 22
The chip 2l is arranged to be connected to the substrate at its outermost periphery so as to surround the entire circuit 24 including the circuit 24 (FIG. 2).

[Problems to be Solved by the Invention] The conventional semiconductor memory device described above is connected to the substrate at the outermost periphery of the chip, so that the center of the chip is the farthest end. Therefore, there is a drawback that the effect is reduced because there is more resistance at the center than at the outer periphery.

[Differences between the invention and the prior art] Compared to the conventional semiconductor memory device described above, the present invention has a difference in that the position for applying a bias to the substrate is connected between the bonding pad and the associated human power protection circuit and the array area. Has a point.

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a semiconductor integrated circuit formed on a semiconductor substrate, and a semiconductor integrated circuit for the semiconductor integrated circuit arranged on the semiconductor substrate so as to surround the semiconductor integrated circuit. In a semiconductor memory device comprising: an input/output circuit and an input/output terminal section; and wiring for applying a bias voltage to the semiconductor substrate, the wiring is connected to the semiconductor integrated circuit, the input/output circuit, and the input/output terminal section. This is a semiconductor memory device characterized in that it is disposed between.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 and 2 are a schematic diagram and a cross-sectional view of the layout of a semiconductor chip for explaining an embodiment of the present invention.

First, as shown in FIG. 1, a wiring l3 for applying a substrate potential is connected to the substrate inside the bonding pad/manpower protection circuit l2. Therefore, since the bonding pad 12 is connected to the substrate about 10 μm inside the length of the bonding pad 12 compared to the conventional arrangement, the distance to the middle part of the semiconductor chip 11 is shortened, and the resistance that is built up to the far end (the center of the chip) is reduced. .

Therefore, the parasitic pn junction can be prevented from becoming forward biased, and the width of the depletion layer at the junction can be expanded to further reduce the parasitic capacitance. Furthermore, when the input protection circuit is made using the diffusion layer resistor 15, when a high voltage is applied to the bonding pad 12, carriers are released into the semiconductor substrate 19 through the diffusion layer resistor 15, and It may move through the substrate and reach the back of the memory, affecting the charge retention time. However, as shown in FIG. 1, there is a P-type diffusion layer 18 to which a substrate potential is applied between the input protection circuit and the memory cell region 14, so carriers generated from the input protection circuit It has the advantage of also having the role of a shield against.

[Effects of the Invention] As explained above, the present invention makes it possible to apply a stable potential to the entire chip by placing the substrate potential inside the bonding pad/input protection circuit.
It also has the effect of shielding carriers generated from the human power protection circuit.

[Brief explanation of drawings]

FIG. 1 is a plan view of a semiconductor chip for explaining an embodiment of the present invention, FIG. 2 is a sectional view taken along the line
The figure is a plan view of a conventional semiconductor chip. 1 l ● 1 2 ・ 1 3 ◆ 1 4 ・ 1 5 ・ 1 6 ・ 17 ● 18 ・ 1 9 ● ・Semiconductor chip, ・Bonding pad, Substrate potential wiring/subcontact, Memory cell/peripheral circuit area, Input protection resistor (N+ diffusion layer), substrate potential wiring, interlayer insulation film, P3 diffusion layer, P-type semiconductor substrate.

Claims (1)

[Scope of Claims] A semiconductor integrated circuit formed on a semiconductor substrate, an input/output circuit and an input/output terminal section for the semiconductor integrated circuit disposed on the semiconductor substrate so as to surround the semiconductor integrated circuit, and a wiring for applying a bias voltage to a semiconductor substrate; and a semiconductor memory device, characterized in that the wiring is arranged between the semiconductor integrated circuit, the input/output circuit, and the input/output terminal section. Semiconductor storage device.