JPH0329405A - Variable gain circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a variable gain circuit that can linearly and electrically vary the III gain, the present invention provides a variable gain circuit that can linearly vary the gain without increasing the scale of the circuit, and that can widen the input dynamic range. The purpose is to obtain a certain level of control without being limited by the differential pair of transistors, by comparing the input voltage and the first voltage, and separately outputting the first and second signals at levels corresponding to each level. The signals of the first and second signals taken out from the first comparator and the first comparator are respectively supplied, and a voltage according to the level difference between them is generated and the first voltage is set as the first voltage.
By supplying the voltage to the comparator, the first differential output means, which together with the first comparator constitutes a negative return amplifier, the first υIIl] voltage and the second sub-voltage at arbitrary levels. IIIt[I voltage source to output and the first
and a second tI11 control voltage and the first signal are supplied, and a third signal having a level corresponding to the product of the difference voltage between the first and second W control voltages and the first signal is supplied. 12 comparators are supplied with the first and second control am pressures and the second signal, and the product of the difference voltage between the first and second control mvt pressures and the second signal is A third comparator that generates a fourth signal with a level corresponding to It consists of a second differential output means that generates a second voltage and outputs it to the output terminal as an output '17]', and is configured to vary the gain by varying the first and second control voltages. do.

[Industrial application field]

The present invention relates to a variable gain circuit, and particularly to a variable gain circuit that can linearly and electrically vary the gain.

Currently, variable gain circuits are widely used in various fields, and similarly various gain b+@ h methods have been proposed. However, with the recent development of electronics, it is necessary that this gain υJilt can also be achieved electrically.

? Prior Art] FIG. 5 shows a circuit diagram of an example of a conventional variable gain circuit. In the figure, 41 is an input terminal, 42 is a differential amplifier. 43 is a resistor, 44 is a variable resistor. 45 is the output terminal, and the differential amplifier 4
A connection point between the output terminal of No. 2 and the output terminal 45 is grounded through a resistor 43 and a variable resistor 44 in series. Further, a connection point between the resistor 43 and the variable resistor 44 is connected to an inverting input terminal of the differential amplifier 42.

According to this conventional variable gain circuit, the input voltage is VIN, the output voltage is VOUT, and the resistor 43. Variable resistor 4
If the respective resistance values of 4 are Ra and Rb, the input Tiff
．． VIN and output voltage V. Regarding the relationship between U and ■, of course, the gain can be similarly varied by using the resistor 43 as a variable w1 resistor and varying R.

Furthermore, as a modification of the conventional variable gain circuit shown in FIG. 5, a circuit configuration as shown in FIG. 6 is also known. In the figure, an input terminal 51 is connected to a differential amplifier 53 via a resistor 52.
Connected to the inverting input terminal of Also, the differential amplifier 5
The output terminal of No. 3 is feedback-connected to the inverting input terminal via a resistor 54, and is also connected to an output pane 55.

According to this conventional variable gain circuit, the input voltage vIN is inverted and amplified to provide an output voltage V to the pane 55. Take out IJ1.

Here, if each resistance of resistors 52 and 54 is R,, Rd, then V. , 1 are expressed by the following equation.

Therefore, as can be seen from equation (1), the gain can be varied by varying the resistance In R fi using the variable resistor 44.

Therefore, as can be seen from equation (2), the resistances iCiRc, R
By varying either d or h, the profit is 1! ? can be varied.

Furthermore, a variable gain circuit as shown in FIG. 7 is also known. In the figure, an input terminal 61 is connected to a non-inverting input terminal of a differential amplifier 62. Further, the output end of the differential amplifier 62 is grounded through a resistor 63 and a resistor 64 in series, and is also connected to an output terminal 67.

The resistor 64 is nII! It has tap terminals I, and is configured to connect or open two adjacent tap panes using analog switches 65+ to 65Tl.

66 is a switching control circuit, which is an AB log switch 651.
~65n are switched independently of each other.

According to the conventional 8-curve variable circuit having such a configuration, the output ′! R
8-VQIJ is the resistance value of resistor 63. , when the resistance value of the resistor 64 obtained by selecting the analog switches 651 to 65n is R', it is expressed as follows. Therefore, as can be seen from the above equation, the gain can be varied by appropriately selecting and turning on the analog switches 651 to 65y+ and varying the resistance value R'.

Furthermore, a variable gain circuit as shown in FIG. 8 is also known. In the figure, 71 is an input terminal. 72 is a comparator,
73 is a current source. 74 and 75 are output terminals having opposite phases to each other.

An example of a specific circuit configuration of the variable gain circuit shown in FIG. 8 is shown in FIG. In the figure, the same reference numerals are given to the same RFT parts as in FIG. 8. In Figure 9, each emitsuta is 1! Each collector of the NPN transistor 'rl'r2 commonly connected to the current source 73 is connected to a resistor R, .R.
h is connected separately to the load resistor.

In this conventional variable gain circuit, the input voltage input to the base of the transistor Tr1 via the eight-power switch 71 is vIN, and the output voltage output from the output terminal 74.75 is VIN. UT1, vOUT2, and power supply f4 voltage to VC
C. Let the current of the current source 73 be 1 and R9-Rh-R.

When the input voltage v1N is equal to zero volts, which is the base input voltage of the transistor Tr2, the transistor T. and "The collector currents of r2 are each 1/2 and equal. Also,
As the input voltage V[N increases in the positive direction, the collector current of the transistor ``,'' increases, and the collector current of the transistor ``r2'' decreases.

Conversely, when the input voltage V increases in the negative direction, the collector current of the transistor ``,1 decreases, and the transistor fr
2 collector current increases.

As a result, the output voltage V OUTI taken out from the collector of the transistor ", 1" and the output voltage V 011T2r2 taken out from the collector of the transistor T 1 are respectively expressed by the following equations.

(4a) (4b) ? Dashi, (4a). (4b) where VT is the thermal voltage, k is the Boltzmann constant, and T is the absolute temperature. When the electron charge is ffi{q, it is expressed as k T /q. Note that equations (4a) and (4b) are for the transistor T
r1 and Tr2 operate in the active region -2 V T <
This is an approximate expression within the range of V IN < 2Vr.

Therefore, the relationship between the above-mentioned output voltages V OUTI and v■υT2 and the human power voltage ■ is as shown in FIG.

As can be seen from the figure, when the input voltage VIN is 2V or more, or -2V or less, the output voltage VOUTI
vOU2 is saturated. Figure 8 with such characteristics. According to the conventional variable gain circuit shown in FIG. 9, as can be seen from equations (4a) and (4b), by varying the current value I of the current source 73, the input IR 13'. V, even if the value is the same, the output voltage V. U.T.
1"OtlT2> can be changed (ie, the gain can be varied).

[Problem to be solved by the invention]

However, in the conventional variable gain circuit shown in FIGS. 5 and 6, either the resistors 43 and 44 or the resistors 52 and 54
Mechanically changes the resistance value of either
It was not something that could be changed electrically.

Further, although the conventional gain variable circuit shown in FIG. 7 can electrically vary the gain, the resistance value R, is the analog switch 651 to 65? Since the change in gain is made stepwise by switching I, the change in gain also becomes stepwise, resulting in too large a systematic change, and there is also the problem that the circuit size is large.

Furthermore, Fig. 8. The conventional variable gain circuit shown in FIG.
JL style! 11i73, whose current value I is linear, and
By using an electrically variable configuration, the gain can also be electrically varied linearly, but the dynamic range of the input is limited by configuring a differential pair as shown in Figure 10. Transistor Ding. , due to the characteristics of Tr2 -? There was a problem in that it was saturated at a value of ±2 times or more than Lepoluage V-cho.

The present invention has been made in view of the above points, and it is possible to linearly vary the gain without increasing the scale of the circuit, and to vary the input dynamic range to a certain extent without limiting the dust by using a differential pair. The purpose is to provide circuits.

(F stage for solving problem I) FIG. 11 shows a diagram of the principle configuration of the present invention. In the figure, 11 is a first comparator, 12 is a first differential output means, and
The converter 911 has an input voltage VI from the input terminal 10.
N and the output first voltage of the differential output f stage 12 of ffil are compared, and the first voltage of the level corresponding to each level is compared. A second signal is output separately. The first differential output means 12 generates a voltage according to the level difference between these signals 11 and the second signal,
Further, together with the first comparator 11, a negative feedback 3I amplifier is configured.

13LIL$1J10 voltage source, 1st (7) i! IJt
il voltage V,1 and a second control voltage VC2 are generated, respectively. 14 is a second comparator, 15 is a third comparator, both of which are supplied with the first and second control voltages; the second comparator 14 is further supplied with the first signal; Further, the second credit is input. As a result, the second comparator 14 generates a third signal corresponding to the product of the first signal and the difference voltage between the first and second control voltages. Similarly, the third comparator 15 generates a fourth signal corresponding to the product of the voltage difference and the second signal.

Reference numeral 16 denotes a second differential output means, which generates a second voltage at a level corresponding to the value of the difference between the third and fourth signals, and outputs this to the output terminal 17 as an output voltage V... do.

[Effect]

The third current generated by the second comparator 14 and the fourth current generated by the third comparator 15 are both connected to the first control voltage and the second (DtllmYi
It changes depending on the pressure and (r) differential voltage (V c2 'cl).

A second differential output means 16 generates a second voltage corresponding to the difference between these third and fourth signals 8. Therefore, this second voltage, that is, the output N pressure is controlled by m
It can be varied by varying the voltages Vcl and vc2.

(Example) FIG. 2 shows a circuit diagram of a first embodiment of the invention.

In the figure, the same components as in FIG. 1 are designated by the same reference numerals. In FIG. 2, NPN} transistors Q+ and Q2
The emitters of Q1 are commonly connected to the current source 21, the collector of Q1 is connected to the collector and base of a PNP transistor Q3, respectively, and the collector of Q2 is a PNP transistor. 4 collector and base, respectively.

PNPi-transistor Qs. Each collector of Q6 is an NPN transistor Q7. It is connected to the collector of transistor Q8, and the collector of transistor Q6 is further connected to the base of transistor Q2. On the other hand, it is connected to resistor R1. The base of transistor Q6 is transistor Q3
and the bases of a PNP transistor QI3, which will be described later, and constitute a current mirror circuit. Similarly, the base of the transistor Qs is connected to the base of the transistor Q4 and the base of a PNP transistor Q9, which will be described later, respectively, and the base of the transistor Qs. Qs. Q9
constitutes a current mirror circuit.

Further, the bases of transistors Q7 and Q8 are also commonly connected to form a current mirror circuit.

In addition, 22.23 is a bias voltage source, which is a DC voltage v
R1 is superimposed on the input voltage VIN and the base voltage of transistor Q2. Collector P of the transistor Q9
It is connected to the emitters of NP transistors Q+o and Qn, respectively, and the collector of the transistor QI3 is connected to the emitters of PNP transistors QI4 and Q+s, respectively.

Transistor Qn. Each collector of Q+s is connected to the collector and base of an NPN transistor QI2.0l6, respectively, and the collector of Qn. The base of Q+s is 1st it, II Gozuko C
It is said that the configuration is such that the first control voltage c1 is applied via the NTI. The other transistor Q+o. constitutes a differential pair with the transistors Qn and Q+s. The base of QI4 is connected to the second υJwJ voltage vc via the second control terminal CNT2.
2 is applied.

Each base of the transistors QI2, Q+a is connected to an NPN transistor Qu+. It is connected to each base of Q+r, and Q
I2 and Q+s constitute a current mirror circuit, and QI5 and QI7 also constitute a current mirror circuit.

A current mihoo circuit consisting of a PNP transistor QI9.021 is connected to the collector side of the transistor QI7.0I8. Further, a common connection point between the collectors of the transistors On and Qu+ is connected to the output terminal 17, and is also connected to the voltage source 24 via a resistor R2. Voltage #R
Reference numeral 24 is for setting the DC potential of the output voltage to VR2.

In such a variable gain circuit, the input voltage V applied to the base of the transistor Q1 via the input terminal 10
It is assumed that IN has changed by ΔVIN. In this case, the collector current Ic of transistor QI
1 increases corresponding to ΔVJN, and the collector current I
The collector current I of transistor Q2 increases by the amount of increase in C1.

2 is about to decrease. The collector current I is equal to the collector current IC3 of the transistor Q3, and since the transistor Q3 forms a current mirror circuit with the transistor Q6, the transistor Q6
collector current! . 6 flows approximately equal to Ic1.

On the other hand, the collector current IC2 is equal to the collector current 11.4 of the transistor Q4, and since the transistor Q4 forms a current mirror circuit with the transistor Qs,
The collector current 'c5 of the transistor Q5 becomes approximately equal to 'c2.

The collector current IC5 of the transistor Qs is supplied to the collector of the transistor Q7, and the collector current IC5 of the transistor Qs is supplied to the collector of the transistor Q7. Collector current of! , 7, but a current having substantially the same value as the collector current 1, 7 (-1.5) of this transistor Q7 flows through the transistor Q8 forming a current mirror circuit with Q7.

Therefore, if we ignore the base current of transistor Q2,
10UTI-ICCI IC5"lC1-IC2 to resistor R1
"Electricity represented by" IOUT1 flows. In this way, the circuit consisting of transistors 01 to 08, etc. operates as a negative feedback amplifier, and the power at the connection point between the base of transistor Q2 and resistor R+ is I. It is increased by lITIR1, which is equal to the change in input voltage Δv1N applied to the base of transistor Q1. That is,
Transistor Q+. Q2 operates so that both base potentials are equal, and 10UT1”8V I N / R
+f3' is obtained.

On the other hand, transistor Q4. Qs and Q9 constitute a current mirror circuit, and transistors Q3 . Q
Since transistors Q9.s and QI3 also constitute a current mirror circuit, transistors Q9. Each collector current of QI3 [C9,
IC13 is 'c9'c5 / 'C13'C6
('7).

Since the transistor Q9 constitutes a current source of the transistor QIO and an ON differential pair transistor, its collector current Ic9 is the same as the transistor QIO. Qn. QI2
Determine the mutual inductance of the comparator. As a result, transistor Q
The current I,12 flowing through the transistor QI2, which is the collector load of n, is expressed by the following equation, where v1 is the thermal voltage.

That is, transistor QIO. A control voltage vc2. applied to each base of QI+. When vC1 is equal, transistor Q1●. Equal currents represented by 1c9/2 flow through Q++, but as the differential voltage (vC2--C1) of the iIIIIIII voltage increases, the collector current 1 (=1) of the transistor Qn increases cl2c11.

Similarly, the current IC16 flowing through the transistor Ql6, which is the collector voltage of the transistor QCs, is expressed by the following equation.

? 9) Since the above transistors Q+2 and Ql6 each constitute a current mirror circuit with the transistor QI8.0l7, ■cl2 "cl8 ・ 'clB "c17
``''. Also, transistor Q17
'clr = 'cl9 ''' c20 Since the collector current and the current flow through the transistor QI9, which forms a current mirror circuit with the transistor Q■.
A current 'c20 with the following relationship flows through the transistor Qte.

Therefore, the current flowing through resistor R2 is I.
・If the current flowing through the resistor QCs is ■, then ■c1
8 From formula (11), 1 becomes as shown in the following formula.

OυT2 'OUT2'''''' c20 'cl6 2 R (12) As a result, the variation ΔV OUT in the output voltage appearing at the output terminal 17 is expressed by the following equation.

△V=I・R20UT
0 11 T 2 (13) Therefore, tree nuts 7Il! The alternating current gain G of the jN circuit is (1
3) Using the formula, the following formula AVIN 4v 2 R + (14
).

Equation (14) is based on the transistor QIO. Qn. Ql
4. QCs operate in active region -2vT vc2-
It is an approximate expression within the range of v,1<2V, and the gain △VOU is
A characteristic diagram with T/ΔVIN as the vertical axis is shown in FIG.

As can be seen from Figure 3, the differential voltage (V c2 - V
, 1), the gain 19 can be varied linearly.

Also, II1 control voltage V. 1 and vc2 can be electrically varied. Furthermore, in the conventional circuit shown in FIG. 8, the output saturates when the input voltage VIN exceeds ±2V, limiting the input dynamic range.
In this embodiment, such manual dynamic range is not limited by the single transistor differential pair.

In addition, the output current according to the change in input voltage 'OtlT
2 is applied to the load resistor R2, and the output voltage is 1q. Since it is not necessary to make the input and output DC levels the same, for example, level shifting can be performed at the same time using the DC voltage Ill 2 4. ,,Furthermore, according to this embodiment, since A can always operate at a low voltage, low power consumption can be achieved. Further, the circuit scale can be configured to be smaller than the conventional circuit shown in FIG.

Next, a second embodiment of the present invention will be described. FIG. 4 includes a circuit diagram of the second embodiment of the present invention. In the figure, the same components as those in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted.

In this embodiment, the transistors 01 to Qn of the first embodiment are
NP type becomes NPN type, and NPN type becomes PN.
This circuit configuration is replaced with a P-type circuit, and is basically based on the same principle of operation as the first embodiment. In Figure 4, transistors that have the same function as those in Figure 2 but differ only in conductivity type from Figure 2 are marked with the same symbol g as in Figure 2.
What does the dash mean and omit its explanation?

In FIG. 4, Q2+. Q22 is an NPN transistor, the emitter of the transistor Q2+ is connected to the base of the PNP transistor Q+' and the current source 31, respectively, and the emitter of the transistor Q22 is connected to the PNP transistor Qz.
' and the current +1132, respectively.

Further, the base of the transistor Q2+ is connected to the input terminal 10, and the base of the transistor Q22 is connected to a common connection point between the low resistor R1 and the collectors of the transistors Qs' and Q8'. Further, 33 is a current source corresponding to the current lIl21.

In this embodiment, the input voltage vIN is inputted to the bases of the transistors Q and l via the base and emitter of the transistor Q2+ which forms the lower emitter node A. Also, the voltage generated in the low resistor R+ is the same as that of the emitter follower 1~
It is applied to the base of transistor Q2' via the base and emitter of transistor Q22.

According to this embodiment, the bias voltage source 22.23 is
I control voltage V. 1, Vc2 is q! Transistor Q added
IG'. Qo'. Since they are the same NPN transistors Q2+ and Q22 as Ql4 and QCs', l.
This embodiment has the same feature as the first embodiment, in that the bias voltage for the bias voltage sources 22 and 23 can be obtained from the IIIil\pressure source 13.

〔Effect of the invention〕

As described above, according to the present invention, the II gain can be linearly varied by varying the II voltage without increasing the scale of the circuit, and the control voltage can be electrically varied. Therefore, the gain can be electrically varied, and the input dynamic range is not limited by the differential pair of transistors, so it can be increased to a certain extent.
From the above, it has the characteristic of blue that contributes to the improvement of the function of the q variable circuit.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is a circuit diagram of the first embodiment of the invention, Fig. 13 is a characteristic diagram of Fig. 2, and Fig. 4 is a circuit diagram of the second embodiment of the invention. , FIG. 5 is a circuit diagram of a conventional example, FIG. 6 is a circuit diagram of a modification of FIG. 5, FIGS. 7 and 8 are circuit diagrams of other conventional examples, respectively, and FIG. 8 is a specific circuit diagram, and FIG. 10 is an input voltage vs. output voltage characteristic diagram of FIG. 9. In the figure, 11 is a first comparator, 12 is a first differential output means, 13 is a control III voltage source, 14 is a second comparator, 15 is a third comparator, and 16 is a second differential. dynamic output means; 17 indicates an output terminal; Fig. 1 Broom 2 Fig. 1 Fig. 3 Fig. 8 Fig. 9 Fig. 10

Claims (1)

[Claims] A first comparator (11) that compares an input voltage and a first voltage and separately outputs first and second signals at levels corresponding to the respective levels; The first value taken out from the comparator (11) of
and a second signal are respectively supplied, and by generating a voltage according to the level difference between them and supplying it as the first voltage to the first comparator (11), the first comparator (11) a first differential output means (12) which together constitute a negative feedback amplifier; a control voltage source (13) which outputs a first control voltage and a second control voltage at arbitrary levels, respectively; and a second control voltage and the first signal;
a second comparator (14) that generates a third signal having a level corresponding to the product of the voltage difference between the control voltages and the first signal;
, the first and second control voltages, and the second signal are supplied, and the fourth signal has a level corresponding to the product of the difference voltage between the first and second control voltages and the second signal. a third signal that generates a signal of
The comparator (15) and the third and fourth signals taken out from the second and third comparators (14, 15) are respectively supplied, and a second current is generated according to the difference between them. and a second differential output means (16) that outputs an output voltage to an output terminal (17), and is configured to vary the gain by varying the first and second control voltages. Features variable gain circuit.