JPH032997Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Technical field The present invention relates to a power-on reset circuit that utilizes the capacitor terminal voltage of a CR oscillator that performs oscillation operation using a capacitor and a resistor. Low-voltage operation ICs such as integrated circuits)
The present invention relates to a power-on reset circuit that is most suitable for

(b) Prior Art Conventionally, as shown in FIG. 1, for example, a power-on reset circuit that performs power-on reset using the terminal voltage of a capacitor Cosc of a CR oscillator has been widely used. In Figure 1,
C1 and C2 are comparators used for power-on reset and oscillation, respectively, Q1 and Q
2 is a transistor, D1 is a diode R1 to R7
is resistance.

In this case, the operation of the oscillator is as follows.

The maximum value of the charging voltage of capacitor Cosc during oscillation is when the output of comparator C2 of the oscillator is L (low level) and transistors Q1 and Q2 are off (at this time, capacitor Cosc is charged).
The reference voltage applied to the inverting input terminal of comparator C2 at The capacitor Oosc is charged until the terminal voltage reaches this Vref (H). When the terminal voltage of capacitor Cosc exceeds Vref (H),
Comparator C2 is inverted and the output is H (high level)
As a result, transistors Q1 and Q2 turn on, capacitor Oosc stops discharging, and the terminal voltage becomes the reference voltage, that is, Vref (L) = {(R6//R5)/( R6//R5 +R4)}Vcc+Vio...(2) (However, R6//R5 indicates the parallel resistance value of resistors R6 and R5.) When the value is below, comparator C2 is inverted again and the output becomes L, capacitor Oosc will be charged again. This is repeated to generate oscillation. Therefore, the minimum value of the terminal voltage of the capacitor Cosc during oscillation is Vref (L) shown in equation (2). In addition, the above-mentioned capacitor Cosc is charged by the resistor R from the power supply Vcc.
1 and R2, the charging time t is t=Cosc(R1+R2)ln[{Vcc-Vref(L)}/{Vcc-Vref(H)}]...(3) However, ln is the real logarithm). Here, the terminal voltage waveform of the capacitor Oosc is as shown in FIG.

On the other hand, comparator C for power-on reset
1 compares the terminal voltage of the capacitor Oosc at point A in Figure 1, which is applied to the inverting input terminal, with the forward direction V _BE of the diode D1 at point B in Figure 1, which is the reference voltage applied to the non-inverting input terminal, When the voltage at point A is lower than the voltage at point B, the reset output is set to H, ie, reset is on, and when the voltage at point A is higher, the reset output is set to L, ie, reset is off.

Therefore, as shown in Figure 3, when the power is turned on, as the power supply voltage rises, the voltages at points A and B both rise, but since the voltage at point A is the charging voltage of the capacitor Cosc, the order of the diode D1 directional voltage
The rise is gradual compared to the voltage at point B, which is _VBE . Therefore, immediately after the power is turned on, the voltage at point B is higher than that at point A, and the output of comparator C1 is in the H state, so that the reset output rises almost in the same way as the power supply voltage rises. The forward voltage V _BE of the diode D1 is about 0.7V, and if the maximum value of the charging voltage of the capacitor Cosc is set higher than that, for example about 2.2V as shown in Fig. 2, the capacitor Cosc will increase as shown in Fig. 3. As charging progresses, the terminal voltage increases.
Reset off when it exceeds 0.7V.

By the way, in this case, the V _BE of the single stage diode D1
is 0.6V to 0.7V, and CMOS (complementary metal oxide semiconductor) circuits generally do not work at this level of power supply voltage. (Threshold level of CMOS circuit
By lowering Vth, it is possible to operate with a low power supply voltage, but it is difficult to stabilize low Vth CMOS in manufacturing. ) Generally Vth is 0.6±0.3V
CMOS (both P channel and N channel) requires a power supply voltage of at least 1 to 1.2V. Therefore, if we use two stages of diodes to provide the reference voltage for power-on reset, the reset release voltage will be 1.2
~1.4V, which is preferable, but in the case of low voltage operation, the rated value of the power supply voltage Vcc
In order to set the voltage to about 2V, Vref (H) in equation (1) and Vref (H) in equation (2) are
Since Vref (L) is about 1.6 to 1.0V, a reset is always applied during the oscillation operation, resulting in instability.

Therefore, the present applicant has previously proposed the following invention regarding a power-on reset circuit that enables reliable power-on reset even for low-voltage operating circuits and is stable even in a steady oscillation state (patent application No. No. 58-31297).

That is, as shown in Fig. 4, a comparator that can obtain a normal comparator output and an inverted output of the output is used as the comparator C3 for power-on reset (of course, the normal comparator output can be inverted and an inverted output is obtained). ), and the diode for obtaining the comparison reference voltage has a two-stage structure consisting of a series circuit of D2 and D3. Then, the connection point of these diodes D2 and D3 is connected to the ground potential through the collector-emitter of the transistor Q3, and the transistor Q
The base of the transistor Q3 is connected to the inverted output of the comparator C3 via the resistor R8, and the transistor Q3 is turned on when the inverted output is high, that is, when the reset is off.

In such a configuration, when the power supply voltage rises, transistor Q3 is off,
The comparison reference voltage of comparator C3 for power-on reset is 2V _BE . The power supply voltage increases,
When capacitor Cosc is charged and the terminal voltage of capacitor Cosc becomes greater than 2V _BE , comparator C3 is inverted and reset off, transistor Q3 is turned on, diode D3 is shorted, and the reference voltage for comparison is only diode D2. becomes V _BE given by and then the capacitor
Oscillation operation can be performed without problems even if the terminal voltage of Cosc drops to about 1.0V.

In this way, even when applied to a low-voltage operation circuit such as a low-voltage CMOS, a reliable and effective power-on reset operation can be performed, and the reset can be canceled only after the power supply voltage has risen sufficiently. There is no risk of destabilizing the steady oscillation operation.

However, even when such a method is adopted, the following problems occur.

FIG. 5 shows an example of a configuration in which the method shown in FIG. 4 described above is implemented, with the same reference numerals assigned to parts corresponding to those in FIG. 4.

In Figure 5, when the potential across the capacitor Cosc is set to a maximum of about 1.3V, the reset circuit
The reference voltage of RST, that is, the comparison reference potential of comparator C3, is approximately
It was necessary to set it to around 1.2V. (However, when oscillation starts, transistor Q3 turns on and the reference voltage becomes 0.6V for one stage of diode.) However, the terminal potential of capacitor Cosc during oscillation is about 0.8 to 1.2V. On the other hand, especially at low temperatures, the V _BE of the diode
may rise, and the reference voltage of the reset circuit RST for the two stages of diodes D2 and D3 may reach about 1.3V. At this time, the terminal potential of the capacitor does not exceed the reference potential no matter how long it takes, and the reset output is not turned off, so the reset remains applied.

(c) Purpose The present invention was developed in view of the above circumstances, and its purpose is to enable reliable power-on reset even for low-voltage operating circuits, and to ensure stability even in steady oscillation conditions. It is an object of the present invention to provide a power-on reset circuit which is free from malfunction even at low temperatures.

(D) Configuration The configuration of the present invention will be explained below based on one embodiment.

In FIG. 5 described earlier, in order to increase the potential at the oscillation capacitor end (base of capacitor Q4) until the reset output changes from "H" to "L", transistor Q1 is turned on and resistor R is turned on.
2. It is sufficient as long as there is no discharge through R3. That is, for this purpose, while the reset output is "H" (when transistor Q5 is off)
The transistor Q1 may be turned off.

Therefore, in one embodiment of the present invention, as shown in FIG. 6, the base potential of the transistor Q7 is controlled by the output of the transistor Q6, which is provided to operate in the same phase as the transistor Q5, and this transistor Q7 is used to control the base potential of the transistor Q1. The base potential of the terminal is switched.

By doing this, immediately after power is turned on, when transistor Q5 is off (same goes for Q6) and a reset output (H) is being output, transistor Q
7 is turned on, so that the transistor Q1, which forms the discharge circuit for the capacitor Cosc in cooperation with the resistors R2 and R3, is forcibly turned off, and the above-mentioned discharge operation is inhibited. Therefore, in this state, oscillation operation does not start.

Then, the terminal voltage of the capacitor Cosc gradually continues to rise, and when it becomes higher than the reference voltage (2V _BE ), the transistor Q5 turns on (same goes for Q6), and therefore, both the reset output and the reset release output become L. Therefore, in response to the reset release output, transistor Q7 is turned off, and transistor Q1, which forms the discharge circuit, is turned off for the first time.
Therefore, the oscillation circuit OSC starts normal oscillation operation on condition that the terminal voltage of the capacitor Cosc exceeds the anode voltage of the diode D2.

As described above, stable reset oscillation operation can be performed even at low temperatures.

Note that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof.

For example, in the above description, we have mainly explained the case at low temperatures, but not only at low temperatures, but also when making an IC, the oscillation capacitor voltage may change from 0.8 to 1.2V to 0.9 to 1.V due to variations in element characteristics. This is well thought out and is useful for improving IC yield in such cases.

(e) Effects According to the present invention, it is possible to perform a reliable power-on reset even for a low-voltage operating circuit, and the power-on reset is stable even in a steady oscillation state, and there is no risk of malfunction at low temperatures. The circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing the configuration of an example of a conventional device, FIGS. 2 and 3 are waveform diagrams for explaining the same example, and FIG. 4 is a prior invention filed by the present applicant. FIG. 5 is a circuit configuration diagram showing an example of the configuration of
A circuit diagram showing the configuration of Fig. 4 in more detail, Fig. 6
The figure is a circuit configuration diagram showing the configuration of an embodiment of the present invention. C2, C3... Comparator, Q1~Q7...
Transistor, Cosc...Capacitor, D2, D
3...Diode, R1-R6...Resistance.

Claims (1)

[Scope of utility model registration request] In a power-on reset circuit that obtains a reset signal when the power is turned on by comparing the terminal voltage of the capacitor mentioned above with a reference voltage of an oscillator that performs oscillation operation using a capacitor and a resistor, the reset signal is set higher than during normal operation before the reset is released. means for switching the reference voltage so as to lower the reference voltage in response to a reset release output when the power is turned on; and prior to the reset release, blocking a discharge operation of a discharge circuit that controls the oscillation operation of the capacitor; A power-on reset circuit comprising means for releasing the blocking of the discharging operation in response to the reset release output so as to enable the oscillation operation.