JPH0330037A - Buffer storage device - Google Patents

Abstract

PURPOSE:To alternately use two cache memories by a simple constitution by providing an extension bit on a register of a replacement control means (LRU control circuit) of the cache memory of a set associative system, and bringing it to external control. CONSTITUTION:On registers REG1 - REGn for constituting an LRU control circuit for controlling the replacement at the time of mishit of a cache memory, not only bit trains F1 - F6 but also a diffusion bit train F7 are provided. When this bit train F7 is brought to external connection and brought to external control, a way is selected, the management can be executed so that two pieces of cache memories can be used alternately by a simple constitution, and by using plural cache memories and extending the way, the bit rate can be enhanced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a storage management technique and a technique that is particularly effective when applied to a control method for a buffer storage device, for example, in an information processing system employing a buffer storage method. This article relates to techniques that are effective for use in cache memory expansion methods.

[Prior Art] Conventionally, in a microcomputer that employs a buffer storage method, frequently used information in a main storage device such as a dynamic RAM is stored in a cache memory, and this information is stored in a cache controller. There are some devices that are controlled by a storage management device called ``Storage Management System'' to improve throughput.

The hit rate of a cache memory increases as the capacity of its data section increases. However, since a cache memory is often provided with a directory memory section for storing tag addresses and a tag comparator in addition to the data section on the same chip, the capacity of the data section cannot be made very large. Therefore, as shown in FIG.
EM to microprocessor MPU and main memory M-M
A method has been proposed in which the capacity of the data section is expanded by connecting a plurality of EMs in parallel.

[Problems to be Solved by the Invention] However, in a set-associative cache memory in which a data block in the main memory can be associated with multiple blocks in the cache memory. LRU (Least Recent
It is necessary to manage ways using a method such as yUsed). However, by simply connecting two cache memories in parallel, expansion in the column direction and bit direction is possible, but expansion in the way direction is not possible because way management between chips cannot be performed. Therefore, there was a problem in that even if the number of memories was increased, the hit rate could not be sufficiently improved.

The cache memory is described in "Nikkei Microdevice J, April 1987 issue, pages 87 to 90. An object of the present invention is to connect a plurality of set associative type cache memories and The objective is to enable expansion and thereby improve the cache hit rate.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings. [Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, in a set-associative cache memory, expansion bits are added to the registers that constitute the LRU control circuit for specifying blocks to be replaced in the event of a mishit, and the expansion bits are externally controlled. An external terminal for outputting the expansion bit status to the outside is provided. [Function] According to the above means, way management can be performed using the LRU method inside the chip, and between chips, an expansion bit can be used to manage two cache memories alternately using a simple external circuit. This makes it possible to expand in the way direction using multiple cache memories. [Embodiment] FIG. 1 shows the configuration of essential parts of an embodiment in which the present invention is applied to a cache memory. Although not particularly limited, each circuit block surrounded by a dashed line A in the figure is implemented on one semiconductor chip such as a single crystal silicon substrate. The cache memory in the figure includes a directory memory 1, a data memory 2, and an LRU (Least Relay).
A memory array consisting of a block replacement control circuit 3 based on the ``Cently Used'' method, a tag comparator 4, a CPU interface 7, a system bus interface 8, etc. are formed, and the system bus to which the main memory is connected and the CPU bus are connected. connected between. In the directory memory 1, the upper ten or more bits of the address on the main memory of data stored in the same column position of the data memory 2 are stored as a tag.

When the column address portion of the address AD given by the CPU via the CPU interface 7 is supplied via the internal address bus 5a to the decoder 6 common to the directory memory 1, data memory 2, and LRU 3, each memory The address tag and data are read simultaneously from the same column. Among these, the address tag read from the directory memory 1 is supplied to the tag comparator 4. The tag comparator 4 is supplied with the tag part TAG of the address AD given from the CPU to the memory array, and compares it with the tag read from the directory memory l to find out if there is a match (cache hit) or a mismatch ( A signal CH indicating (mishit) is output. When a cache hit occurs, the data read from the corresponding column position of the data memory 2 is selected by the selector 9, output to the internal data path 5b, and supplied to the CPU via the CPU interface 7.

On the other hand, if a mishit occurs, the CPU bus and system bus are connected via the system bus interface 8, so that the CPU can directly access the main memory and obtain desired data.

FIG. 2 shows an example of the configuration of the LRU control circuit 3 shown in FIG. That is, the LRU control circuit 3 selects the 6 columns selected by the column address decoder 6.
It is composed of LRU register groups REG1 to REGn of bits. Each LRU register has 6 pits because
This is because the directory memory 1 and data memory 2 are configured in 4 ways. That is, as shown in FIG. 3, if each way is represented by symbols A, B, C, and D, and a flip-flop is associated with each pair of four ways, then
Six flip-flops are required. Assuming that the set and reset states of these flip-flops F1 to F6 correspond to the direction of the arrow between ways, and when the self is selected, all the flip-flops related to the self are set to "1", that is, the direction of the arrow If you point outward, the way with the most number of pointing arrows will represent the one that has not been selected for the longest time. There? It becomes possible to replace the LRU method. Each flip-flop F1 to F6 is a tag comparator 4, for example.
It is managed by simultaneously setting three blip-props corresponding to the way selected by the match detection signal. In this embodiment, the above 6-bit LRU register group REG
Extension bits F7 are added to each of (1) to REGn, and one of the extension bits F7 selected by the decoder 6 is connected to the external bin 10, and its status is output.

Furthermore, in the cache memory of this embodiment, an external pin OD is used to control writing to the expansion bit F7.
S is provided. In Figure 4. An example of the configuration of an external circuit is shown when the LRU control circuit 3 connects two cache memories configured as described above in parallel to expand the way.

In the figure, 11 is a NAND gate for monitoring the state of the expansion bit F7. 12a and 12b decode the address signal AD supplied from the microprocessor to the cache memory to generate chip select signals cs1,
cs, and the address decoder for forming the above NA
One of the address decoders is activated by the output signal of the ND gate 1l to generate a chip select signal. Therefore, the control terminal of the decoder 12b has a NAN
The output signal of the D gate 11 is applied as is, and a signal obtained by inverting the output signal of the NAND gate l1 by an inverter l3 is applied to the control terminal of the other decoder 12a. However, even if the chip select signal does not go to low level, the decoder 6 in the chip is configured to operate when an address is received and select the LRU register.

Next, way management in the above embodiment will be explained.

When an expansion system is constructed by connecting two cache memories C-MEM of the above embodiment to the microprocessor M'PU in parallel as shown in FIG. All bits F7 are set to "1", and all expansion bits in the other memory are reset to "O". For example, assume that the expansion bit in the memory C-MEM1 is set to "rl" and the expansion bit in the memory C-MEMZ is reset to "0". Then, the state of the expansion bit F7 of the column corresponding to the supplied address is output to the external pin 10, so the NAND gate 11 monitors this.
The output signal of address decoder 12 becomes high level.
Of a and 12b, 12a is activated.

Therefore, when the microprocessor accesses the cache memory address space, the chip select signal C
When SE is set to low level, cache memory C-ME
MI is selected and operations such as tag comparison and data reading begin. When a mishit occurs, the oldest way in the chip is selected based on the states of flip-flops F1 to F6 among the selected LRU registers in the LRU control circuit 3, and block replacement is executed.

Then, at the end of accessing the memory, the expansion bit F7 is
is changed from "1" to "O".

On the other hand, in the cache memory C-MEM2, the C-MEMI chip select signal CS1 is sent to the external bin ODS.
is input, it can be known that C-MEM1 has been accessed.

Then, since the address common to the memory C-MEMI is input, the address decoder 6 operates to select one register of the LRU control circuit 3, and when the access to the memory C-MEMI is completed, the expansion bit of the selected register is input. Change F7 from rQJ to "1".

As a result, the output signal of the NAND gate 11 changes from high level to low level, and the address decoder 12a
12b is activated instead, and memory C-MEM2 is selected. When a mishit occurs in the memory C-MEMZ, the oldest way is replaced. In this way, in the cache memory of this embodiment, one of the expansion bits F7 is inverted every time there is an access, and for example, when the same column position is accessed continuously, the cache memory C-MEM1 and C-MEM2 is accessed alternately. As a result, although incomplete,
The possibility that the older way will be selected between the cache memories C-MEM1 and C-MEM2 increases, and the hit rate improves compared to the case where only one cache memory is used.

Note that in the above embodiment, the state of the expansion bit is output to the outside of the chip, and the external circuit generates a signal to select one of the chips. First, an internal control circuit may refer to the expansion bits and replace one of the ways. Even in this case, the configuration is such that the expansion bits in the two memories are always set to different states, and the states are inverted every time they are accessed.

As explained above, in the above embodiment, in a set-associative cache memory, one expansion bit is added to each register that constitutes the LRU control circuit for specifying a block to be replaced in the event of a miss. At the same time, we have provided an external terminal for controlling the expansion bits from the outside and an external terminal for outputting the status of the expansion bits to the outside, so that way management using the LRU method can be performed inside the chip, and the chip In between, the expansion bit can be used to manage the alternate use of two cache memories with a simple external circuit, making it possible to expand in the way direction using multiple cache memories, reducing cache hits. This has the effect of increasing the throughput of the system. Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, two cache memories were connected in parallel to enable expansion in the way direction.
By providing two or more expansion bits in the RU register, it is also possible to expand in the way direction using three or more cache memories. In the above description, the invention made by the present inventor was mainly applied to a cache memory equipped with an LRU type replacement control circuit, which is the field of application that is the background of the invention, but this invention is not limited thereto. Dena<
It can also be used in cache memory equipped with a FIFO type replacement control circuit. [Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, it becomes possible to expand the cache in the way direction by connecting multiple set-associative cache memories, and as a result, the cache hit rate can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of main parts of a cache memory suitable for applying the present invention, FIG. 2 is a block diagram showing an example of the configuration of an LRU control circuit, and FIG. 3 is a block diagram showing an example of the configuration of an LRU control circuit. FIG. 4 is a conceptual diagram showing a method for determining the way replacement order by the LRU control circuit in the cache memory. FIG. 4 is a circuit configuration showing an example of the configuration of an external circuit when expanding using two cache memories of this embodiment. FIG. 5 is a system configuration diagram showing an example of the configuration of a microcomputer system using two cache memories.

Claims (1)

[Claims] 1. In a set-associative type buffer storage device, an expansion bit is provided in a register constituting replacement control means for specifying a block to be replaced in the event of a mishit. buffer storage device. 2. The buffer storage device according to claim 1, further comprising a terminal for outputting the state of the expansion bit to the outside. 3. The buffer storage device according to claim 2, further comprising an input terminal for a signal for controlling the state of the expansion bit.