JPH0330044A - Interruption control method - Google Patents

Abstract

PURPOSE:To connect I/Os by a common signal line, and also, to facilitate the removal of the I/O by using a common interruption request signal from plural I/Os, an interruption acknowledge signal from a CPU, a timing signal having a necessary time slot, and busy signal. CONSTITUTION:By receiving a timing signal 13 having a timing slot synchronizing with an interruption acknowledge signal 12 for showing an interruption cycle from a CPU, each I/O checks whether a common interruption request signal 11 exists in its own timing slot or not. Subsequently, when the signal 11 is not outputted, a busy signal 14 is made inactive. Other I/Os confirm a fact that the signal is inactive and detects a fact that an interruption cycle can be obtained by themselves and the signal 14 is made active, and for a period in which the signal 12 is active, this active state is held. According to this constitution, the I/Os are connected by a common signal line, and the I/O is removed easily without discontinuing the interruption acknowledge signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for handling interrupt requests from a plurality of I/Os by a CPU.
The present invention relates to an interrupt control method for notifying each I/O of an interrupt cycle.

[Prior Art] Two methods are conventionally known for notifying a CPU interrupt cycle in response to interrupt requests from a plurality of I/Os.

The first method is to output an interrupt request signal independently for each I/O, and output a hair acknowledge signal for each I/O in response to each interrupt request signal on the CPU side. This first method is shown in FIG.

I/O-1, I/O-2 and engineering/0-n shown in Figure 3
In response to interrupt request signals 1, 2, and 3 from the CPU, interrupt acknowledge signals 4, 5, and 6 are sent from the CPU to each corresponding I
Output to /O.

The second method of notifying CPU interrupt cycles in response to interrupt requests from multiple I/Os uses a common interrupt request signal for each I/O, and a single signal from the CPU side. This is a method of outputting an interrupt acknowledge signal, and each I/O is connected in a daisy chain. This second method is shown in FIG.

The first I/O from the CPU in response to interrupt request signal 7 from I/O-1, I/O-2 and I/O-n.
It outputs an interrupt acknowledge signal 8 to (here, I/O-1). If the I/O-1 does not send out an interrupt request signal, it outputs an interrupt acknowledge signal relay output 9 to the lower I/O-2.

If I/O-2 is outputting an interrupt request signal, I/O-
2 acquires the CPU interrupt cycle without outputting the interrupt acknowledge signal relay output 10 to the lower I/O-n.

In the second method shown in FIG.
Since the interrupt is interrupted at /O-1, means for relaying the interrupt acknowledge signal 8 to the interrupt acknowledge signal relay output 9 is required.

[Problems to be Solved by the Invention] The first method described above has the disadvantage that each I/O and the CPU side must be individually connected, making the wiring complicated.

In addition, in the second method, the interrupt acknowledge signals between each I/O are connected in a daisy chain.
There is a drawback that a means for relaying the interrupt acknowledge signal is required when /O is removed.

[Means for Solving the Problems] The present invention has been made in view of the above problems, and each
It is an object of the present invention to connect I/Os with a common signal, and to eliminate the need for special signal relay means even if I/Os in the middle are removed.

In order to achieve this objective, the interrupt control method according to the present invention uses a common interrupt request signal output from a plurality of I/Os, an interrupt acknowledge signal indicating a CPU interrupt cycle, and an interrupt control method. By using a timing signal that is synchronized with the acknowledge signal and has time slots assigned to the addresses of multiple I/Os, and a busy signal that indicates that a CPU interrupt cycle is being used, multiple I/O
It is configured to obtain an interrupt cycle by determining a busy signal in the time slot of the timing signal assigned to address O.

[Example code] Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a block circuit diagram showing an embodiment of the interrupt control method according to the present invention, and FIG. 2 is a timing chart illustrating the operation of the circuit shown in FIG. 1. In addition, as an explanation of the embodiment, a case where the I/O-2 issues an interrupt request will be exemplified.

When the I/O-2 requests an interrupt, the interrupt request signal 1
1 becomes active and is transmitted to the CPU. When the CPU receives an interrupt request, it sends an interrupt acknowledge signal 12.
is activated, and the interrupt acknowledge signal l2 is activated.
The timing signal 13 is outputted in synchronization with.

I/O-1 checks whether there is an interrupt request at time slot t1 of timing signal 13 corresponding to its own address. At this time, I/O-1 keeps the busy signal 14 inactive unless it outputs an interrupt request.

I/O-2 checks whether there is an interrupt request at time slot t2 of timing signal 13 corresponding to its own address. At this time, after confirming that the busy signal 14 is inactive and detecting that it can acquire an interrupt cycle, the busy signal 14 is activated. Thereafter, the busy signal 14 is held active while the interrupt acknowledge signal 12 is active.

The I/O-M checks whether there is an interrupt request at the time slot tn of the timing signal 13 corresponding to its own address, but since the busy signal 14 is already active at this time, the I/O-M does not accept the interrupt request. Even if you output the request,
Detects failure to obtain an interrupt cycle.

In this way, each I/O is connected by a common signal, and an interrupt cycle is acquired in the time slot corresponding to the address of each I/O, so that intermediate I/O
Even if O is removed, there is no need to use a special signal relay means.

[Effects of the Invention] As explained above, the present invention provides a common interrupt request signal output from a plurality of processors/0s, an interrupt acknowledge signal indicating a CPU interrupt cycle, and an interrupt acknowledge signal. By using a timing signal that has time slots that are synchronized to the address of the multiple I/Os and assigned to the addresses of the multiple I/Os, and a busy signal that indicates that a CPU interrupt cycle is being used, By configuring the system to obtain an interrupt cycle by determining a busy signal in the time slot of the timing signal assigned to the address, it is possible to connect each I/O with a common signal. Even if the intermediate I/O is removed, there is an effect that no special signal relay means is required.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing one embodiment of the interrupt control method according to the present invention, FIG. 2 is a timing chart explaining the operation of the circuit shown in FIG. 3, and FIG. 3 is a conventional interrupt control method. Block circuit diagram showing an example of a control method FIG. 4 is a block circuit diagram showing another example of a conventional interrupt control method. 11 12 Engineering 3 1 4 Interrupt request signal Interrupt acknowledge signal Timing signal Busy signal

Claims (1)

[Scope of Claims] A common interrupt request signal output from a plurality of I/Os; an interrupt acknowledge signal indicating an interrupt cycle of a CPU;
By using a timing signal having a time slot assigned to the /O address and a busy signal indicating that a CPU interrupt cycle is being used, the timing assigned to the plurality of I/O addresses is determined. An interrupt control method characterized in that an interrupt cycle is obtained by determining the busy signal in a signal time slot.