JPH0330183A - Memory control system - Google Patents

Abstract

PURPOSE:To improve the probability of page hit by dividing a memory into blocks of a multiple of a data bus width of a CPU and enabling an output data bus alternatively in a block at page mode access. CONSTITUTION:A memory 2 is divided into plural blocks equal to a data bus width of a CPU 1, each memory output data bus of the blocks is in wired-logic connection and the memory output data bus of each block is enabled alternatively at page mode access. Thus, since the memory data bus width is expanded to a multiple of 2<m> of the physical data bus width of the CPU 1 to expand the size of one page to 2<m> similarly, the probability of page hit is improved.

Description

TECHNICAL FIELD The present invention relates to a memory control system, and more particularly to a high-speed access control system for a random access memory capable of operating in a page mode.

BACKGROUND OF THE INVENTION A page mode access method is one of the high-speed access methods for conventional DRAMs (dynamic random access memories).

In a DRAM, address information for one memory consists of a page number specified by a row address and an intra-page address specified by a column address. In the page mode, if a page is specified by giving a row address to the DRAM, only a column address can be specified for subsequent accesses within the same page until the page is changed.

Therefore, compared to a method in which a row address is specified for each access, faster access is possible.

In this type of conventional memory control system, the physical data bus width of the CPU and the data bus width of the memory are designed to be equal even if page mode access as described above is employed. Therefore, the size of one page in the page mode of the DRAM being used is uniquely determined by the DRAM being used. In this case, the page size y is y-2' if the number of bits in the column address is X, and is unique.

In this way, in the conventional memory access control method, the CPU
Since the data bus width of the DRAM is equal to the data bus width of the DRAM, the page size is uniquely determined, and depending on the program being run, accesses across pages may occur frequently, resulting in page hits (within the same page). The disadvantage is that the characteristics of the page mode, which enables high-speed access, are not fully utilized in the case of (access), and the performance of the system is not fully utilized.

OBJECTS OF THE INVENTION An object of the present invention is to increase the probability of a page hit by making the memory data bus width larger than the CPU data bus width and making the size of one page substantially that much larger. The object of the present invention is to provide a memory control method that takes advantage of the high speed performance of DRAM in page mode and improves system performance.

According to the present invention, there is provided a control method for a memory that can be accessed in page mode, wherein the memory is divided into a plurality of blocks each having a data bus width equal to the data bus width of a CPU; each memory output data bus of the same block is configured by wired logic connection, and the wired logic output is connected to the data bus of the CPU, and the memory output data bus of the block is selectively enabled during the page mode access. A memory di{J1 system is obtained which is characterized by the following.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention.

In the figure, the CPUI has, for example, a 16-bit data bus, and is connected to a memory 2 having a bus width twice the data bus width.

This memory 2 is composed of two memory blocks 21 and 22, each having a data bus width of 16 bits, and each data bus of the two memory blocks is connected by wired logic, so that it can match the data bus width of the CPUI. The lines are concentrated so that they are equal. This concentrated line output is connected to the data bus of the CPUI.

The memory control circuit 3 receives an access address from the CPUI via the address bus, performs conversion processing to make the address suitable for the memory 2, and supplies the converted address to the memory 2. Furthermore, the memory control circuit 3 determines from the address from the CPUI whether or not this address is within the same page as the address accessed immediately before (page hit or miss), and indicates this by indicating the line a. Notify the CPUI via the CPU.

Furthermore, the memory control circuit 3 has a function of driving lines b and c, respectively, based on addresses from the CPUI, and controlling which part of the page is accessed. That is, it selects which block among the blocks 21 and 22 in the memory 2 is to be enabled for its output.

FIG. 2 is a concrete block diagram of this memory control circuit 3. The page hit detection circuit 32 receives the address from the CPU 1 and detects whether the previous access address and the current access address are in the same page. If they are the same, it is a page hit, otherwise it is a page miss hit, and this hit. l depending on the miss hit? The AS/CAS generation circuit 33 is driven.

The RAS/CAS generation circuit 33 outputs a RAS signal (row address strobe signal) and a CAS signal (column address strobe signal), and if there is a page hit, the RAS signal remains active and CA is generated.
Make the S signal active.

The operation of the RAS/CAS generation circuit 33 determines whether to supply both the row address and column address or only the column address to the memory 2, and the operation of the multiplexer 31 is controlled.

On the other hand, the output of the page hit detection circuit 32 is inputted to the wait control circuit 35, and in the case of page miss hit 1, the necessary and sufficient time is ensured to supply both the row address and the column address to the memory 2. CPU should be
A wait signal a is derived to instruct I not to proceed to the next cycle.

The OE decoding circuit 34 receives an address from the CPUI and instructs signal lines b and c from which of the two memory blocks 21 and 22 output data is to be enabled.

FIG. 3 is a timing chart of signals of various parts showing an example of the operation of the memory control circuit of FIG. In the figure, it is assumed that a low level is active and a high level is inactive. For example, signal lines b and c are logic “0”
, it indicates that data can be output to the data bus, and when the RAS signal and CAS signal are logic "0", it indicates that the strobe is on. Note that when the wait signal line a is at logic "0", it indicates to the CPU that it is OK to proceed to the next cycle.

When an address is supplied from the CPU 1, a page hit is detected in the page hit detection circuit 32, and if it is a page hit, that is, an access within the same page, the CP
A wait signal a (low level) is generated from the circuit 35 for U1, and the wait signal a (low level) is notified to the CPU 1 that it is OK to proceed to the next cycle.On the other hand, in the case of a page miss, the wait signal Set a to high level (inactive) and use the CPU to perform weight control.

Further, in parallel with the above operation, a control signal is generated from the OE decoding circuit 34 to the signal lines b and c to determine which output of the two memory blocks is to be valid.

In the example shown in Figure 3, the first half shows a page hit mode in which three consecutive addresses access the same page, and correspondingly, the wait signal a becomes active for each of the three consecutive addresses. The first time is memory block 22
There is a page hit for the memory block 2], and a page hit for the second and third memory block 2 is shown.

Therefore, corresponding to the first time, the signal line C that activates the output of the memory block 22 is activated, and corresponding to the second and third times, the signal line b that activates the output of the memory block 21 is activated. will be made into

As can be seen from the above, when viewed from the CPUI, the number of pages opened simultaneously in page mode is two, memory blocks 21 and 22, and when viewed as a whole,
This is equivalent to the page size being multiplied by the number of memory blocks.

The number of memory blocks can generally be 2a (m
(1, 2, 3, ...), the page size y has apparently increased to 2''' Gender is brought to life.

Effects of the Invention As explained above, according to the present invention, the memory data bus width can be expanded to 2'' times the physical data bus width of the CPU, and the size of one page can be expanded to 26 times. This has the effect of improving the probability of a hit and making use of the high speed of the page mode of DRAM.

[Brief explanation of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention, FIG. 2 is a concrete block diagram of the memory control circuit of FIG. 1, and FIG. 3 is a timing chart showing the operation of the memory control circuit. Explanation of symbols of main parts 1...CPU 2...DRAM 3...Memory control circuit 21.22...Memory block 31...
・Multiplexer 32...Page hit detection circuit 33...
・RAS/CAS generation circuit 34... OE decoding circuit 35... Weight control circuit output person LI Hon Electric Co., Ltd.

Claims (1)

[Claims] (1) A control method for a memory that can be accessed in page mode, in which the memory is divided into a plurality of blocks each having a data bus width equal to the data bus width of the CPU, and each memory output data of these blocks is Connect the bus with wired logic and send this wired logic output to the C
A memory control system, characterized in that the memory control system is configured to be connected to a data bus of a PU, and selectively enables a memory output data bus of the block during the page mode access.