JPH07281992A - Dma controller - Google Patents

Abstract

PURPOSE:To provide the DMA controller which can more accelerate data transfer speed by simultaneously executing both continuous access and simultaneous read/write execution. CONSTITUTION:According to a data transfer starting instruction from a CPU 30, a timing signal generator 23 latches a row address by using latches 213 and 223 and afterwards, MUs 212 and 222 are switched to the side to output a column address. The timing signal generator 24 lets an output CAS signal fall and outputs data from a transfer source DRAM. A CAS signal delayed for prescribed time by a delayer 25 is inputted through a switcher 26 to a transfer destination DRAM and with the fall of that CAS signal, the data are written. Since the CAS signal is repeatedly turned to L and H levels while holding a RAS signal at the L level, page mode access is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller, and more particularly to a DMA controller which transfers data between a plurality of dynamic random access memories (DRAMs) at high speed by hardware without passing through a microprocessor.

[0002]

2. Description of the Related Art Between a plurality of DRAMs or DRAMs
Direct data transfer between the I / O port and the I / O port by hardware, not through a microprocessor
In recent years, a DMA controller (DMAC) that realizes a memory access (DMA) transfer has been required to have a higher DMA transfer speed. Therefore, D
A DMAC that realizes continuous access using the page mode or static column mode of RAM is known (for example, Japanese Patent Laid-Open Nos. 4-199450 and 3-223948).

FIG. 7 is a block diagram showing an example of a conventional DMAC disclosed in Japanese Patent Laid-Open No. 4-199450. As shown in the figure, the DMAC includes a first storage unit 2, a reading unit 3, a second storage unit 5, a writing unit 6, and a reading unit 3 which are connected to a central processing unit (CPU) bus 1. The register file 4 is connected between the plug-in means 6.

In this conventional DMAC, in response to a data transfer request from a CPU or the like, the CPU releases the CPU bus 1 and the reading means 3 stores the data to be transferred stored in the first storage means 2. Read N words,
This is stored in the register file 4. The writing unit 6 stores the data for one page stored in the register file 4 in the second storage unit 5.

That is, according to this conventional DMAC,
When the first and second storage means 2 and 5 are DRAMs, the page mode or static column mode of the DRAM is used, the row address is fixed, and the column address is changed to change the first storage means 2 from the first storage means 2. Read one page continuously and write to register file 4,
Since the row address of the data for one page written thereafter is fixed and the column address is changed and continuously written in the second storage means 5, the row address of 1
Data for one page can be transferred only by specifying the number of times, and thus DMA transfer can be speeded up.

Further, according to the conventional configuration shown in FIG.
A DMAC that realizes cycle-based data transfer is also known (JP-A-3-204753). In the figure, when data is transferred from the memory 13 to the memory 15, an address signal indicating the transfer source is output from the DMA controller 11 to the memory 13 via the address bus 12, and an address signal indicating the transfer destination is output. It is output to the memory 15 via the address bus 14.

When the read signal supplied from the DMA controller 11 to the memory 13 via the signal line 16 becomes active, the stored contents of the memory 13 are read out to the data bus 17, and at the same time, the DMA controller 1
Since the write signal supplied from 1 to the memory 15 via the signal line 18 becomes active, the data read to the data bus 17 is written in the memory 15. In this way, the data transfer from the memory 13 to the memory 15 is completed in one cycle.

[0008]

However, the above-mentioned FIG.
The conventional DMA controller shown in FIG. 8 is intended for speeding up data transfer by continuous access, and the conventional DMA controller shown in FIG. 8 is high speed for data transfer in one cycle by simultaneous execution of read and write. However, the speed of these is insufficient.

The present invention has been made in view of the above points,
An object of the present invention is to provide a DMA controller capable of further increasing the data transfer rate by simultaneously executing both continuous access and simultaneous reading and writing.

[0010]

In order to achieve the above-mentioned object, the present invention provides a first memory control unit for generating and outputting an address signal for a continuously accessible first memory of a transfer source, and a continuous memory of a transfer destination. A second memory controller for generating and outputting an address signal for the accessible second memory;
First and second address strobe signals are generated based on the output control signals of the first and second memory control units, and the first address strobe signals are output to the first and second memories, respectively. The second address strobe signal is delayed by a timing signal generator for outputting to the first memory, and the second address strobe signal is delayed by a time obtained by adding the access time of the first memory and the data setup time of the second memory. A delay device supplied to the second memory and a control signal for controlling the generation operation of the first and second address strobe signals so as to independently and continuously access the first and second memories, respectively. A structure having first and second control means respectively provided in the first and second memory control units for separately outputting to the first and second timing signal generators. It is obtained by the.

Further, according to the present invention, of the two memories, the first memory which is the transfer source is read out and the second memory which is the transfer destination is write-controlled, and the output of the transfer direction control means. A switch for switching between supplying the output second address strobe signal of the timing signal generator to the first memory and supplying the output address strobe signal of the delay unit to the second memory based on the signal. It is preferable to further have the following because the data transfer direction between the two memories can be switched and set according to an instruction from the host device.

Further, in the present invention, one or both of the first and second memories is a dynamic random access memory capable of operating in a page mode or a static column mode. The first and second control means output the output address signals of the first and second address generators at the transition of the output first address strobe signal of the timing signal generator at the start of data transfer to the active state, respectively. It comprises a latch for holding the row address, and a comparator for comparing whether or not the output of the latch and the row address of the output address signals of the first and second address generators match. While outputting the coincidence signal, the timing signal generator keeps the first address signal active and keeps the second address signal active. It is preferred in that it is continuous access to control to repeat less strobe signal the status of the active and inactive alternately.

[0013]

In the present invention, the data output from the first memory in synchronization with the second address strobe signal from the timing signal generator is synchronized with the second address strobe signal delayed by the delay device. Then, the first memory and the second memory are continuously accessed, and at the same time, the data read from the first memory and the data write to the second memory are repeated for one cycle. Can be done at.

[0014]

EXAMPLES Next, examples of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, the DMAC 20 is composed of a first DRAM controller 21, a second DRAM controller 22, a transfer direction controller 23, a timing signal generator 24, a delay device 25, a switch 26 and an inverter 27. Central processing unit (CPU) 3
It is initialized by 0, and data transfer is controlled by using one of the DRAMs 31 and 32 as a data transfer source and the other as a data transfer destination.

The DRAM controller 21 in the DMAC 20 is
The DRA is composed of an address generator 211, a combiner (MUX) 212, a latch 213, and a comparator 214.
The M control unit 22 includes an address generator 221 and a combiner (MU).
X) 222, a latch 223, and a comparator 224. The DRAM control unit 21 is connected to the address terminal of the DRAM 31, and the DRAM control unit 22 is connected to the DRAM 32.
Connected to the address terminal of.

The address generators 211 and 221 output the addresses of the transfer data of the transfer source and transfer destination DRAMs. The start address and end address of the transfer data or the number of transfer data is initialized by the CPU 30. The timing signal generator 24 updates the transfer addresses from the address generators 211 and 221 during DMA execution.
By a CAS (column address strobe) signal. Further, the address generators 211 and 221 separately output the transfer address as a row address (row address) and a column address (column address), and
Information on whether the transfer is completed is output to the timing signal generator 24.

The MUXs 212 and 222 combine the row address and the column address output from the address generators 211 and 221. The latches 213 and 223 output the row address output from the address generators 211 and 221 to the output RAS (row address
Latch at the falling edge of the strobe signal. Comparator 2
14 and 224 compare the row address output from the address generators 211 and 221 with the row address output from the latches 213 and 223, and determine whether the comparison result matches the timing signal generator 24. Output as information.

The transfer direction controller 23 includes DRAMs 31 and 3
A circuit for controlling the data transfer direction between two CPUs 30
Set by. The timing signal generator 24 uses the DR
Based on the outputs of the comparators 214 and 224 in the AM control units 21 and 22 and the outputs of the address generators 211 and 221,
A switching timing signal between the row address and column address of the DRAMs 31, 32 is supplied to the MUXs 212, 222, and the DRAMs 31, 32 and the latch 21 are supplied.
3 and 223, RAS signal is supplied, and D
The CAS signal is supplied to the RAMs 31 and 32 and the address generators 211 and 221.

The delay device 25 delays the output CAS signal of the timing signal generator 24 by the sum of the access time of the transfer source DRAM and the data setup time of the transfer destination DRAM of the DRAMs 31 and 32. The switching device 26 outputs the CAS signal output from the timing signal generator 24 and the delay device 2.
One of the 5 output CAS signals is selected based on the control signal from the transfer direction controller 23. Furthermore, the inverter 27
Inverts the output control signal of the transfer direction controller 23 to DRA
Input to the write terminal of M32.

In this embodiment having the above structure, the DRAM
In this embodiment, 31 and 32 are memory circuits that support the page mode. This page mode itself is generally known. FIG. 3 shows a timing chart of a read cycle in this page mode, and FIG. 4 shows a timing chart of a write cycle in the page mode.

That is, during the page mode read cycle, the CAS signal is once made inactive (H level) while the RAS signal is kept active (L level) as shown in FIG. Address), the write enable signal W is deactivated, and the CAS signal is alternately activated (L level) and deactivated to alternately input column addresses (column addresses) of the same row and output. The stored data corresponding to is read. In FIG. 3, OE
The bar indicates the output enable signal.

On the other hand, during the page mode write cycle (early write), the CAS signal is once made inactive and the row address is input again while keeping the RAS signal active as shown in FIG. The write enable signal W is made active (L level) before being made active, and the CAS signal is alternately made active and inactive to alternately input column addresses in the same row, and input data DQ1 to
Write DQ4 one after another. At this time, the output enable signal OE may be active or inactive.

Next, the operation of this embodiment will be described with reference to FIG. First, before starting data transfer, the CPU 3
The data transfer direction between the DRAMs 31 and 32 is set to the transfer direction controller 23 by 0, and the transfer start address and the transfer end address or the number of transfer data are set to the address generators 211 and 221. .
When data is transferred from the DRAM 31 to the DRAM 32, the CPU 30 controls the output signal of the transfer direction controller 23 to be H level.

The output signal of the transfer direction controller 23 is a DRAM.
When the output signal of the transfer direction controller 23 is at the H level, the DRAM 31 is read-controlled so that it becomes the transfer source DRAM. At this time, the output signal of the transfer direction controller 23 is Inverter 2
Since it is inverted to L level by 7 and supplied to the write control terminal of the DRAM 32, since the DRAM 32 is write-controlled, the DRAM 32 becomes the transfer destination DRAM.
When the output signal of the transfer direction controller 23 is at L level, the transfer direction is opposite to the above.

Next, the CPU 30 instructs the timing signal generator 24 to start data transfer. The timing signal generator 24 follows the data transfer start instruction from the CPU 30 so that the row address is output first.
Switch 12 and 222. Subsequently, the timing signal generator 24 causes the output RAS signal to fall at time t1 as shown in FIG.
After the above row address is latched by 3, the MU
X212 and 222 are switched to the side where the column address is output.

Next, the timing signal generator 24 outputs the output C.
The AS signal falls at time t2. This CAS signal is D
Since the data is directly input to the transfer source DRAM of the RAMs 31 and 32 via the switch 26, data is output from the transfer source DRAM at the fall of the CAS signal. FIG. 2B shows this CAS signal at time t2.
T3 when the access time has elapsed from the fall of
To output valid data as shown in FIG.

On the other hand, since the CAS signal delayed by the delay device 25 for a predetermined time is input to the transfer destination DRAM of the DRAMs 31 and 32 through the switch 26, the transfer destination is caused by the fall of the delayed CAS signal. The data output from the transfer source DRAM is written in the DRAM. This delayed CAS signal is shown in FIG. 2 (C). Due to the delay caused by the delay device 25, the transfer destination DRAM has the time t.
3. Write the valid data immediately after. FIG. 2F shows the data input to this transfer destination DRAM.

The timing signal generator 24 is shown in FIG. 2B after the delayed CAS signal shown in FIG. 2C has fallen and a time sufficient for writing data to the transfer destination DRAM has elapsed. As described above, the output CAS signal is raised.
At this point, the address generators 211 and 221 have the CPU 3
When the transfer end address or the transfer data number set to 0 has been reached, the timing signal generator 24
A signal is raised to end the continuous access between the DRAMs 31 and 32.

However, when the address generators 211 and 221 do not reach the transfer end address or the number of transfer data set in the CPU 30 at the time of the rise of the CAS signal, the address generator 2 rises at the rise of the CAS signal.
11 and 221 update the address supplied to the address terminals of the DRAMs 31 and 32. When each of the post-address update comparators 214 and 224 outputs a row address coincidence detection signal, the timing signal generator 24 causes the output CAS signal to fall, and the next data transfer is executed in the same manner as described above. FIG. 2D shows addresses input to the DRAMs 31 and 32 via the MUXs 212 and 222, respectively.

In this way, the page mode access is performed by repeating the CAS signal at the L level and the H level while keeping the RAS signal at the L level, after the address updating of the address generators 211 and 221 is performed.
The output of the comparator 214 or the comparator 224 indicates a mismatch,
Alternatively, the address generator 211 or the address generator 2
This is repeated until 21 reaches the transfer end address or the number of transfer data.

When the output of either the comparator 214 or the comparator 224 indicates a mismatch, the timing signal generator 2
4 raises the RAS signal, interrupts the continuous access to the DRAMs 31 and 32, and repeats the above operation from the point where the outputs of the MUXs 212 and 222 are switched to the row address in the same manner as when receiving the transfer start instruction from the CPU 30.

As described above, according to this embodiment, the DRAM
Since continuous access in 31 and 32 page modes, reading from the transfer source DRAM, and writing to the transfer destination DRAM are performed simultaneously in one cycle, the transfer time is shortened and speeded up by continuous access, and two DRAMs are used.
Due to the synergistic effect of shortening and speeding up the transfer time by reading and writing data in one cycle, it is possible to realize data transfer at a significantly higher speed than in the past.

The present invention is not limited to the above embodiment, and for example, one or both of the DRAMs 31 and 32 may be a memory circuit supporting the static column mode. During the read cycle in the static column mode, as shown in FIG. 5, after the RAS signal is activated, the chip select (CS) signal corresponding to the CAS signal is alternately activated and deactivated. , The different column addresses of the same row are sequentially specified to access continuously, and the write enable signal W is made inactive to sequentially read the storage data from the output terminal Q.

In the write cycle of the static column mode, as shown in FIG. 6, after the RAS signal is activated, the write enable signal W is activated before the CS signal is activated, and then the CS signal is activated. By alternately repeating the inactive state and the inactive state, different column addresses of the same row are sequentially specified and continuously accessed, and the input data is sequentially written. At this time, the output terminal Q of the DRAM is kept in a high impedance state.

Further, one of the DRAMs 31 and 32 can also use a register or the like configured to interface with a DRAM capable of page mode or static column mode (these are collectively referred to as a memory in the present invention). Is. Furthermore, when used for DMA transfer between two memories whose transfer directions are uniquely determined, the transfer direction controller 23 and the switch 26 need not be provided.

[0036]

As described above, according to the present invention,
Continuously accessing the first and second memories by using the page mode or the static column mode, and at the same time, reading data from the first memory and writing data to the second memory can be performed in one cycle. Therefore, by the synergistic effect of shortening and speeding up the data transfer time of both, DMA transfer between the two memories can be significantly shortened and speeded up as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is a timing chart for explaining an operation of a page mode read cycle.

FIG. 4 is a timing chart for explaining the operation of a page mode write cycle.

FIG. 5 is a timing chart for explaining the operation of a static column mode read cycle.

FIG. 6 is a timing chart for explaining the operation of a static column mode write cycle.

FIG. 7 is a configuration diagram of a conventional example.

FIG. 8 is a configuration diagram of another conventional example.

[Explanation of symbols]

20 DMA controller (DMAC) 21, 22 DRAM control unit 23 Transfer direction controller 24 Timing signal generator 25 Delay device 26 Switcher 27 Inverter 30 Central processing unit (CPU) 31, 32 Dynamic random access memory (DRAM) 211, 221 Address generator 212, 222 Combiner (MUX) 213, 223 Latch 214, 224 Comparator

Claims (4)

[Claims] 1. A first memory control unit for generating and outputting an address signal for a first memory of a transfer source that can be continuously accessed, and a first memory control unit for generating and outputting an address signal for a second memory of a transfer destination that is continuously accessible. Two memory control units, and first and second address strobe signals are respectively generated based on output control signals of the first and second memory control units, and the first address strobe signal is the first and second address strobe signals. A timing signal generator that outputs the second address strobe signal to the first memory, and outputs the second address strobe signal to the first memory; and a second address strobe signal for the access time of the first memory and the first memory. And a delayer for supplying the second memory with a time delay obtained by adding the data setup time of the second memory, and the first and second memories, respectively. As stand to be continuous access, the control signal for controlling the operation of generating said first and second address strobe signal first
And a first timing controller provided in the first and second memory control units, respectively for separately outputting to the first and second timing signal generators.
And second control means, wherein the data output from the first memory in synchronization with the second address strobe signal from the timing signal generator is delayed by the second delay device. The DMA controller is characterized in that writing to the second memory is repeated in synchronization with the address strobe signal of. 2. A transfer direction control means for controlling a read operation of a first memory which is a transfer source of the two memories and a write control of a second memory which is a transfer destination, and an output signal of the transfer direction control means. Based on the above, a switch for switching the output second address strobe signal of the timing signal generator to the first memory and the output address strobe signal of the delay unit to the second memory The DM according to claim 1, further comprising:
A controller. 3. The first and second memories are dynamic random access memories capable of operating in a page mode, respectively, and the first and second control means are respectively the ones at the start of data transfer. The output of the timing signal generator outputs the first address strobe signal when the first address strobe signal transitions to the active state.
And a latch for holding a row address of the output address signals of the second address generator, and an output of the latch and a row address of the output address signals of the first and second address generators. A comparator for matching or comparing, and while the comparator is outputting a match signal, the timing signal generator keeps the first address signal active and the second address strobe signal 3. The DMA controller according to claim 1, wherein the DMA controller is controlled so as to alternately repeat an active state and an inactive state. 4. The DMA controller according to claim 3, wherein one or both of the first and second memories is a dynamic random access memory operable in a static column mode.