JPH033052U - - Google Patents
Info
- Publication number
- JPH033052U JPH033052U JP6097589U JP6097589U JPH033052U JP H033052 U JPH033052 U JP H033052U JP 6097589 U JP6097589 U JP 6097589U JP 6097589 U JP6097589 U JP 6097589U JP H033052 U JPH033052 U JP H033052U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- address
- package
- cpu
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013256 coordination polymer Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 1
Description
第１図は混在メモリパツケージの機能ブロツク
図、第２図はメモリ有効エリア指定を示す図、第
３図は本案の一実施例であるＰＬＡ内の論理式を
示す図、第４図、第５図はＰＬＡに入力する各条
件の成立条件を示す図である。
１……アドレスバツフア、２……メモリチツプ
セレクタ、３……コントロール回路、４……コン
トロールバツフア、５……アドレスＳＷ、６……
ＲＯＭ、７……ＲＡＭ。
Fig. 1 is a functional block diagram of a mixed memory package, Fig. 2 is a drawing showing memory effective area specification, Fig. 3 is a drawing showing logical expressions in PLA which is an embodiment of the present proposal, Figs. The figure is a diagram showing conditions for establishing each condition input to the PLA. 1... Address buffer, 2... Memory chip selector, 3... Control circuit, 4... Control buffer, 5... Address SW, 6...
ROM, 7...RAM.
Claims (1)
ダとアドレスを選択するアドレススイツチとＣＰ
Ｕとの間でデータをやりとりするデータバツフア
とパツケージの制御を行う制御回路とメモリチツ
プより成るメモリパツケージにおいて、ＣＰＵか
らの指定アドレスに従いメモリチツプ信号を作る
チツプセレクタを設けアドレススイツチに対応し
て重複する主記憶空間を複数のメモリ空間に分割
し異なる種類のメモリを同一パツケージ内に混在
させることを可能とするメモリ空間設定回路。 An address decoder that receives addresses from the CPU, an address switch that selects addresses, and a CP
In a memory package consisting of a data buffer that exchanges data with the U, a control circuit that controls the package, and a memory chip, a chip selector that generates a memory chip signal according to a specified address from the CPU is provided, and a duplicate main memory is provided corresponding to the address switch. A memory space setting circuit that divides space into multiple memory spaces and allows different types of memory to coexist in the same package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6097589U JPH033052U (en) | 1989-05-29 | 1989-05-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6097589U JPH033052U (en) | 1989-05-29 | 1989-05-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH033052U true JPH033052U (en) | 1991-01-14 |
Family
ID=31588816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6097589U Pending JPH033052U (en) | 1989-05-29 | 1989-05-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH033052U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62200477U (en) * | 1986-06-11 | 1987-12-21 |
-
1989
- 1989-05-29 JP JP6097589U patent/JPH033052U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62200477U (en) * | 1986-06-11 | 1987-12-21 |