JPH0330889B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a clock signal frequency divider circuit.

[Conventional technology]

Conventionally, a method of generating a differential pulse signal using a frequency dividing circuit is generally to simply divide the frequency of a basic clock signal 6 using a D-flip-flop, as shown in FIG. The logic circuit 1 is operated by the frequency-divided clock signal 7 for operating the logic circuit, and the input signal 5 is synchronized with the basic clock signal 6.
In order to synchronize the input signal 5 with the clock signal 7 for operating the logic circuit, it is necessary to synchronize the input signal 5, which is asynchronous with the clock signal 7, using a synchronization circuit such as the D-flip-flops 3 and 4. It was hot.

[Problem that the invention seeks to solve]

However, in the above method, the input signal 5 synchronized with the clock signal 6 is converted into a signal 8 synchronized with the clock signal 7 for logic circuit operation by the synchronization circuits 3 and 4.
There is a time delay before the data is input to the logic circuit 1, which slows down the operation time. As an example, a logic circuit 1 operated by a clock signal 7 for logic circuit operation includes a circuit that starts a certain operation when an input signal 5 synchronized with a basic clock signal 6 is input. In addition, when the input signal 5 needs to be synchronized with the clock signal 7 for operating the logic circuit, in conventional circuits of this type, the input signal 5 is synchronized with the clock signal 7 for operating the logic circuit. 8 to the logic circuit 1, the start of the operation is delayed by the time of the delay 20, as shown in FIG. 7, resulting in a disadvantage that the operation time is delayed.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a clock signal frequency divider circuit with minimal operation time delay.

[Means for solving problems]

According to the present invention, there is provided a clock signal frequency dividing circuit characterized in that the clock signal frequency-divided by the frequency dividing circuit is synchronized with an input signal.

In other words, the clock signal frequency dividing circuit of the present invention includes a frequency dividing circuit that divides the frequency of a basic clock signal to generate a clock signal for logic circuit operation, and a differential pulse of an input signal synchronized with this basic clock signal. By controlling the change point of the clock signal for logic circuit operation, which is the output of the frequency divider circuit, by using a differentiator circuit that generates a signal and this differential pulse control, the clock signal for logic circuit operation can be changed to the basic clock signal for logic circuit operation. and means for synchronizing with an input signal synchronized with a clock signal.

[Embodiments of the invention]

Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

1 and 2 showing the first embodiment of the present invention.
In the figure, the basic clock signal 6 is J-
The frequency is divided by the K flip-flop 9 and inputted to the logic circuit 1 as a clock signal 7 for operating the logic circuit. On the other hand, an input signal 10 synchronized with the basic clock signal 6 is input to the D-flip-flop 1.
1 and is input to logic circuit 1 with a delay of one clock. At the same time, a differential pulse signal 13 of the input signal 10 is generated by the NAND gate 12 and
-K is input to the J terminal of flip-flop 9.
Further, the K terminal of the JK flip-flop 9 is fixed at the logic "1" level.

Now, when an input signal 10 synchronized with the basic clock signal 6 is detected inside the logic circuit 1 at the rising edge of the logic circuit operation clock signal 7, the input signal 10 is as shown in FIG. Since the input signal 10 changes at both the rising edge and the falling edge of the clock signal 7 for operating the logic circuit, the input signal 10 is considered to be asynchronous with the clock signal 7 for operating the logic circuit. 1 cannot be entered directly. Therefore, when a differential pulse signal 13 of the input signal 10 is generated by the NAND gate 12 and the differential pulse signal 13 is input to the J terminal of the J-K flip-flop 9, which is a clock signal frequency dividing circuit, the input signal 10 operates as a logic circuit. If the change occurs at the falling edge of the clock signal 7 for logic circuit operation, the waveform becomes one in which the rising edge of the clock signal 7 for logic circuit operation is delayed by one cycle of the basic clock signal 6. In addition, the input signal 10
When the clock signal 7 for logic circuit operation changes at the rising edge of the logic circuit operation clock signal 7, the logic circuit operation clock signal 7 is output without any modification, and as a result, the signal 14 input to the logic circuit 1 becomes: Operationally, it is synchronized with the clock signal 7 for operating the logic circuit, and is always detected within the logic circuit 1 at the rising edge of the clock signal 7 for operating the logic circuit.

Therefore, compared to the system in which the input signal 10 is synchronized with the clock signal 7 for logic circuit operation and inputted to the logic circuit 1, the operating time is certainly shortened.

Referring to FIGS. 3 and 4, the second embodiment of the present invention is an example in which an input signal is detected at the falling edge of a clock signal for logic circuit operation, and is synchronized with the basic clock signal 6. input signal 15
The differential pulse signal 18 is input to the K terminal of the JK flip-flop 9, while the J terminal of the JK flip-flop 9 is fixed at the logic "1" level. Therefore, if the input signal 15 synchronized with the basic clock signal 6 changes at the rising edge of the clock signal 7 for operating the logic circuit, the rising edge of the clock signal 7 for operating the logic circuit becomes the basic clock. The waveform is delayed by one cycle of signal 6. Furthermore, when the input signal 15 changes at the falling edge of the clock signal 7 for operating the logic circuit, the clock signal 7 for operating the logic circuit is output without any modification, and as a result, the input signal 7 to the logic circuit 1 is output. The signal 19 to be output is synchronized with the clock signal 7 for logic circuit operation, and is synchronized to the logic circuit 1.
Internally, it is always detected at the falling edge of the clock signal 7 for logic circuit operation.

Therefore, compared to the system in which the input signal 15 is input to the logic circuit 1 in synchronization with the logic circuit operating clock signal 7, the operating time is certainly shortened.

Referring to FIG. 5, the third embodiment of the present invention is an example realized by combining the features of the first embodiment and the second embodiment. Since the operation is the same as in the first embodiment and the second embodiment, the explanation will be omitted.

〔Effect of the invention〕

As explained above, the present invention synchronizes the frequency-divided clock signal with the input signal.
This has the effect of shortening the operating time of the circuit.

[Brief explanation of drawings]

1 and 2 are views showing a first embodiment of the present invention, FIGS. 3 and 4 are views showing a second embodiment of the present invention, and FIG. 5 is a view showing a third embodiment of the present invention. The figures showing the embodiments, FIGS. 6 and 7, are diagrams showing conventional frequency dividing circuits. 1...Logic circuit, 2, 3, 4, 11, 16...D
- flip-flops, 5, 10, 15...input signals synchronized with the basic clock signal 6, 6...
Basic clock signal, 7... Clock signal for logic circuit operation, 8... Signal synchronized with clock signal 7 for logic circuit operation, 9... J-K flip-flop, 12, 17... NAND gate, 13 ，
18... Differential pulse signal.

Claims (1)

[Claims] 1. A frequency dividing circuit that divides the frequency of a basic clock signal to generate a clock signal for logic circuit operation, and a differentiating circuit that generates a differentiated path signal of an input signal synchronized with the basic clock signal. means for synchronizing the clock signal for operating the logic circuit with the basic clock signal by controlling the change point of the clock signal for operating the logic circuit, which is the output of the frequency dividing circuit, using the differential pulse signal; A clock signal frequency dividing circuit comprising: