JPH0330899B2 - - Google Patents

Description

Detailed Description of the Invention <Technical Field> The present invention relates to an electronic device including a CPU, a memory device, and an auxiliary storage device.

<Prior art> An direct memory access system that directly transfers data between a main storage device (hereinafter referred to as memory) and an auxiliary storage device (hereinafter referred to as device) such as a floppy disk or hard disk without the intervention of a CPU. DMA (hereinafter abbreviated as DMA) is widely used in recent electronic devices because it can send and receive data at high speed. However, since DMA is performed using a bus that connects the memory and the CPU, the CPU's processing operations on the memory are interrupted while the DMA is performed. Therefore, the less time the DMA uses the bus, the better. Recent 16-bit CPU
has become commonplace, and memory and buses are composed of 16 bits.

On the other hand, most devices are constructed with the same 8-bit length as conventional devices. Therefore, when writing 16-bit long (1 word) memory data to an 8-bit long device, the first DMA
Upper 8 bits or lower 8 bits of bit length data
One of the 8 bits of the bit length is written to the device, and the other 8 bits are written to the device by the second DMA. Conversely, when writing 8-bit data from a device to 16-bit memory, the first DMA writes only to the upper or lower 8-bit portion of the memory, and then the second
Write to the other 8-bit part using DMA. In any case, sending and receiving one word of data requires two DMAs.
Requires. Furthermore, a circuit for alternately connecting the upper 8-bit data bus and the lower 8-bit data bus of 16-bit data between the device and the memory is required for each DMA cycle, which increases the complexity.

<Purpose> The present invention consists of a circuit that temporarily latches 8-bit data and a circuit that generates the signals necessary for DMA, and reduces the time required for DMA by performing DMA in 16-bit units. Let, DMA
The purpose is to improve the processing speed of the CPU by reducing the amount of time that CPU processing is interrupted.

<Features of the Invention> A feature of the direct memory access control circuit of the present invention is that it is composed of a circuit that latches, for example, 8-bit data, and a circuit that generates signals necessary for performing DMA, and that the For example, DMA is performed in units of 16 bits.

<Example> The details of the invention will be explained below.

The device 1 is a device that exchanges data with the memory 4, and its data line 20 has an 8-bit width.The latch 19 and the switching circuit 18 are both bidirectional and are called flip-flops (hereinafter abbreviated as F/F).
When the output Q6 of 5 is "1" and the I/O write signal 7 is "1", the switching circuit 18 connects the contents of the lower 8-bit bus 12 to the data line 20, and the I/O write signal is When it reaches “0”, (second
At t ₁ in the figure, latch 19 latches the contents of upper 8-bit bus 11 internally. Here, the bus 30 is a 16-bit bus composed of an upper bit bus 11 and a lower bit bus 12. This latched content is output to the latch bus 23 while the output Q6 of the F/F 5 is "0" and the I/O write signal 7 is "1" (t2 in FIG. ₂ ). On the other hand, the output Q6 of F/F5 is “0”
When the I/O read signal 8 becomes "1" (t3 in Fig. ₃ ), the switching circuit 18 connects the contents of the data line 20 to the latch bus 23, and the I/O read signal 8 becomes "0". At the time of locking (t ₄ in FIG. 3), the contents of the latch bus 23 are latched internally. When the output Q6 of the F/F 5 is "1", the upper 8 bits of the latched contents are outputted to the bus 11 while the I/O read signal 8 is "1" ( _t5 in FIG. 3). Device 1 outputs two signals requesting data transfer by DMA, namely a device read request signal 27 and a device write request signal 26. These signals are ORed by OR gate 2 and sent to the clock input of F/F 5. and and gate 13
It is connected to the. The F/F 5 inverts the output Q6 every time the device read request signal 27 or the device write request signal 26 is generated. Also F/F5
The output Q6 enters as one input of the AND gate 13, and its output is sent to the DMA controller (hereinafter referred to as
This is a DMA request signal 9 for the DMAC (abbreviated as DMAC) 3.

When the DMA request signal 9 becomes "1", the DMAC 3 requests the CPU 17 for DMA, and when the request is accepted, it generates addressing of the memory 4 and a memory read signal 24 or a memory write signal 25.

Now consider the case where data is transferred from device 1 to memo 4. First, it is assumed that the output Q6 of F/F5 is set to "1". At t6 in FIG. 4, the device 1 sets the device read request signal 27 to "1" to instruct that it wants to send data. Since it becomes an inverted “0”, the DMA request signal 9 to the DMAC3 remains “0” due to the AND gate 13.
No DMA is performed. Instead, the device read request 27 passes through the AND gate 28 and the OR gate 14, sets the I/O read signal 8 to “1”, and outputs the data held by the device 1 (upper 8 bit data) to the data line 20. let Furthermore, this data passes through the switching circuit 18 and the latch bus 23.
appear above. At t7 in FIG. 4, the device read request signal 27 remains at "0", and the data on the latch bus 23 is latched by the latch 19 at this fall. After a further certain period of time, t in Figure 4
At step 8, the device 1 sets the device read request signal 27 to "1" again to request the next data read. This time, the output Q6 of the F/F is inverted from "0" to "1", so the device read request signal 27 passes through the AND gate 13 and changes the DMA request signal 9 to "1". As a result, DMAC3 is
17 for DMA, and after a certain period of time, DMA is started. In the DMA cycle, the memory write signal 25 is set to "1" by the DMAC 3 at t9 in FIG. The memory write signal 25 passes through the decoder 30 and the OR gate 14 and sets the I/O read signal 8 to "1". I/O read signal 8
1, the device outputs output data (lower 8-bit data) to the data line 20 at t10 after a certain period of time. At this time data line 20
is connected to the lower 8-bit bus 12 by a switching circuit 18.

On the other hand, the upper 8-bit bus 11 outputs the latch output of the data output during the previous device access. When the memory write signal 25 changes from "1" to "0" at t11, 16 bits of data on the upper 8-bit bus 11 and the lower 8-bit bus 12 are written into the memory 4, and the DMA ends. This process is repeated every time the device read request signal 27 is generated thereafter. Next, a case will be described in which data is transferred from the memory 4 to the device 1. F/F
It is assumed that the output Q6 of 5 is initially initialized to "0". When the first device write request signal 26 from device 1 becomes "1" (t12 in FIG. 5)
The output Q6 of the F/F5 is inverted and becomes "1". Therefore, the device write request signal 26 passes through the AND gate 13 and requests DMA from the DMAC 3,
DMAC3 requests DMA from CPU17, and DMA can be started. When the memory read signal 24 becomes "1" by the DMAC 3 at t13 in FIG. 5, the I/O write signal 7 also becomes "1" by the OR gate 15. After a certain period of time, the data in the memory 4 is fixed on the upper 8-bit bus 11 and the lower 8-bit bus 12 (t14 in FIG. 5). At this time, the switching circuit 18 connects the lower 8-bit bus 12 to the data line 20. After that, when the memory read signal 24 becomes "0" at t15, the data on the data line 20 (lower 8-bit data) is written to the device 1, and the contents of the upper 8-bit bus 11 are latched into the latch 19. DM ends and the device write request signal 26 also becomes "0". Next, when the device write request signal 26 becomes "1" again (FIG. 5, t)
16) At this time, the output Q6 of F/F5 is inverted and becomes "0". Therefore, by AND gate 13
The DMA request signal 9 remains at "0" and no DMA is performed. However, AND gate 29 and OR gate 1
5, the I/O write signal 7 becomes "1" and the previously latched upper 8-bit bus data is output to the latch bus 23. At this time, the switching circuit connects the latch bus 23 to the data line 20. After a certain period of time, when the device write request signal 26 becomes "0" (t17 in FIG. 5), the I/O write signal 7 also becomes "0" and the data on the data line 20 is written to the device. At this stage, 16 bits of data in memory 4 have been transferred to device 1. This is repeated every time the device write request signal 26 is generated thereafter. Furthermore, in the above embodiments, switching between 8 bits and 16 bits was described, but the present invention is not limited to this.
For example, it can be applied to switching from 16 bits to 32 bits.

<Effects> As described above in detail, in the present invention,
Either the upper side data or the lower side data is stored in a temporary storage means, and a switching circuit outputs the data stored in the storage means to a bus with a large bus width in synchronization with the switching. So,
Even during DMA execution, the time dedicated to the bus can be significantly reduced, thereby greatly reducing the time during which CPU processing is interrupted, thereby greatly improving the throughput of the entire system.

Moreover, in the present application, if the switching circuit is switched,
When the last data can be transferred to a bus with a large bit width, the data stored in the temporary storage means can also be transferred to a bus with a large bit width at the same time. As a result, data transfer efficiency can be greatly improved.

In addition, since read or write access is performed to the device and DMA is executed for the amount of data that has been prepared by the device, overrun errors in data transfer that occur due to the device not being ready in time are completely eliminated, and data transfer is Reliability is greatly improved.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the DMA control circuit of the present invention. 2 to 5 are time charts showing the operation of the embodiment of FIG. 1. 1...Device, 4...Memory, 5...Flip-flop, 18...Switching circuit, 19...Latch, 30...Decoder.

Claims (1)

[Claims] 1. In a device that exchanges data between a memory device and a device using a direct memory access execution circuit activated by a direct memory access start request signal, an upper bit side bus and a lower bit side bus a first bus consisting of a first bus, a second bus connected to a device, and selectively connecting one of an upper bit side bus and a lower bit side bus of the first bus to the second bus. a bus switching circuit; temporary storage means connected to either one of the upper bit side bus and the lower bit side bus of the first bus and the bus switching circuit; responsive to a read or write request signal from the device apparatus; executes read or write access to the device for the unit address of the device, inputs a read request signal and a write request signal from the device, and outputs a signal in response to the read request signal or write request signal. and when reading the data from the device, the read request signal from the device is inverted a predetermined number of times necessary to prepare the data corresponding to the bus width of the first bus. inputting the signal into an inverting means to change the output signal from the inverting means to release the read request signal passage prohibition state of the gate means to which the output signal from the inverting means and either the read request signal or the write request signal are input; By doing this, when writing the data to the device, the write request signal to the device is input to the inverting means to change the output signal from the inverting means, and the gate means changes the output signal from the inverting means to the write request signal. A direct memory access control circuit comprising: a circuit that generates the direct memory access start request signal and outputs it to the direct memory access execution circuit to activate the direct memory access execution circuit.