JPH033112A - Synchronizing circuit for magnetic recording and reproducing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a synchronization circuit for a magnetic recording/reproducing device (hereinafter referred to as VTR), and in particular, to a synchronization circuit for a magnetic tape recording track. This circuit is effective as a circuit for controlling the tracking state of a magnetic head.

(Prior Art) In recent years, in addition to normal playback in which a playback signal is obtained by running a tape at the same speed as the recording speed, special playback functions have been incorporated in VTRs. Special playback functions include slow playback, still playback, and double speed playback.

When such special reproduction is performed, noise bands occur in the reproduced image because the relative positional relationship between the magnetic head and the recording track is different from that obtained during normal reproduction. In order to eliminate this noise band, by attaching a magnetic head to a piezoelectric element and supplying a control signal to this piezoelectric element,
Systems have been developed to achieve linear tracking.

This system is disclosed, for example, in Japanese Patent Publication No. 83-41470.

FIG. 5 is an example of a circuit considered with reference to the above system.

The input terminal 11 is supplied with a capstan FC pulse (CF CP) indicating the rotational phase and frequency of the capstan motor. In addition, the input terminal 12 receives a head switching pulse (HSW) indicating the switching timing of the video head.
is supplied. Furthermore, the input terminal 13 is connected to a drum FG pulse (DF) indicating the rotational phase and frequency of the video head.
GP) is supplied.

The cab scan FG pulse (CFGP) is generated by a first counter 14, a second counter 15, and a timing generation circuit 1.
6. In addition, this timing generation circuit 16 receives the aforementioned head switching pulse (HSW) and the drum FG.
A pulse (D F G P) is supplied. drum FG
The pulse (D F G P) is also supplied to a drum pattern generation circuit 17 used, for example, when performing still playback.

The count output of the first counter 14 is supplied to the second counter 15 as preset data.

The timing generation circuit 16 outputs a reset pulse (R8P) to the first counter 14 and a first preset pulse (CPRS) to the second counter 15. Further, the timing generation circuit 16 includes a pattern generation circuit 17.
A second preset pulse (DPRS) is also supplied to

The output of the second counter 15 and the output of the drum pattern generation circuit 17 are supplied to an adder 18 and combined.

The output of this adder 18 is used to control the amount of displacement of the piezoelectric element. By displacing the piezoelectric element, the deviation of the trajectory of the video head with respect to the recording track can be corrected and normal tracking can be obtained.

(Problem to be Solved by the Invention) In the above circuit, the drum pattern generation circuit 17:
It is set to output a predetermined data pattern when the first drum FC pulse (DFGP) is input after the head switching pulse (HSW) changes. This data pattern is read-only memory (ROM).
) may be read out, or clocks may be counted and their values may be changed in a preset pattern.

On the other hand, the preset pulse (C
PRS) is the capstan FG pulse (CF GP)
It is set to occur synchronously with. Further, the reset pulse (R3P) for the first counter 14 is
This is given to create preset data to be given to the counter 15, and also the capstan FC pulse (
CF CP).

FIG. 6 is a timing chart shown to explain the operation of the above-described circuit. This figure shows an example of creating a displacement amount control signal for the A head during normal playback of a VTR.

3A shows the head switching pulse (HSW), and FIG. 1B shows the second preset pulse (DPRS). Also, (C) in the same figure shows the first preset pulse (CPRS).
It is.

When the video head is switched from the A head to the B head, a second preset pulse (DPRS) is output, and a drum pattern (see FIG. 6(C)) is generated. Next, the first
The second counter 1 is set by the preset pulse (CPRS).
5 is preset, the preset data is set in the second counter 15, and counting up is started (
Figure 6(E)). Figure 6 (F) is similar to Figure 6 (D) and (E).
The data pattern obtained by adding the data of is shown.

By the way, as shown in Fig. 6, when looking at the data pattern finally obtained, when the B head trace section, that is, the A head finishes tracing and moves to the B head trace section, the A For the head side, whisker pulses 20 during section T are included. This whisker pulse 20 is supplied when the A head moves away from the magnetic tape. Therefore, the load on the A head becomes lighter, resulting in the actuator being driven rapidly, which leads to deterioration of the piezoelectric element.

As mentioned above, the cause of the occurrence of the upper pulse 20 is the sixth
This is because the phases of the first and second preset pulses (CPR3) and (DPR8) are shifted as shown in FIGS. (B) and (C).

This problem may be solved by matching the phases of both pulses, but realizing this complicates circuit design and reduces the degree of freedom in design.

That is, the drum pattern generation circuit 17 needs to generate pattern data in synchronization with the drum FG pulse, and the second counter 15 needs to start counting in synchronization with the capstan FC pulse. Here, if there are m drum FG pulses (D F G P) in the A head trace period and n capstan FC pulses (CFGP) corresponding to one track pitch, m and n do not necessarily match. It is. Further, the values of m and n may vary depending on the model, and may also vary depending on the speed.

Therefore, at present, the above-mentioned whisker pulse 20 cannot be avoided.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a synchronization circuit for a magnetic recording/reproducing device in which a pulse waveform that would degrade the piezoelectric element as described above does not appear at least in the final output stage.

[Structure of the Invention (Means for Solving the Problems) This invention provides a counter means for counting capstan pulses in synchronization with a first pulse (capstan clock) after a change in the head switching pulse; an adder to which the output of the counter means is supplied to one end; a pattern data generation means to generate pattern data in synchronization with a second pulse (drum clock); and an output of the pattern data generation means to the other end of the adder. When supplying to
Synchronization in which the output of the pattern data generation means is held during a period from when the pattern data generation means is initialized until a clock is first input to the first counter means, and is in a through state during other periods. means.

(Function) With the above means, a sharp change part of the pattern data will not be superimposed on a section where the output of the counting means that counted the first pulse changes smoothly, and no whisker pulses will appear.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The input terminal 21 is supplied with a capstan FG pulse (CF CP) indicating the rotational phase and frequency of the capstan motor. Further, a head switching pulse (HSW) indicating switching timing of the video head is supplied to the input terminal 22. Further, the input terminal 23 is supplied with a drum FG pulse (DFGP) indicating the rotational phase and frequency of the video head.

The cab scan FC pulse (CF CP) is supplied to a first counter 24 , a second counter 25 , and a timing generation circuit 25 . In addition, this timing generation circuit 25 receives the aforementioned head switching pulse (HSW) and the drum F.
G pulse (DFGP) is supplied. Drum F
The G pulse (DFGP) is generated by the tram pattern generation circuit 27. which is used when performing still playback, for example. is also supplied.

The count output of the first counter 24 is supplied to the second counter 25 as reset data.

The timing generation circuit 26 outputs a reset pulse (R5P) to the first counter 24 and a first preset pulse (CPR3) to the second counter 25. Further, the timing generation circuit 26 includes a pattern generation circuit 27.
A second preset pulse (DPR8) is also supplied to the second preset pulse (DPR8).

Here, the output pattern data of the drum pattern generation circuit 27 is supplied to the adder 28 via the hold circuit 31. Therefore, the output of the second counter 25 and the output of the drum pattern generation circuit 27 are supplied to the adder 28 and combined. The output of this adder 28 is used to control the amount of displacement of the piezoelectric element. By displacing the piezoelectric element, the deviation of the trajectory of the video head with respect to the recording track can be corrected and normal tracking can be obtained.

The hold state and through state of the hold circuit 31 are controlled by the output of the AND circuit 30. A signal obtained by inverting the steal mode designation signal from the input terminal 32 is supplied to one input terminal of the AND circuit 30. In the normal reproduction state, the terminal 32 side is always at a high level, and the output of the AND circuit is controlled by the output of the hold timing circuit 29. The hold circuit 31 is an AND circuit 30
When the output is high level, it is in a hold state, and when it is low level, it is in a through state, in which input data is passed through as is. When in steal mode, AND circuit 3
The output of 0 is at a low level because the terminal 32 is at a low level, and the hold circuit 31 is always in a through state.

The output from the hold timing circuit 29 is supplied to the other input terminal of the AND circuit 30. This hold timing circuit 29 uses a head switching pulse (HSW).
) is input manually (falls), the high-level output ( hold signal).

FIG. 3 is a timing chart of various signals. As a result, as shown in FIG. 4, the drum pattern data is
Although it is generated from time tl, the timing at which it is actually input to the adder 28 is time t2, and no whisker pulse appears in the final output from the adder 28 as in the conventional case. Therefore, a sudden pulse is not supplied to the piezoelectric element serving as the head base immediately after the A head finishes tape tracing, and the life of the piezoelectric element is not deteriorated.

FIG. 2 shows a specific circuit example of the hold timing circuit 29. The counter 41 is cleared, for example, at the rising edge of the head switching pulse (HSW), and counts the drum FC pulse (DFGP). Then, when the head switching pulse (HSW) falls and the subsequent second preset pulse (DPRS) is obtained, the detection circuit 42 detects this and sets the flip-flop circuit 43. This means that the leading edge of the hold section is set. The set output of the flip-flop circuit 43 is also used as a clear pulse for the counter 45. The counter 45 receives a capstan FG pulse (CF
GP).

Then, from this count, the detection circuit 46 detects the time point at which the first preset pulse (CPRS) is obtained. The detection circuit 46 resets the flip-flop circuit 43 at the time of this detection. This means that the trailing edge of the hold section has been set.

The above description has been made regarding the circuit for obtaining the tracking control signal for the piezoelectric element on the A head side, but the tracking control signal can also be obtained for other heads by a similar circuit.

Furthermore, when the VTR is in the steel mode, the cab scan FC pulse (CF CP) cannot be obtained. For this reason, the output of the flip-flop circuit 43 always becomes a set output (high level).

If the output of the flip-flop circuit 43 is always at a high level, the output of the AND circuit 30 depends on the level applied to the terminal 32. For steel mode, terminal 3
2 is always at a low level, the output of the AND circuit 30 is at a low level. Therefore, in the steal mode, the hold circuit 31 is always in the through state.

At this time, since the output of the counter 25 does not count up, a tracking control signal for steel is obtained in accordance with the drum pattern data.

The drum pattern generation circuit 27 generates tracking pattern data corresponding to the mode set in the VTR.
If the data is stored in the ROM in advance and the data is used, optimal tracking can be obtained in response to various special playback modes.

The above description is a basic embodiment of the invention, and various modifications are possible. For example, when changing drum pattern data in response to special playback, a mode switching signal is input to the generating circuit.

Furthermore, when setting the hold timing, various configuration examples can be considered in order to create a timing pulse.

[Effects of the Invention] As explained above, according to the present invention, it is possible to prevent the pulse waveform that would degrade the piezoelectric element as described above from appearing at least in the final output stage.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the hold timing generation circuit of FIG. 1, and FIG.
4 and 4 are signal waveform diagrams shown to explain the operation of the circuit of this invention, FIG. 5 is a diagram showing an example of a tracking control circuit that is the premise of this invention, and FIG. FIG. 4 is a diagram showing signal waveforms shown to explain the operation of the circuit. 24.25... Counter, 26... Timing generation circuit, 27... Drum pattern generation circuit, 28...
Adder, 29...Hold timing circuit, 30...
-AND circuit, 31...Hold circuit.

Claims (1)

[Claims] Counter means for counting capstan pulses in synchronization with a first pulse (capstan clock) after the head switching pulse changes, and an adder to which the output of the counter means is supplied to one side. and a pattern data generating means for generating pattern data in synchronization with a second pulse (drum clock); and when supplying the output of the pattern data generating means to the other of the adders, the pattern data generating means The apparatus further comprises synchronizing means for holding the output of the pattern data generating means during a period from initialization to when a clock is first input to the first counter means, and keeping the output of the pattern data generating means in a through state during other periods. A synchronization circuit for a magnetic recording/reproducing device characterized by: