JPH033183B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital display vehicle speedometer, and more particularly, a vehicle speed counter that counts vehicle speed pulses generated in proportion to vehicle speed for a fixed gate time, and a display according to the output of the vehicle speed counter. The present invention relates to an improvement in a digital display vehicle speedometer that includes a display register that stores values and a display that displays the contents of the display register.

In general, a digital display speedometer that digitally displays the running speed of a vehicle, etc. includes a vehicle speed counter that counts vehicle speed pulses generated in proportion to the vehicle speed in accordance with the rotation of a propeller shaft or wheels for a fixed gate time; The vehicle speed counter includes a display register that stores the previous count value of the vehicle speed counter as a display value while the vehicle speed counter is counting, and a display that displays the contents of the display register. This digital display speedometer has the feature that the vehicle speed is always digitally displayed on the display, but conventionally, the output of the vehicle speed counter is stored as a display value in a display register and repeatedly displayed on the display. As a result, the display was rewritten every approximately constant gate time, and when the vehicle stopped from running, the display did not immediately return to 0 due to the gate time, which caused an odd feeling. It was hot. That is, as an example, the vehicle speed pulse is 0.5Km/
In the case of h/pulse, if the gate time is 0.28 seconds, if the vehicle stops after the vehicle speed pulse is input immediately after the gate starts, the time will be approximately twice the gate time even though the vehicle has stopped. There is a delay in the display speed reaching 0 km/h for 0.56 seconds.

In order to overcome these drawbacks, it is possible to change the gate time and display rewriting cycle depending on the vehicle's driving condition, but this would not only require an acceleration sensor etc. to detect the vehicle's driving condition. Post-processing of the signal becomes complicated, making it difficult to put it into practical use.

The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and an object of the present invention is to provide a digital display type vehicle speedometer that can provide a good display without giving any strange feeling when the vehicle is stopped from running. shall be.

The present invention includes a vehicle speed counter that counts vehicle speed pulses generated in proportion to vehicle speed for a fixed gate time, a display register that stores a display value according to the output of the vehicle speed counter, and a digital display of the contents of the display register. In a digital display vehicle speedometer equipped with a display, when the interval between vehicle speed pulses exceeds a predetermined time, the contents of the vehicle speed counter as well as the contents of the display register are given priority over the display based on the vehicle speed pulses measured for a certain gate time. The above object is achieved by providing a zero display determination circuit that forcibly sets the value to 0, and a timing generation circuit that commands the vehicle speed counter, display register, and zero display determination circuit to initial reset when the power is turned on. It is.

Embodiments of the present invention will be described in detail below with reference to the drawings. As shown in FIG. 1, this embodiment uses a gate signal 101 to generate a vehicle speed pulse 100 that is generated in proportion to the vehicle speed in accordance with the rotation of the axle.
A vehicle speed counter 12 that counts a certain period of time during which the AND gate 10 is open;
A display register 14 for storing a display value corresponding to the output signal 107 of No. 2, and a display device 16 consisting of a fluorescent display tube, a plasma display, a liquid crystal, a light emitting diode, etc., for displaying the contents 108 of the display register 14. In the digital display type vehicle speedometer,
A zero display determination circuit 18 for forcibly resets the contents of the display register 14 and the vehicle speed counter 12 to 0 when the generation interval of the vehicle speed pulse 100 exceeds a predetermined time;
2. A timing pulse generation circuit 20 is provided which instructs the display register 14, zero display determination circuit 18, etc. to perform an initial reset. In the figure, 20 indicates a constant gate signal 101 whose gate-on timing is synchronized with the rising edge of the vehicle speed pulse 100 and which determines the counting time of the vehicle speed counter 12.
The latch signal 102 is output to the display register 14 at a timing suitable for inputting the count value of the vehicle speed counter 12 to the display register 14 after counting the count value of the vehicle speed counter 12. Reset signal 1 to return to 0
03 to the vehicle speed counter 1 via the OR gate 22.
2, and further outputs an initial setting signal 104 for initial setting when the power is turned on;
The zero display signal 105 of 8 outputs is sent to the display register 14 and the vehicle speed counter 1 via the OR gate 24.
It is designed to be input to the second reset terminal.

The zero display determination circuit 18 detects a vehicle speed pulse of 100
The OR gate 30 outputs the logical sum of the initial setting signal 104 outputted from the timing pulse generation circuit 20, and the clock pulse signal 106 outputted from the timing pulse generation circuit 20. A time counter 32 that counts until it is reset by the output, and the OR gate 30 that outputs a zero display signal 105 to the OR gate 24 when the time counter value 107 output from the time counter 32 becomes equal to or higher than a predetermined value. The bistable multivibrator 34 is reset by the output.

The timing pulse generation circuit 20 also includes a bistable multivibrator 40 to which the vehicle speed pulse 100 is input, and the bistable multivibrator 40.
The Q terminal output of the bistable multivibrator 40 is input directly, and the terminal output of the bistable multivibrator 40 is also input via the resistor 42 and capacitor 44.
an AND gate 46, a resistor 48, a capacitor 50, a diode 52, and an inverter 54, which output an initialization signal 104 when the power is turned on;
An oscillator 56 that generates clock pulses, the output of the oscillator 56 is directly input to the CP terminal, and a shift register 60 is input to the D terminal via the frequency dividing circuit 58, and the output of the shift register 60 is input directly and via an inverter 62,
AND outputs latch signal 102
a gate 64, an AND gate 68 to which the output of the shift register 60 is input directly and via an inverter 66, and outputs a reset signal 103; a reset signal 103 output from the AND gate 68; A three-input OR gate 70 receives the output of the gate 46 and the initial setting signal 104 of the inverter 54 output, and outputs a reset signal to the frequency divider circuit 58; The output of the frequency dividing circuit 58 is input, and the bistable multivibrator 4
It consists of an OR gate 72 that outputs a reset signal to 0.

The operation will be explained below with reference to FIG. The second signal is generated in proportion to the vehicle speed according to the rotation of the wheels.
A vehicle speed pulse 100 as shown in FIG. a is input to a vehicle speed counter 12 via an AND gate 10,
As shown in FIG. 2b, if the gate signal 101 output from the timing pulse generation circuit 20 is "1", AND
A certain period of time T during which the gate 10 is open is counted. This gate signal 101 is a vehicle speed pulse 10
It becomes “1” in synchronization with the rise of 0, and remains for a certain period of time T.
After continuing to be "1" for a period of time, it becomes "0". After the gate signal 101 becomes "0", the timing pulse generating circuit 20 outputs a latch signal 102 as shown in FIG. 2c to the display register 14. When "1" is output to this latch signal 102, the contents of the display register 14 are rewritten according to the output signal 107 (count value) of the vehicle speed counter 12, and the contents 108 of this display register 14 are rewritten according to the output signal 107 (count value) of the vehicle speed counter 12.
becomes the displayed value on the display 16.

On the other hand, the time counter 3 of the zero display determination circuit 18
2 includes a vehicle speed pulse 100 and an initial setting signal 10.
4 is input as a reset signal via the OR gate 30, and the time counter 32
As shown in Figure e, the oscillator 5 of the timing pulse generation circuit 20 is
By counting the clock pulse signals 106 of 6 outputs,
The time counter value is set to 107. When the vehicle is at slow speed or stopped, the time counter value counted by the time counter 32 is a value 110 corresponding to a predetermined interval set in the bistable multivibrator 34, for example, a vehicle speed of less than 1 km/h or 1 mile/h. As shown in Figure 2 f,
The zero display signal 105 output from the bistable multivibrator 34 becomes "1" and is input as a reset signal to the display register 14 and vehicle speed counter 12 via the OR gate 24, and the contents of the display register 14 and vehicle speed counter 12 are forcibly changed. It is set to 0. Here, the reason why the output of the zero display determination circuit 18 is inputted not only to the display register 14 but also to the vehicle speed counter 12 is that the output of the zero display determination circuit 18 is inputted not only to the display register 14 but also to the vehicle speed counter 12 at very low speeds.
This is to prevent the contents of the vehicle speed counter 12 from being displayed again when the zero display signal 105 becomes "0" due to the difference between the contents of the display register 14 and the contents of the display register 14. In this way, when you stop from running, the displayed speed will change to 1 for the set time.
By setting the interval time between vehicle speed pulses to be Km/h or 1 mile/h, it is possible to monitor whether the vehicle speed is 0 Km/h or 0 mile/h for each vehicle speed pulse, and /h or less, the contents of the display register 14 can be immediately set to 0, and the display value of the display 16 can be set to 0.
It can be done. In contrast, conventionally, in the worst case, that is, immediately after the gate signal 101 becomes "1", a vehicle speed pulse equivalent to 1 km/h or more is input and the vehicle immediately stops, the gate becomes "1". When the signal 101 becomes "0", the speed is displayed at 1 km/h or more, and after the gate signal changes from "1" to "0", the latch signal 102 becomes "1" and the speed becomes 0 km/h for the first time. was. For this reason, even when the vehicle stops, the displayed value does not immediately become 0, which creates a sense of discomfort.

On the other hand, the AND of the timing pulse generation circuit 20
After the gate 64 outputs "1" to the latch signal 102, the AND gate 68 outputs "1" to the reset signal 103, as shown in FIG. 2d, and the vehicle speed counter 12 is reset. Provides for vehicle speed pulse counting during gate time. Therefore, after "1" is output as the reset signal 103, when "1" is input as the vehicle speed pulse 100,
The timing pulse generation circuit 20 sets the gate signal 101 to "1" in synchronization with the vehicle speed pulse 100. The reason why the vehicle speed pulse and the gate signal are synchronized in this way is to prevent variations in the counted value of the vehicle speed counter caused by the gate being out of alignment with the vehicle speed pulse.

Note that when the power is turned on, there is a possibility that the above-mentioned operation may not be performed properly, so the initial setting signal 104 is used to control the vehicle speed counter 12, display register 14, time counter 32 of the zero display determination circuit 18, and bistable multivibrator. 34, the bistable multivibrator 40, shift register 60, etc. of the timing pulse generation circuit 20 are initialized to prevent malfunctions.

That is, in FIG. 1, when the power is turned on by the ignition switch, the capacitor 50 is rapidly charged through the resistor 48 and rises to the power supply voltage. Therefore, the output of the inverter 54 inverts the rising signal to output a spike-like trigger pulse, and this trigger pulse is used as the initial reset signal.
It is supplied as RI to the circuit to perform the desired initial reset.

In the embodiment described above, the zero display determination circuit was constructed of a time counter and a bistable multivibrator, but the configuration of the zero display determination circuit is not limited to the embodiment described above.

A modification of the zero display determination circuit used in the present invention is shown in FIG. This zero display determination circuit 80 uses the initial setting signal 1 output from the timing pulse generation circuit 20.
04, and a vehicle speed pulse 100.
and outputs the logical product of the output of the inverter 82.
It is set by an AND gate 84 and the output of the AND gate 84, and its contents are cleared by the output of the inverter 82. It is composed of a retriggerable monostable circuit 90 which has a set time determined by a capacitor 86 and a resistor 88, and outputs a terminal output as a zero display signal 105 when the time interval of the output of the AND gate 84 exceeds the set time.

As explained above, according to the present invention, when the vehicle stops from a running state, the displayed value can be quickly set to 0, and a good display without any strange feeling can be obtained. can be set to 0, and it is possible to prevent the display from becoming difficult to read due to the difference between the vehicle speed value and the displayed value. Furthermore, since the vehicle speed value, display value, etc. are initially reset when the power is turned on, it has the excellent effect of preventing erroneous display due to malfunction. Specifically, the gate time of the vehicle speed counter is 0.28 seconds, and the vehicle speed pulse is 0.5 km/pulse.
h, when the displayed value becomes 1 km/h due to two vehicle speed pulses within the gate time, conventionally the 0 display is delayed by 0.56 seconds under the worst condition, but with the present invention, the 0 display is delayed within 0.14 seconds, which is half the gate time. By setting the display to 0 if there is no vehicle speed pulse, the delay time can be reduced to 0.14 seconds.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital display vehicle speedometer according to the present invention, and FIG.
FIG. 3 is a block diagram showing a modification of the zero display determination circuit used in the present invention. 10...AND gate, 12...vehicle speed counter,
14...Display register, 16...Display device, 18,
80... Zero display determination circuit, 20... Timing pulse generation circuit, 22, 24... OR gate.

Claims (1)

[Claims] 1. A vehicle speed counter that counts vehicle speed pulses generated in proportion to vehicle speed for a fixed gate time, a display register that stores a display value according to the output of the vehicle speed counter, and a display register that stores the contents of the display register. A digital display vehicle speedometer equipped with a digital display device includes a time counter that counts the generation interval of vehicle speed pulses by counting clock pulses and outputs a zero display signal when the counter value exceeds a predetermined value, a zero display determination circuit that forcibly sets the contents of the display register and the vehicle speed counter to zero, giving priority to a display based on a vehicle speed pulse measured for a certain gate time when the zero display signal is output; and a power source. 1. A digital display type vehicle speedometer, comprising: a timing pulse generation circuit which, when turned on, instructs the vehicle speed counter, the display register, and the time counter of the zero display determination circuit to initialize reset.