JPH033185A - Input/output asynchronous controller for field memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an input/output asynchronous control device when a field memory is used as a FIFO (first in, first out) buffer.

<Prior Art> Conventionally, as a field memory used as a FIFO buffer, there is a type shown in the 11th ffl. This field memory includes a memory section 40 consisting of a memory block I and a memory block ■, and a read register (
a read register) 41, a write register (write register) 42, the memory section 40, and a read register 41. Transfer gates 43 . The transfer gate 44 receives a signal from a serial clock (not shown). The above read register 41. Write register 42. Transfer gate 43. The transfer gate 44 has first half portions 41a, 42a, 43a, and 44a that each operate on memory block I, and a second half portion 4 that operates on memory block ■ independently of these.
It consists of lb, 42b, 43b, and 44b.

Then, the serial clock is the timing signal WO~W3
99. As W400 to W909 are generated sequentially, the first half 42a and the second half 42b of the write register 42 are sequentially accessed to input serial data, and in synchronization with this, the first half 41a and the second half 41b of the read register 41 are accessed. is accessed to output serial data (input/output synchronous method). In this method, for example, as shown in FIG.
2 to the bit line of the memory section 40 (hereinafter referred to as the "write transfer control period") and the period during which data is transferred from the memory section 4 to the bit line of the memory section 40.
The serial clock sequentially outputs a timing signal WO during which data is transferred from the 0 bit line to the read register 41 (hereinafter referred to as "read transfer control period").
- It is synchronized with W909 to prevent conflicts between the above two periods. That is, when the serial clock advances sequentially and generates the timing signal W400, a write transfer control period and a read transfer control period of 8 clock cycles are sequentially provided from the timing of generation of this signal based on this signal to control the memory block. Similarly, a write transfer control period of 8 clock cycles starts from the time when the timing signal WO is generated.

The above memory blocks are set up in sequence with read transfer control periods.
I am trying to transfer information about this.

<Problems to be Solved by the Invention> However, in the conventional field memory described above, if the input/output asynchronous method is used in which the frequencies of data input timing and data output timing are different, read transfer is executed during the write transfer control period. Conversely, it becomes necessary to execute write transfer during the read transfer control period, and if this is done, there is a problem that data continuity is lost.

Therefore, an object of the present invention is to control field memory input/output asynchronous control that can obtain data continuity regardless of whether the timing of data output is synchronous or asynchronous by skillfully adjusting the conflict in the transfer control period. The goal is to provide equipment.

Means for Solving the Problems> In order to achieve the above object, the present invention transfers data serially written to a write register to bits of a field memory via a transfer gate at a timing determined by a signal from a serial clock. In a field memory input/output asynchronous control device that reads the data from the bit line of the field memory at a timing asynchronous to the above timing and transfers it to the read register via a transfer gate, the data is generated by the serial clock. Creates and outputs a transfer request signal indicating that data transfer between the memory block and the read or write register is requested based on the timing signal, and outputs a transfer request signal for either the read or write. During the period,
A transfer request signal that creates and outputs the other transfer request signal after the data transfer is completed and the one transfer request signal is released when the other read or write timing signal is received asynchronously. A generation unit receives the transfer request signal, starts clock counting to determine a certain transfer control period, and generates a timing signal that becomes a reference for opening the transfer gate and executing the transfer during this transfer control period. a counter section that generates and outputs the output, and receives the timing signal from the counter section,
a row address strobe signal generation unit that creates a row address strobe signal and outputs it to the memory block during the transfer control period; and a row address strobe signal generation unit that receives the timing signal from the counter unit and receives the row address strobe signal output period, and Create transfer signals to perform data transfers between memory blocks and read or write registers,
a transfer signal generation unit outputting to the transfer gate;
Transfer control that receives the timing signal from the counter section, creates a signal for canceling the one transfer request signal after the one transfer control period has elapsed, and outputs this signal to the transfer request signal creation section. The present invention is characterized in that it includes a period end signal generator so that the two transfer gates between the field memory and the write register and read register operate during mutually different transfer control periods.

<Operation> When the transfer request signal generation unit receives the timing signal for the read or write asynchronously generated by the serial clock during the transfer control period for either read or write, the transfer request signal generation unit Rather than immediately creating a transfer request signal based on a timing signal,
Based on the signal from the transfer control period end signal generation section, after the data transfer is completed and the one transfer control period ends, the other transfer request signal is generated and output.

Therefore, there is no overlap in the read and write transfer control periods, and the two transfer gates between the field memory, write register, and read register operate during different transfer control periods, so each transfer can be performed smoothly. be exposed. Therefore, continuity of input data and output data is obtained.

<Embodiments> Hereinafter, the field memory input/output asynchronous control device of the present invention will be explained in detail with reference to illustrated embodiments.

As shown in FIG. 1, this input/output asynchronous control device includes a transfer request signal generation section 1, a 3-bit counter section 2, and an RA
It includes an S (row address strobe) signal generation section 3, a transfer signal generation section 4, and a transfer control period end signal generation section 5. In addition to the field memory shown in FIG. 11, it is assumed that a field memory including a write serial clock WCK and a read serial clock RCK synchronous or asynchronous thereto is controlled. It is also assumed that the field memory is used in synchronization with a read address reset signal RRSTAL1 for resetting the read address and a write address reset signal WR9TALI for resetting the write address. Note that the read address reset signal RRSTAL l
represents a signal obtained by taking the logical sum of the read line reset use RLRST1 that resets the address in the row direction and the read address clear signal RCLR1 that clears the address.Similarly, the write address reset signal WRSTALI is Reset signal WLR
8TI and the write address clear signal RCLRI are logically summed.

As shown in FIG. 2, the transfer request signal generation section 1 includes a next transfer signal memory section 2, a synchronous mode recognition section 12, a transfer cancellation signal generation section 13, and a transfer request signal output section t4. The next transfer signal memory section 11 is configured by, for example, the circuits shown in FIGS. 3(a) to 3(d), and receives the timing signal R from the read serial clock RCK during the output period of the write transfer request signal WTRN (WTRN=H).
CK400, read address reset signal RR8TAL
If l is input, read transfer preparation signal WR
By creating TRNBFl and WRTRN and outputting them to the transfer request signal output unit 14, preparations are made to perform read transfer (RTRN=H) as soon as the write transfer request signal WTRN is released (WTRN=L). On the other hand, during the read transfer request signal RTRN output period (RTRN=H), the timing signal WCK400.
When the write address reset signal WR8TALI is input, the respective write transfer preparation signal RWTRNBF'
The above read transfer request signal RTRN is generated by creating the RWTRN of l and outputting it to the transfer request signal output unit
As soon as RTRN is released (RTRN=L), write transfer (WTRN
Prepare to perform =H). The synchronous mode recognition unit 2 is configured by, for example, the circuits shown in FIGS. 5(a) and 5(b), and when the read address reset signal RR9TAL1 and the write address reset signal overlap in time, or when the timing signal W400 and If there is a temporal overlap with R400, the input/output system of the field memory is recognized as synchronous mode, and each synchronous mode recognition signal 5yn
cl O, 5 sync20 to the transfer request signal output unit 14
(Sync O=H, 5sync20=H). The transfer cancellation signal generation section 13 is constituted by, for example, the circuits shown in FIGS. Based on this, each transfer request signal WTRNI, WTRN2 . RTRNI, RT
Transfer release signal WT 8 for releasing each RN2
1, WT 82. RT 81. RT 82 is created and output to the transfer signal output section 14.

The transfer request signal output unit 14 is configured by, for example, a circuit shown in FIG.
Read transfer request signal R for opening the first half 44a of 4
While creating and outputting TRN2, timing signal R9
10 or read address reset signal RR9TAL
The second half 44b of the transfer gate 44 based on
A read transfer request signal RTRN1 for opening the read transfer request signal RTRN1 is generated and output. Moreover, these signals RTRN l , RTR
A read transfer request signal RTRN is created by calculating the logical sum of N2 and output. Further, when the read clock RCK and the read address reset signal RR9TALI are asynchronous and the read address reset signal RR9TAL1 is input while the first half 41a of the read register 41 is being accessed, the transfer gate 4
In order to simultaneously open the first half 44a and the second half 44b of 4, the read transfer request signal RTRN2 is output.

Similarly, this transfer request signal output unit 14 outputs a timing signal WCK40 from the write serial clock WCK.
The first half 43a of the transfer gate 43 based on
Creates and outputs a write transfer request signal WTRN2 for opening the transfer gate 43b, and creates and outputs a write transfer request signal WTRNI for opening the latter half 43b of the transfer gate 43 based on the timing signal W910 or the write address reset signal WRSTALI. do. Furthermore, these signals WTRN1. A write transfer request signal WTRN is created by calculating the logical sum of WTRN2 and output. Write clock WCK and write address reset signal WRSTA
When the write address reset signal WR8TALI is input while the first half 42a of the write register 42 is being accessed, the first half 43a and the second half 43b of the transfer gate 43 are simultaneously reset based on this signal. To open the above write transfer request signal WT
Output RN2. Furthermore, the read transfer request signal R
A transfer request signal TRN is generated by taking the logical sum of TRN and a write transfer request signal WTRN, and is output. Also, the simultaneous mode recognition signal 5yn from the simultaneous mode recognition section 12
When IO is input, the write transfer request signal WTRNI or WTRN2 is set to H level and output, and after the write transfer is completed, the read transfer request signal RTRNI or RT11N2 is output. Further, when the read address reset signal RRSTAL l or the timing signal R400 is input during the write transfer request signal output period (WTRN=H), the transfer request signal output unit 14 outputs the next transfer signal memory fill based on this. Write transfer preparation signal WRT from
In the state where RN (=H) and WRTRNBpl (=H) are being input, the transfer release signal generator 13 further generates a transfer release signal WT81. based on the transfer end signal T8T.
When WT82 is input, the above transfer preparation signal WRTRN
Alternatively, it releases WRTRNBF'1 and outputs the read transfer request signal RTRN1 or RTRN2 at H level. Similarly, during the read transfer request signal output period (
RTRN=H), write address reset signal WRS
When TAL l or timing signal W400 is input, read transfer preparation signal RWTRN (=H) or RWTRN is sent from next transfer signal memory section 11 based on this.
In the state where BF 1 (=H) is not input, the transfer cancellation signal RT81. When RT82 is manually operated,
The above RWTrtN or r (WTrtNBF' l is released and the write transfer request signal WTRNI or WT is
RN2 is set to 1-level and output.

The 3-bit counter section 2 includes, for example, the 3-bit counter section 2 shown in FIG. 7(a).
It is composed of a bit counter and a decoding section shown in (b) to (e) of the same figure. Then, upon receiving the transfer request signal TRN outputted from the transfer request signal generation section 1, when this signal TRN goes to L level, the 3-bit counter counts the clocks of the 8 clock period of the write serial clock WCK. . That is, a transfer control period for eight clocks of the write serial clock WCK is created. During this period, the decoding section generates a timing signal T4 (fourth clock) according to the clock count, and uses the timing signal T4 (4th clock) for use by the RAS generation section shown in FIG. Also, a timing signal W for write transfer
T5 (5th clock), RT7 (7th clock) for read transfer
(8th clock) and RT8 (8th clock) are created in the same way and outputted to the transfer signal creation section 4, and at the same time, a timing signal T8 is created and outputted to the transfer control period end signal creation section 5. The 3-bit counter is reset by a counter reset signal Re5etC generated and outputted by the transfer control period end signal generation section 5 based on the timing signal T8.

The RAS signal generating section 3 is constituted by, for example, a circuit shown in FIG. 8, and generates a RAS signal based on the timing signal T4 and the counter reset signal Reset C.

That is, while the first half of the transfer control period (To-T3) of 4 WCK clocks is used as a precharge period, the RAS signal is set to H level in response to timing signal T4, and then set to L level in response to counter reset signal Reset C. 4 clocks of WCK (T4 to T7) in the second half as R
This is the AS signal output period.

The transfer signal generation unit 4 is configured as shown in FIGS. 9(a) and 9(b), for example.
It consists of the circuit shown in . The transfer signal generating section 4 receives the timing signal WT5 from the 3-bit counter section 2 and generates the write transfer signal W at this timing.
After setting TRE to H level, bit line sense end signal R
Upon receiving CD2, this signal is set to L level, and further, upon receiving timing signal r (T7) from the 3-bit counter section 2, the read transfer signal RTRE is set to H level at this timing, and then upon receiving timing signal RT8, this signal is set to H level. R
Set TRE to L level. Then, by outputting the write transfer signal WTRE and the read transfer signal RTRE to the transfer gate 4344 shown in FIG.
Light transfer between.

A read transfer with the read register 41 is executed.

The transfer control period end signal generating section 5 is constituted by, for example, a circuit shown in FIG. 1O. Then, upon receiving the timing signal T8, a transfer end signal T8T having a pulse width of half a rising clock of this signal is generated based on the timing signal T8, and is outputted to the transfer request signal generating section 1. Further, a counter reset signal ResetC is created based on this transfer end signal T8T and outputted to the 3-bit counter section 2 and RAS signal creation section 3.

This input/output asynchronous control device operates as follows as a whole.

During the write transfer control period (WTRN=H), the write line reset signal WLR8Tl or the write clear signal WCLRI, that is, the write address reset signal WR
When STALI is input (H level), the transfer control period end signal generation unit 5 generates the counter reset signal Res.
etc. C signal is output to reset the 3-bit counter section 2, and at the same time, a transfer end signal T8T is output to cancel the write transfer request signal WTRN of the transfer request signal generation section 1 (L
level). And then, the transfer request signal creation section again! outputs the write transfer request signal WTRN to the 3-bit counter section 2, and starts the write transfer control period again.

Similarly, during the read transfer control period (RT RN=) (
), when the read line reset signal RLR8T1 or the read clear signal RCLRI, that is, the read address reset signal RR9TAL1 is input (H level), the read transfer control period starts again after the above period has elapsed.

On the other hand, if the read address reset signal RR9TAL1 is input during the write transfer control period (WTRN=H), the transfer control period end signal generation section 5 outputs the counter reset signal Reset C signal to reset the 3-bit counter section. 2 and outputs the transfer end signal T8T to generate the write transfer request signal W of the transfer request signal generation unit l.
Release TRN.

Thereafter, the transfer request signal generating section 1 newly outputs a read transfer request signal RTRN to the 3-bit counter section 2, thereby starting a read transfer request period.

Similarly, if the write address reset signal WRSTALI is input during the read transfer control period (WTRN=H), a new write transfer control period is started after the above period has elapsed.

In this way, by controlling the operation of the field memory, it is possible to adjust the conflict (overlap) of the transfer control period that occurs when the input/output clocks are asynchronous, and the timing of the input/output is synchronous; It is possible to obtain continuity of data without any problem.

<Effects of the Invention> As is clear from the above, the field memory input/output asynchronous control device of the present invention controls data transfer between the memory block and the read or write register based on the timing signal generated by the serial clock. When creating and outputting a transfer request signal indicating that a request has been made, and asynchronously receiving the timing signal of the other reading or writing during the output period of the transfer request signal of one of the reading or writing, A transfer request that does not immediately create a transfer request signal based on the other timing signal, but creates and outputs the other transfer request signal after the data transfer is completed and the one transfer request signal is released. A signal generation unit, upon receiving the transfer request signal, starts clock counting to create a certain transfer control period, and also serves as a reference timing for opening the transfer gate and executing the transfer during this transfer control period. A counter section that creates and outputs a signal,
Transfer control that receives the timing signal from the counter section, creates a signal for canceling the one transfer request signal after the one transfer control period has elapsed, and outputs this signal to the transfer request signal creation section. A period end signal generation section is provided so that the two transfer gates between the field memory and the write register and read register operate during different transfer control periods, so that the data input/output timing is synchronized. Data continuity can be obtained despite asynchronous data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a field memory input/output asynchronous control device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a transfer request signal generation section of the input/output asynchronous control device, and FIG. Figures 3 (a) to (d), Figure 4 (a)
) to (d), Fig. 5 (a) to (b), and Fig. 6 are diagrams showing the circuit configuration of each part of the transfer request signal generation section, respectively, and Fig. 7 (a) to (e) are the diagrams shown above. Figure 8 is a diagram showing the circuit configuration of the 3-bit counter section of the output asynchronous control device.
A diagram showing the circuit configuration of the AS signal generation section, FIGS. 9(a) and (b) are diagrams showing the circuit configuration of the transfer signal generation section, and FIG. 1θ is a diagram showing the circuit configuration of the transfer control period end signal generation section. , FIG. 11 is a block diagram showing the configuration of a conventional field memory, and FIG. 12 is a diagram illustrating a conventional method of adjusting a transfer control period. l...Transfer request signal generation unit, 2...3-bit counter unit, 3...RAS signal generation unit, 4...Transfer signal generation unit,
5...Transfer control period end signal creation section, l[...Next transfer signal memory section, 12...Synchronization mode recognition section, 13...Transfer cancellation signal creation section, 14...Transfer request signal output Department. Patent creator Sharp Corporation

Claims (1)

[Claims] (1) At the timing determined by the signal from the serial clock, the data serially written in the write register is transferred to the bit line of the field memory via the transfer gate, and at the same time, the bit line of the field memory is transferred asynchronously to the above timing. In a field memory input/output asynchronous control device that reads the above data from the line and transfers it to the read register via the transfer gate, the control between the memory block and the above read or write register is based on the timing signal created by the above serial clock. Creates and outputs a transfer request signal indicating that a data transfer is requested, and receives the timing signal of the other read or write asynchronously during the output period of the transfer request signal of one of the read or write. a transfer request signal generation section that generates and outputs the other transfer request signal after the data transfer is completed and the one transfer request signal is released; a counter unit that starts counting and determines a certain transfer control period, and generates and outputs a reference timing signal for opening the transfer gate and executing the transfer during this transfer control period; a row address strobe signal generation unit that receives the timing signal and generates a row address strobe signal during the transfer control period and outputs it to the memory block; a transfer signal generation unit that generates a transfer signal for executing data transfer between the memory block and the read or write register during a strobe signal output period, and outputs the signal to the transfer gate; and the timing signal from the counter unit. a transfer control period end signal generation unit that receives the transfer control period, generates a signal for canceling the one transfer request signal after the one transfer control period has elapsed, and outputs this signal to the transfer request signal generation unit. , An input/output asynchronous control device for a field memory, characterized in that two transfer gates between the field memory and the write register and read register operate during mutually different transfer control periods.