JPH033191B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to automatic simulator technology, and particularly to an automatic simulation device for aircraft radio navigation. BACKGROUND OF THE INVENTION The aviation industry has developed a special set of standard radio frequency navigation signals, generated by ground stations, that aircraft can process to determine their relative position. It's becoming like that. This signal is used not only for general navigation purposes, but also for instrument landings of aircraft under adverse weather conditions. One such signal is a very high frequency omnidirectional (VOR) signal. The VOR signal includes a carrier wave selected between 108 MHz and 116.5 MHz modulated with a 30 Hz and 9.96 KHz sound signal. The VOR signal is radiated from the transmitting station in all directions.
Each radial radiation line encompasses a predetermined phase relationship of the two sound signals. Therefore, an aircraft receiving a VOR signal should detect the relative phase of both sound signals and use a "lookup" table to determine the relative position indicated by the phase relationship of the sound signals. Accordingly, it is possible to determine its own position with respect to the transmitting station. Ground stations also typically transmit marker beacons. The marker beacon is used to modulate a 75MHz carrier wave.
A sound signal having a selected frequency. The frequency of this sound signal indicates to the aircraft its distance from a certain geographic point. For example, a 400Hz sound signal is transmitted when an aircraft is 3.22km from a city.
(2 miles) away, and a 1300Hz sound signal indicates that the aircraft is 1.61 Km (1 mile) from the city.
For example, it indicates that the distance is . When approaching an airport, a localizer signal and a glideslope signal are typically provided. The localizer signal typically includes a carrier wave selected between 108.1 MHz and 111.9 MHz modulated with 90 Hz and 150 Hz sound signals. Localizer signals are emitted from ground stations such that if the aircraft deviates to the right of its desired flight path, it will receive a high percentage of 150Hz sound signals, and if it deviates to the left, it will receive a high percentage of 90Hz sound signals. It's getting old. The sum of the amplitudes of both sound signals is always kept constant and their ratio determines the relative left/right position of the aircraft with respect to the runway centerline. The glide slope signal is also 90Hz and
327MHz or 327MHz modulated with a 150Hz sound signal
Contains selected carriers between 337MHz. As in the case of the localizer signal, the sum of the amplitudes of these two tone signals is always kept constant. However, in this case, the relative proportion of each tonal signal to the sum of both tonal signals is determined by the desired vertical glide path (Vertical
Figure 2 shows the vertical glide path of the aircraft relative to the glide path. That is, if the aircraft is above the desired vertical glide path it will receive a high percentage of 150Hz sound signals, and if it is too far below it will receive a high percentage of 150Hz sound signals.
receives a high proportion of sound signals. As can be readily appreciated, especially in commercial aviation, it is extremely important that an aircraft's radio navigation avionics be functional and properly calibrated. All prior art methods of testing and calibrating aircraft navigation avionics have been tedious and time consuming. The operator places a generator capable of generating any desired navigation signal near the antenna of the aircraft to be tested. The operator then sets the generator's mechanical switch so that the generator simulates the desired signal.
In other words, to simulate the VOR signal,
The operator sets the thumb rotary switch to correspond to the relative angle to the ground station being simulated. Marker beacons are generated by manually flipping a toggle switch to provide the appropriate sound signal to be generated. The glide slope and localizer signals are set mechanically by potentiometers. i.e. 90
2 with constant levels of Hz and 150Hz, respectively
A signal is applied across the potentiometer and the taps on the potentiometer are placed in the appropriate position.
Thereby, the two signals can be combined at any desired ratio while keeping the amplitude of the sum of the two signals constant. The above test method for navigation avionics of navigation aircraft is
Not only does it take a considerable amount of time to implement, it is prone to human error, and the operator must
It is not possible to set the switches at a speed that accurately simulates the speed at which navigation signals are received during normal operation of the aircraft. Therefore,
The above test method has inherent imperfections. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an automatic simulation device for air navigation signals. Another object of the present invention is to provide an automatic air navigation signal simulation system capable of generating navigation signals at a speed comparable to the speed at which navigation signals are normally received by aircraft in actual operation. Still another object of the present invention is to provide an automatic air navigation signal simulator for use in testing aircraft navigation equipment. Briefly, in the present invention, the glideslope, localizer,
A device is provided that can automatically simulate VHF omnidirectional guidance (VOR) and marker beacon signals. The apparatus includes a computer controller that can be programmed to provide a digital signal representative of: (a) a desired final glide slope value and an approach to the final glide slope value; (b) a desired final localizer value and a speed that should approach the final localizer value; (c) a desired final VOR value and a speed that should approach the final VOR value. The glide slope circuit includes a device for receiving a digital signal representative of a final value of glide slope and a speed at which the final value should be approached, and a device for generating the desired final value at the desired speed in response to the received signal. . The localizer circuit includes a device for receiving a digital signal representative of a final localizer value and a speed at which the final localizer value is to be approached, and a device for generating the desired final value at the desired speed in response to the received signal. The VOR circuit includes a device that receives a digital signal representing a final VOR value and a speed at which the final VOR value should be approached. The VOR circuit further includes a register device that receives and holds a final value signal, a speed register that receives and holds a speed signal that should approach the final value, and a current value of the VOR signal that is held in the speed register. a logic device for digitally changing the contents of a final value register up to a final value stored in the final value register at a rate determined by a signal; and a switching device for performing a switching operation in response to the state of the logic device. and a device that generates a predetermined VOR signal in response to the state of the switching device. Preferably, the computer controller is configured to be interconnected and in communication with the glide slope circuit, the localizer circuit, and the VOR circuit by a common bus. Each of the circuits is assigned a predetermined address for use by the computer, which uses the particular address to transmit the desired final value and speed to the respective circuit. [Embodiment of the Invention] FIG. 1 is a block diagram showing the structure of a preferred embodiment of the invention. The computer 10 generates signals on the output bus 12 according to the program,
When these signals are coupled to other parts of the equipment,
A specific signal will be generated at the desired rate. Preferably, the computer 10 is a commercially available Hewlett Packart.
A model 9845 computer is used. The output bus 12 of the Model 9845 computer includes 16 lines consisting of 8 data lines and 8 control lines. Given the information set forth below and the fact that the purpose of the device is to generate aircraft radio navigation signals for testing aircraft radio navigation equipment, one of ordinary skill in the art would For example, programming the computer 10 should be familiar. It should also be noted that computer 10 is suitably programmed to generate signals that accurately simulate signals received by an aircraft in flight. That is, by generating various signals at a predetermined speed, the computer can simulate conditions that an aircraft would actually experience. Output bus 12 of computer 10 is connected to interface circuit 14 . Interface circuit 14 is preferably a commercially available Fairchild model 4880 interface unit, which decodes information on the data lines of bus 12 onto the 40 output lines of output bus 1. do. Output bus 16 having 40 lines is connected in parallel to three circuits including each of localizer circuit 20 , glide slope circuit 22 , and VHF omnidirectional induction (VOR)/marker sound signal circuit 24 . The bus 16 includes respective boards 20, 22,
and 24 connectors 26, 28, and 30. Each circuit 2
0, 22, and 24 have in common that they each have address registers 32 and 24, respectively.
34, 36, speed registers 42, 44, 46, and final value registers 52, 54, 56. Each of these elements within any one circuit block is connected to the same lines of bus 16. Thus, for example, address registers 32, 34, and 36 in an embodiment of the invention are all connected to lines 3-6 of 40 line bus 16.
In addition, the speed registers 42, 44, and 46 are all
Connected to lines 11-18 of a 40-line bus 16, final value registers 52, 54, and 56 all
Connected to tracks 19-30 of 40 track bus 16,
The sound signal section of the VOR/marker sound signal circuit is line 16
is connected to lines 31 and 32 of. Computer 10 causes circuits 20 and 20 to
22, 24, the address signal being a predetermined sequence of numbers on line 3-6 of bus 16 corresponding to that circuit. For example, if the computer wants to call localizer circuit 20, the
Generates a signal 0001. The address of the glide slope circuit 22 is assigned 0010, and the address of the VOR/marker sound signal circuit 24 is assigned 0101. A circuit block will not respond to further commands from the computer unless it receives its address signal. Localizer circuit 20, which will be described in more detail with respect to FIG. 3 below, operates as follows. Upon receiving the appropriate address signal in address register 32,
Localizer circuit 20 inputs into its logic circuit 62 the final value from final value register 52 and the speed at which the final value should be approached from speed register 42 . The previous localizer value is held in logic circuit 62 where logic circuit 62 updates the previous value as determined by velocity register 42 up to the final value determined by final value register 52. digitally incremented at a rate of During this incrementing process from the initial value to the final value, the logic circuit 62 performs a digital conversion, which is generated by a conventional digital-to-analog converter 72 as an analog signal corresponding to the converter's output 82. Ru. This control signal originating from converter output 82 is provided to a control input of synthesis circuit 92. This synthesis circuit 92 is also supplied with a 90 Hz sound signal generated from block 102 and a 150 Hz sound signal generated from block 112. These two sound signals each have a certain predetermined level. Synthesizing circuit 92, in response to the control signal input on line 82, synthesizes the 90 Hz and 150 Hz tonal signals at a predetermined ratio, with the sum of the amplitudes of the two tonal signals always being kept constant. This composite signal, which can be considered as information about the normal localizer signal, is
2 and is fed via line 123 to a first input 131 of generator 130 . Glideslope circuit 22 operates in exactly the same way as localizer circuit 20, and when its address register 34 receives a correct address signal, logic circuit 64 responds by inputting the current value of the glide slope into final value register 54. the rate determined by the rate register 44 until the final value determined by the rate register 44. As a result, the logic circuit 64
The digital changes occurring at the output of are converted by digital-to-analog converter 74 to a corresponding analog signal, which is produced at converter output 84. This output is applied to the control input of synthesis circuit 94, which includes the 90 Hz sound signal generated from block 104 and the 150 Hz sound signal generated from block 114, and provides a composite signal output at its output 124. Occur. This composite signal is fed via line 125 to a second input 132 of generator 130 . The operation of the VOR/marker sound signal circuit block 24 is as follows. address register 36
When VOR receives a correct address signal, logic circuit 76, which holds the current value of the VOR signal in digital form, transfers this current value up to the final value determined by register 26, as determined by speed register 46. increase at a rate of The instantaneous digital changes made by logic circuits 76 corresponding to the desired VOR signals appear on respective output buses 86 and are provided to the inputs of orientation switching circuits 96, which will be described in more detail in conjunction with FIG. 5 below. Azimuth switching circuit 96 responds to signals on line 86 to actuate selected switches, thereby outputting output 126.
generates a switching sequence signal at the third input 133 of the generator 130 via the bus 127.
, the generator 130 will generate the desired VOR signal. In addition to generating a simulation of the desired VOR signal, circuit 24 can generate any one of several beacon marker tone signals. That is, if address register 36 receives an address signal corresponding to a desired marker tone signal, logic circuit 76 processes the digital signal through mode/tone signal register 140 in response to that tone signal. This activates the sound signal switching circuit 142. The sound signal switching circuit 142 receives three signals generated from blocks 143-145 corresponding to each beacon sound signal used.
Two different sound signals are provided. Sound signal switching circuit 142 is responsive to logic circuit 76 to
A selected one of the two tone signals 143-145 is provided on output line 146, which signal is further provided via bus 127 to generator 130. In this embodiment of the invention, generator 130
is equipped with a NAV401L generator commercially available from Instrument Flight Research. Generator 130 is inherently capable of generating any of the aforementioned signals in response to mechanical switches on the front panel of the generator. Thus, for example, a series of thumb rotary switches may be set between 0 degrees and 360 degrees, and when set, a corresponding VOR signal is generated.
Further, the generator 130 includes potentiometers corresponding to the localizer signal and the glide slope signal, respectively, and a 90 Hz sound signal and a 150 Hz sound signal at a constant level are applied to both ends of each potentiometer. Thus, at the taps of these potentiometers a signal of constant amplitude is obtained, which is the sum of two signals with any desired ratio depending on the position relative to the ends of the tap. There is. As described below, in the embodiments of the present invention,
By modifying the circuit of the generator 130, the computer 1
0 has complete control over all signals generated from generator 130. moreover,
It is also noted that the 90 Hz and 150 Hz bitone signals shown in blocks 102, 112, 104, 114 can be generated internally within generator 130 along with beacon tone signals 143-145. You should be careful. In this way, modification generator 130 inputs 1
In response to the signals received at 31-133, the antenna output 150 generates a desired set of simulated radio navigation signals that are to be radiated and used to test certain aircraft equipment. Figures 2A, 2B, and 2C are
1B is a diagram showing a detailed structure of the localizer circuit 20 shown in FIG. 1A and FIG. 1B. here,
The address bits carried by lines 3-6 of 40 line path 16 of FIGS. 1A and 1B are applied to pins 12-15 of integrated circuit 200. In these and subsequent figures, arrows extending from the lines represent connections to external circuitry and do not represent the direction of current flow. Integrated circuit 200 is a 10-to-1 decoder commercially available as TTL Part 7442. The binary address signal applied to input pins 12-15 is
It is converted to an equivalent decimal signal in decoder 200, thereby driving the corresponding one of the 10 output pins to the decimal state. In this example, the address of the localizer circuit is 0001
, which corresponds to the decimal number 1. Therefore, upon receiving the correct address signal, decoder 2
Pin 2 of 00 is driven to a low state. This state is coupled through switch 2 to inverter 202 which inverts the low level to a high state and supplies it to pin 1 of OR gate 204. The other input to pin 2 of OR gate 204 is at a low level because the decimal 8 appearing at pin 10 of decoder 200 is at a high level and is inverted to a low state by inverter 206. Therefore, orgate 2
The output at pin 3 of 04 will be high and is fed to pin 5 of OR gate 208 as its one input. OR gates 204 and 208 are both included in a Model 7432 integrated circuit.
The other input to pin 4 of OR gate 208 is the output from pin 1 of decoder 200 inverted by inverter 210 and is at a low level. Therefore, the output at pin 6 of OR gate 208 will be high and provided to pin 9 of AND gate 212. A second input pin 10 of AND gate 212 is applied with a transfer pulse appearing on line 33 of bus 16 . This transfer pulse is generated by the computer approximately 10 microseconds after the data is applied on the bus line.
This allows the data to be stabilized before being input to the circuit in response to the transfer pulse. In this manner, AND gate 212 generates a pulsed high level output on pin 8 in response to the transfer pulse. This pulsed high level signal is inverted to a low level by inverter 214 and then further inverted to a high level by parallel inverters 216 and 218. The purpose of inverters 216 and 218 is to allow high drive fanout. The pulsed high level outputs from inverters 216 and 218 are applied to one input, pin 1, of OR gate 220. The other input of OR gate 220, pin 2, is at a low level for the following reason.
That is, the outputs at pins 3 and 11 of decoder 200 are high, and they are inverted by inverters 222 and 224 and applied to the inputs of OR gate 226, pins 9 and 10, as low levels. Therefore, orgate 2
Pin 8, the output of 26, will be low and pin 12, the input of OR gate 228, will be low. This low level in combination with the low level at the other input, pin 13, causes its output, pin 11, to be in a low state. OR gates 204, 208, 226, and 228 are all implemented on a Model 7432 integrated circuit. The low level output of OR gate 228 is provided to pin 12 of AND gate 230, which is connected to pin 13 of AND gate 230.
Its output, pin 11, is brought low with the second output being low. This is then inverted by inverter 232 and further supplied to output point A via inverters 234 and 236 connected in parallel. In this way, input pin 1 of OR gate 220 goes high and input pin 2 goes low, producing a pulsating high level output at its output pin 3, which is connected to the storage register 240 pin. 8. Storage register 240, which is a type 74L95 integrated circuit, can be operated in either serial or parallel load mode. In this case, parallel load mode is desired, so pin 6 of this integrated circuit is connected to inverter 242.
-245 parallel array and biased to high level. In this way, data on lines 8, 9, 10 from the 40 line bus 16 is transferred to register 240.
When a transfer pulse is applied to pin 8 of , it is transferred to its output pins 10, 12, and 13, respectively. In localizer-only mode, 40 track buses 1
Line 10 of 6 is at high level and resistor 240
Set pin 13 to high level. This high level is reversed by inverter 246, causing three buffer stages 247-249 to operate at a low level, thereby causing the current in relay coils 250-252 to close switch contact pairs 253-255, respectively. . When these switches are closed, the NAV connected via output lines 48-53
Appropriate changes occur within the -401L generator, which will be detailed below. Switch pair 253-2
As a result of closing 55, inside the NAV-401L generator,
A localizer crystal controlled carrier frequency signal is generated. If track 9 of bus 16 is at high level,
This indicates glide slope mode, and pin 12 of resistor 240 goes high, which is inverted by inverter 260, resulting in coils 264-26 by buffers 261-263.
A drive current of 6 will cause switch contacts 267-269 to close. If you modify the NAV-401L generator as described below, switch contact 267-
The closure of 269 causes the generator to generate a crystal controlled glide slope carrier frequency signal via output pins 45-47. Finally, if line 8 of the 40 line bus 16 were to go high at the same time that line 9 went high, pin 10 of resistor 240 would go high, which would be driven low by inverter 270. level, activating relay coil 274 via buffer 272, thereby closing switch contact 275. This contact is connected to the NAV-401L generator via lines 43 and 44, resulting in the generation of both localizer and glide slope crystal control carrier signals. The pulsed high level outputs of inverters 216 and 218 are also provided to pin 8 of registers 280-284. These types of pins 6 of each of resistors 280-284 are driven high by inverters 242-245.
Each of the 74L90's registers will operate in a parallel manner. The inputs of registers 280 and 281 receive the localizer speed control bits appearing on lines 11-18 of bus 16. register 280,2
Upon receiving a transfer pulse on input pin 1, each of 81 loads the data bits applied to its inputs in parallel to the divisor inputs of a pair of Type 7498 divider ICs 290, 291. In this way,
The first divider 292 is loaded with a decimal number corresponding to the first desired divisor N1, and similarly the second divider is loaded with the second divisor N2. The input pin 9 of the first divider 290 has a model 555
500Hz generated from multivibrator IC292
A waveform of is applied. As is well known, in this IC, external elements 293, 294, and 295 are selected so that a 500 Hz waveform is generated at output pin 3. In this way, the 500 Hz waveform appearing at input pin 9 of first divider 290 is divided by first divisor N1 and output to output pin 5. This frequency-divided signal is applied to input pin 9 of second divider 291. In the second divider 291 this signal is divided by the divisor N2 and appears at the output pin 6. Overall, therefore, the 500Hz signal will be divided by the divisor N=N1×N2. A divided signal having a frequency of (500/N) Hz is applied to pin 2 of AND gate 300 and pin 5 of AND gate 302. ANDGATE 300,3
02 is included in the model 7408IC along with AND gates 212 and 230. and gate 300,
The inputs to other input pins 1 and 4 of 302 are determined by the outputs at pins 12 and 13 of a comparator delay consisting of a type 74L85 comparator IC 310-312. Comparators 310-312 are connected as shown to compare the numbers loaded into registers 212-284 with the current count values of binary counters 320-322. The numbers loaded in registers 282-284 are the numbers loaded in registers 282-284 for lines 19-2 of 40-line bus 16.
is the desired final value of the localizer signal appearing on 30. The numbers held in counters 320-322 also correspond to the current value of the localizer signal. Thus, if the computer is programmed to change the localizer signal, it loads the desired final values into registers 282-284. Comparator 310-
312 stores this desired new value in counter 320
-322 and if the desired value is greater than the current value, the comparator 3
The output at pin 13 of comparator 312 goes high, and if the desired new value is less than the current value, the output at pin 12 of comparator 312 goes high. If the new desired final value is greater than the current value, the AND gate 300
The Hz signal is sent to the count up input pin 5 of the counter 320 via an inverter 330. In this way, counter 320 has its output pin 1
It increases with the carry output appearing at 2, which is fed to the carry input of counter 321. In response, the carry output of counter 321 is loaded into the carry input of counter 322. In this way, the counter 320-3
22 counts up at a rate determined by the divisor N to the value requested by the computer. If the desired minimum value requested by the computer is less than the current value in counters 320-322, then
AND gate 302 outputs a (500/N) Hz signal,
It is fed through an inverter 332 to the countdown input of counter 320. The resulting borrow output of counter 320 is applied to the countdown input of counter 321, and similarly, the borrow output appearing at pin 13 of counter 321 is applied to countdown input pin 4 of counter 322. Thus, in this case the contents of the desired counter are reduced to the desired final value. The instantaneous value of the digitized localizer signal is constantly monitored by input pins 1-12 of digital-to-analog converter 340. Digital to analog converter 34 in this embodiment of the invention
0 is Burr Brown model number
Consists of DAC80CVI-V module. As stated in the Instructions for Use for this module, various external components, shown generally at 250, are used to gain adjust and zero adjust the analog signals appearing at output pins 15 and 18 of this unit. used. In this manner, the value of the analog signal appearing on output line 350 is directly proportional to the instantaneous value of the digitized localizer signal present within counters 320-322. This analog value is fed to a synthesis circuit detailed in connection with FIG. When the computer addresses the glide slope circuit, it generates a corresponding address signal 0010 on lines 3-6 of the 40 line bus 16. Similar to the case in which pin 2 of decoder 200 was activated by the localizer address in the above description, this in turn activates pin 3 of decoder 200 and a pulsed high level signal is sent to point A. appears in It should also be noted that the 500 Hz timing signal is coupled to the glide slope circuit of FIG. 3 via point B. This address logic structure has substantial flexibility in application to all devices. for example,
The device can be expanded to include two NAV-401Ls, one dedicated to generating VOR and marker beacon signals and one dedicated to generating ILS signals (localizer, glide slope). The NAV-401L, called Localizer 1/Glideslope 1, generates a unique frequency signal, while Localizer 2/Glideslope 2
Another called NAV-401L generates signals at different frequencies. This structure allows testing of aircraft that require simulation of different signals and allows for the selection of a backup unit in case of generator failure or interference on the selected frequency. . The address format for the localizer/glideslope is as follows.

[Table] Switch S1 has a localizer address of 10
Allows you to change from base 1 to decimal 3.
Switch S2 has a similar function for the glideslope address, which is decimal 2 and decimal 4. This allows a general purpose printed circuit (PC) board to be constructed, which when used in the device can act as a switch. Pin 10 of IC200 is connected to pin 5 of IC206, and since pin 10 of IC200 corresponds to decimal number 8, the address signal corresponding to decimal number 8 on bus 16 causes the PC board assigned to localizer 1 to It can be seen that the PC board assigned to the localizer 2 and the PC board assigned to the localizer 2 respond simultaneously, so that the control of the two signal generators can be performed simultaneously. IC200 is
Upon receiving decimal 8, pin 10 of IC 200 goes to a low state. This low level is IC206
is input to pin 5 of the
A high level input is applied to pin 2 of IC 204. From this point on, everything works as described above, except that in this case it happens on two PC boards at the same time. The above holds true for the glide slope portion of the address as well, but in this case the address signal on the input bus 16 is a decimal number 9,
IC200 produces a low level output on pin 211,
Thereby, from the inverter 224 to the OR gate 2
A high level signal will be sent to pin 9 of 26. The other glideslope addressing functions operate in the same manner as described above, the only difference being that in this case it occurs on two PC boards at the same time. In "all calls" address mode, 10
A base 0 (zero) is input on lines 3-6 of bus 16. This allows the IC200 on the two PC boards to
A low level output is generated on pin 1 of the This low level is inverted to high level by IC210,
It will be input to pin 4 of IC 208 and pin 13 of IC 228 to address the localizer and glide slope on both PC boards simultaneously. In this way, the first and second localizers and the first and second glide slopes are controlled simultaneously by common velocity and amplitude commands. FIG. 3 is a diagram showing the detailed structure of the glide slope circuit 22 of FIGS. 1A and 1B.
In this circuit, as in the localizer circuit of FIGS. 2A-2C, the transfer pulse at point A is connected to a series of type 74L95 registers 401-405.
is coupled to pin 8 of. These registers are formed by inverter bank 408 and are connected to pin 6 of each of registers 401-405.
A high level input applied to
Mode biased. As in the previous case, track 11 of 40 track bus 16
-18, the desired speed appears on divider 410,4
11 and thereby supplied from point B appears at output pin 6 of divider 411, appropriately divided by the net divisor N. This frequency divided signal is applied to the inputs of AND gates 412 and 413. The other inputs of AND gates 412 and 413 are controlled by the output from a comparator delay that includes three comparators 420-422. Comparator 420
-422 loads the desired glide slope final value loaded into registers 403-405 from lines 19-30 of 40-line bus 16 into counters 431-4.
Compare with the current glide slope digital value contained within 33. Just as in the localizer circuits described in connection with FIGS. 2A-2C, if the predetermined final glide slope value determined by the computer is greater than the current value in counters 431-433; AND gate 412 is activated to sequentially increment counters 431-433 to the desired value. If the desired final value is less than the current value, AND gate 413 becomes active, causing counters 431-433 to decrease to the desired value. The speed at which the final value approaches is determined by the divider 410,
determined by the divisor loaded in 411. Also similar to that in the localizer circuit, the digitized instantaneous glide slope value is monitored by a digital-to-analog converter 450, which transmits a corresponding analog output signal on its output path 452. occurs in FIGS. 4A and 4B are diagrams showing detailed structures of the synthesis circuits 92 and 94 shown in FIGS. 1A and 1B. Composite circuit 9 in Figures 1A and 1B
A synthesis circuit used in a localizer such as 2 and a synthesis circuit used in a glide slope such as synthesis circuit 94 have the same structure. Therefore, only the structure of a single composite circuit is shown. Some of the inputs to the synthesis circuit are provided from within the NAV-401L generator. That is, lines 500 and 502 receive constant levels of 90Hz and 150Hz sound signals from the generator. The amplitude of each sound signal is at the same fixed level. Also from the generator, a 5.5V reference level is received on line 504 and an 11V reference level is received on line 506. Line 3 from transducer 340 in the localizer circuit shown in FIGS. 2A-2C.
50 or converter 45 in the circuit shown in FIGS. 3A and 3B.
The analog output signal on line 452 from 0 is
It is fed via line 508 to the synthesis circuit. The fixed level 90 Hz and 150 Hz bitone signals are supplied to a pair of divider modules 520, 522, respectively.
is fed to pin 7, which is the Vz input of the railroad track 50
The analog signal on 8 is the divider module 520
is directly fed to pin 13, which is the Vy input of
A differential amplifier stage, indicated generally at 530, subtracts the analog signal on line 508 from the 11V reference level on line 506 and applies the result to pin 13, the Vy input of divider module 522.
The 5.5V reference level on line 504 is provided directly to pin 1, the Vx input of each of divider modules 520, 522. In addition, module 5
Also shown are offset circuits 536 and 537 for providing inputs to pins 5 of 20 and 522, respectively. The divider modules 520, 522 used in this embodiment of the invention are Burr-Brown
Burr Brown's Model 4302 divider, which is commonly commercially available. Dividers 520, 522 produce an output signal at pin 6, calculated by the equation Eout=Vy(Vz/Vx), in a known manner. In this way, the signal developed at pin 2 of divider module 520 is proportional to the product of the analog signal on line 508 and the 90 Hz signal on line 500;
The output at pin 2 of divider module 522, on the other hand, is proportional to the product of 11V minus the analog level on line 508 and the 150Hz signal level. These signals are passed through differential amplifiers 540 and 55
It is supplied to summing amplifiers 560 and 562 together with a DC error correction signal generated from 0, and added together. The functions of the differential amplifiers 540 and 550 are NAV
−5.5V DC reference level present in the 401L generator;
regeneration at the output of the synthesis circuit. Each amplifier 530, 540 used in various circuits,
550, 560 and 562 are commercially available LM308
It is an integrated circuit. Thus, the output of summing amplifier 560 is 90Hz
The output of summing amplifier 562 is proportional to the fixed 150Hz reference signal and the 11V to digital-to-analog converter output. It is proportional to the product of the signal subtracted. These two output signals are connected to summing resistors 563 and 5
64 to provide a composite signal output having a constant amplitude and containing both 90 Hz and 150 Hz signals in controlled proportions in response to the output of the digital-to-analog converter. This composite signal is thus viewed as a localizer or glide slope information signal, which is then communicated to the NAV-401L generator to modulate the appropriate carrier. 5A and 5B show the VOR marker sound signal circuit 2 shown in FIGS. 1A and 1B.
4 is a diagram showing the detailed structure of FIG. In this circuit, as in both the localizer and glide slope circuits, address signals are received from lines 3-6 of the 40 line bus 16. The address signal is type 74L85 comparator 60
0 inputs. This comparator detects equality and drives pin 3 high when the signal applied to input pins 10, 7, 2, 15 equals the signal present at input pins 11, 9, 1, 14. connected so that As shown, pins 11 and 14 have a high level input provided by inverter bank 602. Pins 9 and 14 are grounded. The standard address is 1010. For address input
When 1010 appears, equality is detected and pins 10 and 11 of NAND gate 604 go high. Thereafter, when a transfer pulse occurs on line 33, pin 9 of NAND gate 604 goes high, resulting in a constant level pulse at pin 8. This low level pulse is connected to a parallel inverter 606 which is used to increase fanout.
and reversed by 607, eight types
74L95 registers 610-617 at respective pins 8. Lines 7 and 8 of the 40 line bus 16 determine whether the four possible sound signal deviations are to be generated, line 9 determines whether the marker beacon is turned on, and line 10 determines whether VOR is turned on. If lines 7 and 8 are low, pins 9 and 10 of register 610 will be low. These low levels are provided to pins 15 and 14 of a one-of-ten decoder 630. Pin 1 of decoder 630 is
In response to the low level on pins 15 and 14, the low level is inverted by inverter 631 and buffered by driver 632 before being applied to pin 13 of switching IC 634. If track 7 of bus 16 becomes high level,
If track 8 remains at a low level,
Pin 15 of decoder 630 goes high and pin 14 of the decoder goes low. For these inputs, pin 2 of decoder 30 goes low, and this low level is inverted by inverter circuit 636 and buffered by drive circuit 637 before being applied to pin 5 of switching IC 634. . If line 7 of bus 16 is at a low level and line 8 of this bus is at a high level, pin 9 of register 610 will be at a low level while pin 10 will be at a high level. For these inputs,
Pin 3 of decoder 630 goes low, this low level is inverted by inverter 637 to go high, and then buffered by driver 638 before being applied to pin 6 of switching circuit 634.
is applied to In the last case, tracks 7 and 8 of bus 16
Both may be at high levels. In this case, pins 9 and 10 of register 610 will be high and pin 4 of decoder 360 will be low. This low level is inverted by inverter 639 and, after being buffered by buffer 640, drives pin 12 of switching circuit 634. Depending on the above four cases regarding the lines 7 and 8 of the bus 16, it is determined which of the four sound signals is to be generated. As described in detail below, switching circuit 634 generates a 1KHz sound signal when switching pin 13 is driven, and 400Hz, 1300Hz, and 3KHz when pins 5, 6, and 12 are driven, respectively. It is connected to the NAV-401L generator so that the sound signal is generated. This line 9 determines whether the marker tone signal is turned on. If line 9 is at a high level, pin 12 of register 610 will be at a high level, and this high level will be passed through buffers 641-643 to drive pins 13, 650 of switching circuit 650.
Drives 5 and 6. As will be described in detail below, switching circuit 650 is connected to the generator such that the marker tone signal is turned on when pins 13, 5, and 6 are activated. The line 10 of the bus 16 is the VOR in the generator.
Determine whether the circuit should be enabled. When line 10 goes high, register 61
0 pin 13 is driven high, which drives pin 12 of switching circuit 650 and pins 13, 5 of switching circuit 655 through buffers 651-653. The circuitry that determines the speed at which the desired final value of VOR heading is approached is virtually identical to the circuitry described with respect to the localizer and glide slope circuits. In particular, the 500 Hz signal generator, generally designated 660, is a type 555 integrated circuit 66
1 and a total of 66 to determine the oscillation frequency.
and associated timing circuitry shown at 2. At pin 3 of the model 555 integrated circuit 661,
A 500Hz signal is generated. This signal is divided by divider 6
18 input pins 9. A first divisor N1 is loaded into the divider 618 from the register 611. Therefore, the 500Hz signal is divided by the divisor N1 and sent to the second divider 6 via the output pin 5.
19 input pin 9. Second divider 61
9 contains the second
A divisor N2 is held. Register 611,6
Both divisors in 12 are the line 11- of the 40-track bus 16.
It was given from 18. In this way, the output signal generated at pin 6 of the second divider 619 is a 500Hz signal N=N1·
The signal is frequency-divided by the divisor N given by N2. This frequency-divided signal is supplied to pins 2 and 4 of a pair of NAND gates 670, 671. Tracks 19 to 32 of 40 track bus 16 are the final
Determine the VOR direction. The signals on these lines are loaded into registers 613-617, and when the address circuit addresses the VOR, a series of comparators 620-623 loads the VOR stored in a series of BCD counters 680-683.
It is compared with the current value of heading. In this embodiment of the invention, these BCD counters consist of commercially available Type 74LS192 integrated circuits. The tracks 37 of the 40 track bus 16 are given computer power to indicate whether to approach the final value of the VOR heading clockwise or counterclockwise. That is, if line 37 is in a low state, pin 12 of register 617 will be low, a low level will appear on pin 3 of NAND gate 671, and a high level will appear on pin 1 of NAND gate 670 via inverter 690. Comparator chain 620-623 includes register 6
A high level is generated at pin 3 of the last comparator 623 only if the desired final value stored in counters 13-617 is exactly equal to the current value in counters 680-683. The state of pin 3 of comparator 623 is monitored by pin 13 of NAND gate 670 and pin 5 of NAND gate 671. The operation of the VOR direction circuit is as follows. The desired new orientation value determined by the computer is
Loaded into registers 613-617. The computer also drives line 37 of bus 16 high or low to determine whether the new heading value should be approached clockwise or counterclockwise. If the desired final value is different from the current VOR value, pin 3 of comparator 623 will be low; if a clockwise approach to the final heading value is desired, pin 2 of NAND gate 670 will be low. As a result, its pin 12 goes high, which causes counters 680-683 to begin incrementing counts at (500/N) Hz. Similarly, if the final value is to be approached counterclockwise, pin 3 of NAND gate 671
becomes a low level, and pin 4 of the first counter 680
is driven and the counts of the counters are decremented. The counts of counters 680-683 continue to increment or decrement until the current value in the counter is exactly equal to the desired final value stored in registers 613-617, at which point comparator 623 Pin 3 of is driven high, which is inverted by inverter 691 and fed to NAND gates 670 and 671, resulting in
There will be no count up or count down signals to counters 680-683. FIG. 9 shows the modifications to be made to FIGS. 5A and 5B to limit the count range from 0 degrees to 360 degrees. As known, 74LS192
If a decimal type counter is arranged as shown in FIGS. 5A and 5B, the range of count up/count down will be 400 degrees from 0 degrees. U34 and U35 are 7485 type comparators;
It has been added between the outputs of U18 and U19. The "B" side of the comparator is wired for 360 degree input. Pin 6 of U30, which is the A=B output, is
5A and 5B through point "A" and to pin 14 of all 74LS192 counters, this connecting line is a clear line. In this way, the count of 360.0 degrees is U3
Output a high level to pin 6 of 5, thereby
All counters are forced to 0 degrees (zero). This operation (clearing operation) is designed to occur when the count is up or clockwise (cw). When counting down or counterclockwise (ccw) through 0 degrees (zero), a borrow occurs and registers U16-U19 will output 399.9 degrees. If this remains, A>B
The output, pin 5 of U35, goes high. This high level is fed to pin 2 of the Model 7400 NAND gate U36. On the next half cycle of the clock, pin 2 of U22 goes high and U36
A low level is output from pin 3 to pin 11 of all counters, resulting in a parallel load pulse for these counters. Pin 1 of these counters
5, 1, 10, and 9 are connected so that they are equal to 359.9 degrees. These counters are connected to pin 11
When it receives a load pulse, it is forced to 359.9 degrees and continues counting down (counterclockwise) to the target value as described above. given by counters 680-683
The instantaneous value of VOR heading is constantly detected and NAV−
Used to drive corresponding circuits within the 401L generator. That is, the current value of counter 680 is buffered by buffers 700-703 and input to input pins 6 and 12 of switching circuit 655.
and drives input pins 13 and 5 of switching circuit 710. The current value of counter 681 is buffered by buffers 711-714 and applied to pins 6 and 12 of switching circuit 710 and pins 13 and 5 of switching circuit 715. The current value of counter 682 is buffered by buffers 716-719 and drives pins 6 and 12 of switching circuit 715 and pins 13 and 5 of switching circuit 720. Finally, the current value of counter 683 is buffered by buffers 721 and 722 to drive pins 6 and 12 of switching circuit 720. Switching circuit 634, 650, 655, 7
10,715,720 is commercially available model CD4016AE
Consists of equipment. These devices require banks of pull-up resistors, one of which is shown at 730, each of which has a 15V supply coupled to its input pin. There is a metal oxide film (MOS) in the switching circuit.
A device is included and activated via an input pin, essentially closing a switch. The outputs of the switches are provided through output pins as shown and connected through terminals 43-74 of the output plug, generally designated 740. This plug is compatible with figures 6, 7, and 8.
Modified NAV as detailed in connection with the figure
Mated to the connector on the 401L generator. Figures 6, 7, and 8 show standard
Modifications to the NAV-401L generator are shown in detail. Figure 6 shows modifications to NAV-401L to automate VOR and marker beacon generation. A new connector has been added to NAV-401L,
Forms the interface between NAV-401L and the control PC board. Switch S7, which controls the VOR and marker beacon audible signals, is placed in the off position for automatic operation. Four conductors are added between this switch and the interface connector to allow control of the tone signals via bus 127 of FIGS. 1A and 1B. Switch S70
1 is a 3-segment switch that supplies the internal signal of the generator to the original NAV-401L circuit, allowing the generator to function as a marker beacon, VOR, localizer,
Set to glide slope or VHF communication generation mode. The inputs to the rotating parts of these switch segments are disconnected and connected to the interface. Also, only the parts of the switch segments that control the operation of the marker beaker crystal mode and the VOR crystal mode are connected to the bus connector of the interface. By this,
All VOR and marker beacon signals are automatically controlled and output, but no other mode is output under automatic control. Figure 8 shows the thumb rotary switch on the NAV-401L, which normally
Used to manually select the desired azimuth output using the format. Duplicate conductor wires are drawn out and connected to the automatic interface. In the automatic mode of operation, the switches are all set to the zero or "open" position and the closing is done by the CMOS switches 655, 710, 715, shown in FIGS. 5A-5D.
720. FIG. 7 shows a modification of NAV-401L to allow automatic control of the localizer and glide slope. 90Hz and 150Hz sound signals are manually controlled potentiometer R5 (localizer)
and is separated from R7 (glide slope) and supplied to the interface connector.
From here it is track 12 in Figures 1A and 1B.
3 and 125 as an input to the synthesizer printed circuit board. These signals are processed as described above and then sent back to the potentiometer in NAV-401L. Thereby, the potentiometer is used to zero out the tolerances of the aircraft receiver. Switch S701 is modified as described for the VOR/marker beacon case, except that control is now performed in localizer crystal mode and glide slope crystal mode. Both the VOR/marker and localizer/glideslope generators are equipped with jumper plugs as shown in Figures 6 and 7, which prevent internal modification when inserted into the interface connector. be disabled. By this,
The generator is disconnected from the automatic test equipment section and all functions of the generator can be used normally in manual mode. The above description completes the disclosure of the automatic simulation device for air navigation signals. Although the preferred embodiments of the invention have been described in detail, it is understood that many changes and modifications may be made thereto without departing from the true spirit and scope of the invention. should be recognized. [Effects of the Invention] As described above, according to the present invention, the glide slope signal, the localizer signal, and the VOR signal are automatically generated at the desired speed and up to the desired final value. It is possible to obtain a simulation device that can accurately generate navigation signals that vary at a speed comparable to the speed at which navigation signals are normally received by aircraft in actual operation.

[Brief explanation of drawings]

1A and 1B are block diagrams showing an embodiment of the radio navigation simulation apparatus of the present invention. FIGS. 2A, 2B, and 2C are diagrams showing detailed structures of the localizer circuits shown in FIGS. 1A and 1B. Third
Figures A and 3B are diagrams showing detailed structures of the glide slope circuits shown in Figures 1A and 1B. Figures 4A and 4B are
1A and 1B show a detailed structure of the synthesis circuit shown in FIGS. 1A and 1B; FIG. FIGS. 5A to 5D are diagrams showing detailed structures of the VOR circuits shown in FIGS. 1A and 1B. 6th
The figure is a schematic diagram showing modifications to the conventional NAV-401L generator that allow automatic control of the VOR and marker beacons. FIG. 7 is a schematic diagram showing modifications to the NAV-401L generator to enable automatic generation of localizer and glide slope signals. Figure 8 shows the NAV-
FIG. 4 is a schematic diagram showing modifications to 401L. FIG. 9 is a schematic diagram showing modifications to the circuit shown in FIGS. 5A-5D. In the figure, 10 is a computer, 20 is a localizer circuit, 22 is a glide slope circuit, 2
4 is VOR/marker sound signal circuit, 42, 44, 4
6 is a speed register, 52, 54, 56 are final value registers, and 62, 64, 76 are logic circuits. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. An automatic simulation device for an aircraft very high frequency omnidirectional guidance path VOR signal, which indicates a desired final value of the aircraft very high frequency omnidirectional guidance path signal and a speed at which the desired final value should be approached. control means for generating a digital signal; final value register means for receiving and holding the final value signal; speed register means for receiving and holding the speed signal; and the aircraft VHF omnidirectional guidance. holding the current value of a path signal and digitally varying its contents up to said final value stored in said final value register means at a rate determined by the signal held in said rate register means; switching means for operating a predetermined switch in response to a state of said logic means; and for generating a predetermined aircraft VHF omnidirectional guidance path signal in response to a state of said switching means. An apparatus for automatically simulating air navigation signals, comprising: means for simulating air navigation signals; 2. The logic means comprises a counter means for storing the instantaneous value of the aircraft VHF omnidirectional guidance path signal, the counter means being operable to increase or decrease the count value, and the counter means further comprising comparison means for comparing the instantaneous value of the aircraft VHF omnidirectional guidance path signal stored in the desired final value stored in the final value register means; operating said counter means at a speed determined by said speed signal stored in said register means, thereby increasing or increasing the count value of said counter means if the desired final value and said instantaneous value are different; 2. An apparatus for automatically simulating aeronautical navigation signals as claimed in claim 1, wherein said instantaneous value is varied towards said desired final value. 3. The logic means further comprises: a fixed frequency speed oscillator for generating a constant frequency speed signal f _r ; and a divisor _N determined by a speed signal stored in the register means; dividing means for generating a signal with a frequency f _r /N by dividing the frequency by; coupling the signal with the divided frequency f _r /N to the counter means to control the rate of change of the count value; 3. An automatic simulation device for air navigation signals according to claim 2, further comprising means for simulating aeronautical navigation signals. 4. The automatic simulation device is further capable of automatically simulating aircraft marker beacon sound signals, each of the sound signals representing a distance between the aircraft and a reference position, the simulation device further comprising: control means including means for generating a digital signal representing a desired marker beacon sound signal; marker beacon sound signal register means for storing said marker beacon sound signal; 2. The automatic air navigation signal simulation apparatus according to claim 1, further comprising means for coupling to beacon sound signal generating means and for causing said sound signal generating means to generate a desired sound signal.