JPH02216480A - Automatic simulation apparatus for navigation signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to automatic simulator technology, and particularly to an automatic simulation device for aircraft radio navigation.

BACKGROUND OF THE INVENTION The aviation industry has developed a special set of standard radio frequency navigation signals generated by ground stations that allow aircraft to determine their relative position by processing them. There is. This signal is used not only for navigation purposes, but also for instrument landings of aircraft under adverse weather conditions.

One such signal is very high frequency omnidirectional guidance (VO
R) There is a signal. VOR signal is 30H2 and 9.9
6 contains a carrier wave selected between 108 MHz and 116.5 MHz modulated with a Hz sound signal. The VOR signal is radiated from the transmitting station in all directions, with each radial line of radiation encompassing a predetermined phase relationship of the two sound signals. Therefore, an aircraft receiving a VOR signal detects the relative phase of both sound signals and uses a "lookup" table to determine the relative position indicated by the phase relationship of the sound signals.
It is possible to determine its position relative to the transmitting station.

The ground station also typically sends a marker beacon (marker beacon).
beacon) is transmitted.

The marker beacon is a sound signal with a selected frequency to modulate a 75 MHz carrier. The frequency of this sound signal indicates to the aircraft its distance from a certain geographic point.

For example, a 400Hz sound signal is transmitted from the city where the aircraft is located.
．． Indicates that it is 22km (2 miles) away,
The 1300Hz sound signal is 1.61K from the city the aircraft is flying from.
m (1 mile) distance, etc.

When approaching an airport, a localizer signal and a glideslope signal are typically provided. The localizer signal is typically modulated with 90Hz and 150Hz sound signals,
It includes carriers selected between 108.1 MHz and 111.9 MHz. The localizer signal is emitted from a ground station such that if the aircraft deviates to the right of its desired flight path, it will receive a high percentage of the 150 Hz sound signal, and if the aircraft deviates to the left, it will receive a high percentage of the 90 Hz sound signal. It has become. The sum of the amplitudes of both sound signals is always kept constant and their ratio determines the relative left/right position of the aircraft with respect to the runway centerline.

The glide slope signal is also 90Hz and 150Hz.
327MH2 to 337MHz modulated with Hz sound signal
Contains a selected carrier between MHz. As in the case of the localizer signal, the sum of the amplitudes of these two tone signals is always kept constant. However, in this case, the relative proportion of each tonal signal to the sum of both tonal signals depends on the desired vertical glide bus (Vertical glide pat
h) shows the vertical glide bus of the aircraft for That is, if the aircraft is above the desired vertical glide bus it will receive a high percentage of 150 Hz sound signals, and if it is too far below it will receive a high percentage of 90 Hz sound signals.

As can be readily appreciated, especially in commercial aviation, it is extremely important that an aircraft's radio navigation avionics be functional and properly calibrated. Prior art methods for testing and calibrating aircraft navigation avionics have all been tedious and time consuming. The operator places a generator capable of generating any desired navigation signal near the antenna of the aircraft to be tested. The w1 author then sets the generator's mechanical switch so that the generator simulates the desired signal. That is, V.O.
To simulate the R signal, the operator sets the thumb rotary switch to correspond to the relative angle to the ground station being simulated. Marker beacons are generated by manually activating a toggle switch to provide the appropriate sound signal to be generated. The glide slope and localizer signals are set mechanically by potentiometers. That is, two signals having constant levels, 90H2 and 150Hz, respectively, are applied across the potentiometer, and the taps of the potentiometer are placed at appropriate positions. Thereby, the two signals can be combined at any desired ratio while keeping the amplitude of the sum of the two signals constant.

The above test method for navigation avionics of a navigation aircraft not only requires a considerable amount of time to perform, it is also prone to human error, and operators cannot receive navigation signals during normal operation of the aircraft. It is impossible to set the switches at a speed that accurately simulates the speed. Therefore, the above test method has inherent imperfections.

SUMMARY OF THE INVENTION The present invention therefore aims to provide an automatic simulation device for air navigation signals.

Another object of the present invention is to provide an automatic air navigation signal simulation device that can generate navigation signals at a speed comparable to the speed at which navigation signals are normally received by aircraft actually in operation.

Still another object of the present invention is to provide an automatic air navigation signal simulator for use in testing aircraft navigation equipment.

In simple terms, the present invention uses the glideslope, localizer, and VHF signals normally received by an aircraft.
One device is capable of automatically simulating omnidirectional guidance (VOR) as well as marker beacon closing signals.
It will be ained. The device includes a computer control device that can be programmed to provide digital signals representative of: a)
a desired final glide slope value and the speed at which the final glide slope value should be approached; c) the desired final localizer value and the speed at which the final localizer value should be approached; c) the desired final VOR value and the speed at which the final VOR value should be approached. . The glide slope circuit includes a device for receiving a digital signal representative of a final value of glide slope and a speed at which the final value should be approached, and a device for generating the desired final value at the desired speed in response to the received signal. . The localizer circuit includes apparatus for receiving a digital signal representative of a final localizer value and a speed at which the final localizer value is to be approached, and apparatus for generating the desired final value at the desired speed in response to the received signal. The VOR circuit is the final VO
Apparatus is included for receiving a digital signal representative of the R value and the rate at which the final VOR value is to be approached.

The VOR circuit further includes a register device that receives and holds a final value signal, a speed register that receives and holds a speed signal that should approach the final value, and holds a current value of the VOR signal;
A logic device that digitally changes its contents to a final value stored in a final value register at a rate determined by a signal held in a speed register, and a switching operation responsive to the state of the logic device. and a device that generates a predetermined VOR signal in response to the state of the switching device.

Preferably, the computer controller is configured to be interconnected and in communication with the glide slope circuit, the localizer circuit, and the VOR circuit by a common bus. Each of the circuits is assigned a predetermined address for use by the computer, and the computer uses that particular address to transmit the desired final value and speed to the respective circuit.

[Embodiment of the Invention] FIG. 1 is a block diagram showing the structure of a preferred embodiment of the invention. Computer 10 generates signals on output bus 12 in accordance with the program, and when these signals are coupled to other parts of the device, particular signals will be generated at the desired rate.

Preferably, the computer 10 is a commercially available Hewlett Packart.
A Model 9845 computer is used. Model 9845
The output bus 12 of the computer includes 16 lines consisting of 8 data lines and 8 control lines. Given the information below and the fact that the purpose of the device is to generate an aircraft radio navigation signal for testing the aircraft's radio navigation equipment, a person of ordinary skill in the art would understand that For example, you should be familiar with programming the computer 10. It should also be noted that computer 10 is suitably programmed to generate signals that accurately simulate signals received by an aircraft in flight. That is, the computer
By generating various signals at scheduled speeds,
It is possible to simulate the set of conditions that an aircraft would experience on a real deer.

Output bus 12 of computer 10 is connected to interface circuit 14 . The interface circuit 14 is preferably a commercially available Fairchild.
A model 4880 interface unit from A.H.H.I.D.
The 40 output lines of the output bus 1 are decoded.

Output bus 16 having 40 lines is connected in parallel to three circuits including each of localizer circuit 20 , glide slope circuit 22 , and VHF omnidirectional induction (VOR)/marker sound signal circuit 24 . Bus 16 connects each board 20.22 and 24 connectors 26.28
, and 30. What is common to each of the circuits 20, 22 and 24 is that they each have an address number register 32, 34.
．． 36, speed registers 42, 44.46, and final value registers 52, 54.56. any 1
Each of these elements within the circuit block is connected to bus 16
connected to the same lines. That is, for example, address registers 32, 34, and 36 in an embodiment of the invention are all connected to lines 3-6 of 40 line bus 16.

Also, speed registers 42, 44, 46 are all connected to lines 11-18 of 40-track bus 16, and final value registers 52, 54, and 56 are all connected to lines 11-18 of 40-track bus 16.
The sound signal section of the VOR/marker sound signal circuit is connected to the lines 31 and 32 of the line 16.

Computer 10 addresses a particular one of circuits 20.22.24 by outputting an appropriate address signal on output bus 12, which address signal is applied to line 3 of bus 16 corresponding to that circuit. -6 is a predetermined sequence of numbers. For example, if the computer wants to call localizer circuit 20, lines 3-6 of bus 16
A signal of 0001 is generated on the top. 0010 is assigned to the address of the glide slope circuit 22, and 0101 is assigned to the address of the VOR/marker sound signal circuit 24. A circuit block will not respond to further commands from the computer unless it receives its address signal.

LOCALIZER CIRCUIT 20, DESCRIBED IN MORE DETAIL IN CONNECTION WITH FIG.
works like this: Upon receiving the appropriate address signal in address register 32, localizer circuit 20
inputs into its logic circuit 62 the final value from the final value register 52 and the speed at which the final value should be approached from the speed register 42. A previous localizer value is held within logic circuit 62 where logic circuit 62 advances the previous value at a rate determined by rate register 42 to a final value determined by final value register 52. Increase digitally. In this process of increasing from the initial value to the final value, the logic circuit 62 performs a digital conversion;
This is done by an ordinary digital-to-analog converter 72.
It is generated as an analog signal corresponding to the output 82 of the converter.

This control signal originating from converter output 82 is provided to a control input of synthesis circuit 92. This synthesis circuit 92 also receives a 90Hz sound signal generated from the block 102,
A 150 Hz sound signal generated from block 112 is supplied. These two sound signals each have a predetermined level.

Synthesizing circuit 92, in response to the control signal input on line 82, synthesizes the 90 Hz and 150 Hz bitone signals at a predetermined ratio, with the sum of the amplitudes of the bitone signals always being kept constant. This composite signal, which may be thought of as information about the normal localizer signal, is generated at output 122 and is
3 to the first human power 131 of the generator 130.

Glideslope circuit 22 operates in exactly the same manner as localizer circuit 20, and when its address register 34 receives a correct address signal, logic circuit 64 responsively transfers the current value of the glide slope to final value register 54.
is increased at a rate determined by rate register 44 to a final value determined by . Thereby, digital changes occurring at the output of logic circuit 64 are converted by digital-to-analog converter 74 into a corresponding analog signal, which is produced at converter output 84. This output is applied to a control input of a synthesis circuit 94, which combines the 90H2 sound signal generated from block 104 and the 90H2 tone signal generated from block 11
4 and a 150 Hz sound signal generated from the output signal 124 to generate a composite signal output at its output 124. This composite signal is
A second power source 132 of a generator 130 is supplied via a line 125.

The VOR/OR/marker sound signal lob block 24 is as follows. When the address register 36 receives the correct address signal, the logic circuit 76 holding the current value of the VOR signal in digital form transfers this current value to the speed register 4 to the final value determined by the register 26.
Increase at a rate determined by 6. logic circuit 76
The instantaneous digital changes made by the VOR signals corresponding to the desired VOR signals appear on respective output buses 86 and are fed to orientation switching circuits 96, which will be described in more detail in connection with FIG. 5 below. Azimuth switching circuit 96 actuates selected switches in response to the signal on line 86, thereby producing a switching sequence signal at output 126, which is transmitted via bus 127 to the third input of generator 130. 133, generator 130 generates the desired VOR
It will generate a signal.

In addition to generating a simulation of the desired VOR signal, circuit 24 may generate any one of several beacon marker tone signals. That is, if address register 36 receives an address signal corresponding to a desired marker tone signal, logic circuit 76 processes the digital signal through mode/tone signal register 140 in response to that tone signal. As a result, the sound signal switching circuit 1
42 is activated. Sound signal switching circuit 14
2 are supplied with three different sound signals originating from blocks 143-145 corresponding to each beacon sound signal used. Sound signal switching circuit 142 is responsive to logic circuit 76 to provide a selected one of three sound signals 143-145 to output line 146, which signal is further transmitted via bus 127 to generator 130. supplied to

In this embodiment of the invention, generator 130 is an instrument flight research engine.
nt Flight Research). Generator 13
0 was originally capable of generating any of the above-mentioned signals in response to mechanical switches on the front panel of the generator. Thus, for example, a series of thumb rotary switches can be set between 0 degrees and 360 degrees, and when these are set, the corresponding VO
An R signal is generated. Further, the generator 130 includes potentiometers corresponding to the localizer signal and the glide slope signal, respectively, and a 90 Hz sound signal and a 150 Hz sound signal at a constant level are applied to both ends of each potentiometer. Thus, at the taps of these potentiometers, a signal of constant amplitude is obtained, but this signal is the sum of the two signals with any desired proportion depending on the position relative to the ends of the tap.

As described below, in an embodiment of the invention, the generator 1
By modifying the circuit of 30, the computer 10 becomes the generator 13
To be able to completely control all signals generated from 0. Furthermore, blocks 102, 112, 1
90Hz and 150Hz shown in 04,114
It should also be noted that the rain sound signals can be generated internally within the generator 130 along with the beacon sound signals 143-145.

In this way, modification generator 130 provides input 131-1
In response to the signals received at 33, it generates at the antenna output 150 a desired set of simulated radio navigation signals which will be used to test the equipment of the aircraft being radiated.

FIGS. 2A, 2B, and 2C are diagrams showing the detailed structure of localizer circuit 20 shown in FIGS. 1A and 1B. Here, FIGS. 1A and 1B
The address bits carried by lines 3-6 of the 40 line bus 16 shown are applied to pins 12715 of the integrated circuit 200.

In these and subsequent figures, arrows extending from the lines represent connections to external circuitry and do not represent the direction of current flow. The accumulation outlet 200 is T
This is a 10-to-1 decoder commercially available as TL part 7442. The binary address signals applied to input pins 12-15 are converted to equivalent decimal signals in decoder 200, thereby driving the corresponding one of the ten output bins to a low state. In this example, the address of the localizer circuit is 0001, which corresponds to decimal 1. Therefore, upon receiving the correct address signal, the decoder 2
Pin 2 of 00 is driven to a low state. This state is coupled to the inverter 202 via switch 1,
Inverter 202 inverts the low level to a high level state and supplies it to pin 1 of OR gate 204. The other input to bin 2 of OR gate 204 is at a low level because the decimal 8 appearing at bin 10 of decoder 200 is at a high level and is inverted to a low state by inverter 206.

Therefore, the output produced in bin 3 of OR gate 204 is at a high level, which is supplied to bin 5 of OR gate 208 as its single power. orgate 204 and 2
08 are both included in a Type 7432 integrated circuit. Another input to bin 4 of OR gate 208 connects the output from pin 1 of decoder 200 to inverter 2.
It is inverted by 10 and is at a low level. Therefore, the output produced at pin 6 of OR gate 208 is:
It goes high and is supplied to pin 9 of AND gate 212. A transfer pulse appearing on the line 33 of the bus 16 is applied to the second input pin 10 of the AND gate 212 . This transfer pulse is generated by the computer approximately 10 microseconds after the data is applied on the bus line. This allows the data to be stabilized before being input to the circuit in response to the transfer pulse. In this manner, AND gate 212 generates a pulsed high level output on bin 8 in response to the transfer pulse. This pulsed high level signal is inverted to a low level by inverter 214 and then further inverted to a high level by parallel inverters 216 and 218. The purpose of inverters 216 and 218 is to allow high drive fanout.

The pulsed high level output from inverters 216, 218 is applied to one input, bin 1, of OR gate 220. Bin 2, the other input to OR gate 220, is at a low level for the following reason.

That is, the outputs at bins 3 and 11 of decoder 200 are high and are inverted by inverters 222 and 224 to be applied to the inputs of bins 9 and 10 of 226 at low levels. Therefore, the output of OR gate 226, Bin 8, will be low and the input of OR gate 228, Bin 12, will be low. This low level in combination with the low level in another human input, bin 13, causes its output, bin 11, to be in a low level state. or gate 20
4,208, 226, and 228 are all implemented on type 7432 integrated circuits.

The low level output of the OR gate 228 is the AND gate 230
This, along with a low level of second power to bin 13, causes its output, bin 11, to be at a low level. This is then inverted by inverter 232 and further supplied to output point A via inverters 234 and 236 connected in parallel.

In this way, input bin 1 of OR gate 220 goes high and input bin 2 goes low, producing a pulsating high level output on its output bin 3, which output goes to bin 240 of storage register 240. 8. Model 74
Storage register 240, consisting of an L95 integrated circuit, can operate in either serial or parallel load mode. In this case, parallel load mode is desired, so bin 6 of this integrated circuit is connected to inverter 242-2.
Biased high through 45 parallel arrays. In this way, tracks 8, 9.1 from 40 track bus 16
When a transfer pulse is applied to bin 8 of register 240, the data on 0 is transferred to its output bin 10.12.1, respectively.
Transferred to 3.

In localizer-only mode, 40 track buses 16
line 10 is at a high level, and bin 1 of register 240
Set 3 to high and set it to bell. This high level is inverted by inverter 246 and the three buffer stages 247-
249 is activated at a low level, so that the current in relay coils 250-252 flows through switch contact pairs 253-
255 are respectively closed. When these switches are closed, the NA connected via output line 4g-53
Appropriate changes occur within the V-401L generator, which will be discussed in more detail below. Switch pair 253-25517
) closure results in the generation of a localizer crystal controlled carrier frequency signal within the NAV-401L generator.

If line 9 of bus 16 is high, indicating glide slope mode, bin 12 of register 240 will be high and this will be inverted by inverter 260 so that the coils by buffers 261-263 264-266 drive current is connected to switch contact 26
7=269 will be closed. NAV-401L
If the generator is modified as described below, the switch contact 26
The closure of 7-269 causes the generator to generate a crystal controlled glide slope carrier frequency signal via output bins 45-47.

Finally, if track 8 of the 40 track bus 16 goes high at the same time as track 9 goes high, then
Bin 10 of resistor 240 goes high, which is inverted to low by inverter 270, energizing relay coil 274 through buffer 272, thereby closing switch contact 275. This contact is connected to the NAV-401L generator via lines 43,44, resulting in the generation of both localizer and glide slope crystal control carrier signals.

The pulsed high level output of inverters 216 and 218 is
It is also provided to the eighth bin of registers 280-284. Bin 6 of each of registers 280-284 is driven high by inverters 242-245, resulting in each of these type 74L90 registers operating in a parallel manner.

The inputs of registers 280 and 281 receive the localizer speed control bits appearing on lines 11-18 of bus 16. Upon receiving a transfer pulse at input bin 1, each of registers 280, 281 transfers the data bits applied to its inputs to a pair of Model 7498 divider ICs.
Load the divisor inputs of 290 and 291 in parallel. In this manner, the first divider 292 is loaded with the decimal number corresponding to the first desired divisor N1, and similarly the second divider is loaded with the second divisor N2.

A 500 Hz waveform generated from a model 555 multi-by-break IC 292 is applied to the manual power bin 9 of the first divider 290. As is known, in this IC, external elements 293, 294° and 295 are selected so that a 500 Hz waveform is generated in output bin 3.

In this way, the 500 Hz waveform appearing at the input pin 9 of the first divider 290 is divided by the first divisor N1 and output to the output bin 5. This frequency-divided signal is T
Applied to input pin 9 of S2 divider 291. In the second divider 291 this signal is divided by the divisor N2 and appears at the output bin 6. Therefore, overall, 5
The 00Hz signal will be divided by the divisor N-NlXN2.

The frequency-divided signal having a frequency of (500/N) Hz is applied to bin 2 of AND gate 300 and bin 5 of AND gate 302. AND gate 300° 302 is included in model 74081C along with AND gates 212 and 230. ANDGATE 300.302 Other manual bin 1
and 4 to 4, type 74L85 comparator IC310
Determined by the outputs in bins 12 and 13 of the comparator delay consisting of -312.

Comparators 310-312 are connected as shown to compare the numbers loaded into registers 212-284 with the current count values of binary counters 320-322.

The numbers loaded into registers 282-284 are the desired final values of the localizer signals appearing on lines 19-30 of 40-line bus 16. In addition, counters 320-322
The number held within corresponds to the current value of the localizer signal.

Thus, if the computer is programmed to encapsulate the localizer signal, it loads the desired final values into registers 282-284. Comparators 31o-312 compare this desired new value with the current location determined by counters 320-322, and if the desired value is greater than the current value, the output of bin 13 of comparator 312 goes high. and if the desired new value is less than the current value, comparator 3
The output of 12 bins 12 becomes high level.

If the new desired final value is greater than the current value, AND gate 300 sends the aforementioned (7)(500/N) Hz signal to count-up input bin 5 of counter 320 via inverter 330.

Thus, counter 320 increases with the carry output appearing in its output bin 12, which is fed into the carry power of counter 321.
. In response, the carry output of counter 321 is loaded into the carry output of counter 322. In this manner, the counters 320-322 count up at a rate determined by the divisor N to the value required by the computer.

Desired minimum value required by computer 32
If it is smaller than the current value within 0-322, AND gate 3
02 outputs a (500/N) Hz signal to the inverter 332.
to the countdown input of counter 320. This causes a debt of the counter 320 (bor
row) output is fed to the countdown input of counter 321, and similarly, the borrow output appearing in bin 13 of counter 321 is fed to countdown manual bin 4 of counter 322. Thus, in this case the contents of the desired counter are reduced to the desired final value.

The instantaneous value of the digitized localizer signal is constantly monitored by input bins 1-12 of the digital-to-analog converter 340. Digital-to-analog converter 340 in this embodiment of the invention is a Burr-Brown converter.
It consists of a type DAC80CV I-V module of R. Brown). As stated in the Instructions for Use for this module, various external components, shown generally at 250, are used to gain adjust and zero adjust the analog signals appearing on output bins 15 and 18 of this unit. used. In this way, the output line 3
The value of the analog signal appearing at counter 320-
322 is directly proportional to the instantaneous value of the digitized localizer signal present within 322. This analog value is fed to a synthesis circuit detailed in connection with FIG.

When the computer addresses the glide slope circuit, the combiator generates a corresponding address signal 0010 on lines 3-6 of the 40 line bus 16. In the above description, bin 2 of the decoder 200 is the localizer
This in turn causes bin 3 of decoder 200 to be activated, as if activated by the address;
A pulsed high level signal appears at point A. It should also be noted that the 5 DEG OHZ timing signal is coupled to the glide slope circuit of FIG. 3 through point B.

This address logic structure has substantial flexibility in application to all devices. For example, the device could be expanded to include a dedicated N for generating VOR and marker beacon signals.
AV-401L and ILS signal (localizer, glide slope) generation IJJTIa two NAV-40
1L can be included. A NAV-401L called Low Force Enhancer 1/Glideslope 1 generates a signal at a unique frequency, while another NAV-401L called Localizer 2/Glideslope 2 generates a signal at a different frequency. This structure allows testing of aircraft requiring the simulation of different signals, and also allows for the selection of a backup unit in case of generator failure or interference on the selected frequency. Become.

The address format for localive/glideslope is as follows.

Localizer 1 Glideslope 1 0 - Calizer 2 Glideslope 2 0 - Calizer I and 2 (simultaneously) Glideslopes I and 2 (simultaneously) All localizers and glideslopes (simultaneously) Human Power Bin (Bus 1B) Switch S1 is the localizer address decimal 1
It is possible to change from to decimal number 3. switch S
2 has a similar function for the glideslope address, which is decimal 2 and decimal 4.

This allows a general purpose printed circuit (PC) board to be constructed, which when used in a device can act as a switch.

Bin 10 of IC 200 is connected to bin 5 of IC 206, and since bin 10 of IC 200 corresponds to decimal number 8, the address signal corresponding to decimal number 8 on bus 16 causes the PC board assigned to localizer 1 to It can be seen that the PC board assigned to the localizer 2 simultaneously responds, and the t4I11 of the two l co signal generators are performed simultaneously and become 1. When IC 200 receives decimal 8, I
Bin 10 of C200 goes to a low level state. This low level is input into bin 5 of IC 206, thereby
A high level input is applied to bin 2 of OR gate 1c204. From this point on, everything works as described above, but
The only difference in this case is that it occurs on two PC boards at the same time.

The above holds true for the glide slope portion of the address as well, but in this case the address signal on input bus 16 is decimal 9 and IC 200 is in bin 21.
1, thereby producing a low level output at inverter 22.
4 will send a high level signal to OR gate 226 bin 9.

The other glideslope address functions operate in the same manner as described above, except that in this case they occur simultaneously on two PC boards.

In "all calls" address mode, decimal 0
(zero) is input to line 3-6 of bus 16. This produces a low level output on bin 1 of IC 200 on the two PC boards. This low level is inverted to a high level by IC210, and IC208 bin 4 and IC22
8 and bin 13, so that the localizers and glide slopes on both PC boards are addressed simultaneously. In this way, the first and second localizers and the first and second glide slopes are controlled simultaneously by common velocity and amplitude commands.

FIG. 3 is a diagram showing the detailed structure of the glide slope circuit 22 of FIGS. 1A and 1B.

In this circuit, as in the localizer circuit of FIGS. 2A-2C, the transfer pulse at point A is coupled to bin 8 of a series of Type 74L95 registers 401-405. These registers are formed by inverter bank 408 and are biased into parallel load mode by high level inputs applied to respective bins 6 of registers 401-405.

As in the previous case, tracks 11-18 of the 40 track bus 16
The desired speed appearing above is loaded into dividers 410 and 411, whereby the 500Hz signal supplied from point B is suitably divided by the net divisor N and sent to divider 4.
11 output bins 6. This frequency divided signal is applied to AND gates 412 and 413.

The other inputs of AND gates 412 and 413 are controlled by outputs from comparator delays that include three comparators 420-422. Comparators 420-422 compare the desired glide slope final values loaded into registers 403-405 from lines 19-30 of 40 track bus 16 with the current glide slope digital values contained in counters 431-433. compare.

Just as in the localizer circuits described in connection with FIGS. 2A-2C, if the desired final glide slope value determined by the computer is greater than the current value in counters 431-433, the AND gate 412 is activated, counter 431-4
33 is increased sequentially to the desired value. If the desired final value is less than the current value, AND gate 413 becomes active, causing counters 431-433 to decrease to the desired value. The speed at which the final value is approached is determined by the divisor loaded into the dividers 410, 411.

Also similar to that in the localizer circuit, the digitized instantaneous glide slope value is monitored by a digital-to-analog converter 450, which generates a corresponding analog output signal on its output line 452. do.

FIGS. 4A and 4-B are diagrams showing detailed structures of the synthesis circuits 92 and 94 shown in FIGS. 1A and 1B. A synthesis circuit used for a localizer, such as synthesis circuit 92 in FIGS. 1A and 1B, and a synthesis circuit used for a glide slope, such as synthesis circuit 94, have the same structure. Therefore, only the structure of a single composite circuit is shown.

Some of the power to the synthesis circuit is supplied from within the NAV-401L generator. That is, lines 500 and 502
is a constant level of 90Hz and 150H from the generator.
Receive the sound signal of z. The amplitude of each sound signal is at the same fixed level.

Also from the generator, a reference level of 5.5 volts is received on line 504 and a reference level of 11 volts is received on line 506. An analog output signal on line 350 from converter 340 in the localizer circuit shown in FIGS. 2A-2C or from converter 450 in the circuit shown in FIGS. 3A and 3B. The analog output signal on line 452 is provided to the synthesis circuit via line 508.

The fixed level 90 Hz and 150 Hz rain sound signals are each divided into a pair of divider modules 520° and 522 Vz.
It is supplied to bin 7 which has a large input. The analog signal on line 508 is fed directly to bin 13, which is the 77 input of divider module 520, while a differential amplifier stage, indicated generally at 530, feeds the analog signal on line 508 directly to bin 13, which is the 77 input of divider module 520. 11v reference level and apply the result to bin 13, which is 77 volts of divider module 522. The 5.5v reference level on line 504 is fed directly to Bin 1, the VX input of each of divider modules 520, 522. Note that the module 520,5
Also shown are offset circuits 536, 537 for providing inputs to each of the 22 bins 5.

The divider module 520,522 used in this embodiment of the invention is a Burr Bro
wn) model 4302 excluded! liL device, which is commonly commercially available.

The division 8520.522 is, as is known, the equation %formula%) An output signal calculated by is generated in bin 6.

In this way, the signal appearing on bin 2 of divider module 520 is the analog signal on line 508 and the analog signal on line 50.
0 and the 90 Hz signal on line 508, while the output produced at bin 2 of divider module 522 is proportional to IIV minus the analog level on line 508 and 150 Hz.
is proportional to the product of the signal level.

These signals are sent to summing amplifiers 560 and 5 along with DC error correction signals generated from differential amplifiers 540 and 550.
62 and are added together. Differential amplifier 540
．． The function of the 550 is to reproduce the 5.5v DC reference level present in the NAV-401L generator and at the output of the combining circuit. Each amplifier 5 used in various circuits
30°540.550, 560 and 562 are commercially available LM308 integrated circuits.

Thus, the output of summing amplifier 560 is proportional to the product of the 90Hz reference level input and the control signal from the digital-to-analog converter, while the output of summing amplifier 562 is proportional to the fixed 150H2 reference. It is proportional to the product of the signal and 11v minus the output signal of the digital-to-analog converter. These two output signals are summed at summing resistors 563 and 564 to produce a composite signal of constant amplitude and containing both 90 Hz and 150 Hz signals in controlled proportions in response to the output of the digital-to-analog converter. give the output. This composite signal is thus viewed as a localizer or glide slope information signal, which is then communicated to the NAV-401L generator to modulate the appropriate carrier.

5A and 5B are diagrams showing the detailed structure of the VOR marker sound signal path 2A shown in FIGS. 1A and 1B.

In this circuit, as in both the localizer and glide slope circuits, the address signal is
It is received from the line 3-6 of the line bus 16. Address signals are coupled to inputs of a Type 74L85 comparator 600. This comparator detects the equality when the signal applied to the manual pin 10, 7, 2.15 is equal to the signal present in the manual bin 11, 9, 1.14 and the bin 3
is connected so that it is at high level 1. As shown, bins 11 and 14 have a high level input provided by inverter panchromator 02. Bins 9 and 14 are grounded. The reference address is 1010. When 1010 appears on the address input, equality is detected and bin 1 of Nant gate 604
0 and 11 will be high levels. Thereafter, when a transfer pulse occurs on the line 33, the bin 9 of the Nant gate 604
goes high, resulting in a constant level pulse at pin 8. This low level pulse is inverted by parallel inverters 606 and 607, which are used to increase fanout, and is applied to bin 8 of each of the eight Type 74L95 registers 610-617.

Lines 7 and 8 of the 40vA road bus 16 determine whether the 1.4 possible sound signal deviations are to be generated, line 9 determines whether the marker beacon is turned on, and line 9 determines whether the marker beacon is turned on; 10 determines whether the VOR is turned on.

When lines 7 and 8 are low, register 61
Bins 9 and 10 of 0 will be low levels.

These low levels are processed by a one-on-ten decoder (10
1 decoder) 630 to bins 15 and 14. Bin 1 of decoder 630 goes low in response to the low level of bins 15 and 14, and this low level is inverted by inverter 631 and buffered by driver 632 before bin 1 of switching IC 634 goes low.
is applied to

If line 7 of bus 16 goes high and line 8 remains low, decoder 630
Bin 15 of the decoder goes high and bin 14 of the decoder goes low. For these inputs, bin 2 of decoder 30 goes low, and this low level is inverted by inverter circuit 636 and buffered by drive circuit 637 before being applied to bin 5 of switching IC 634.

If line 7 of bus 16 is at a low level and line 8 of this bus is at a high level, then bin 9 of register 610 will be at a low level while bin 10 will be at a high level. In these cases, bin 3 of decoder 630 goes low, this low level is inverted by inverter 637 to a high level, then buffered by driver 638 and then bin 6 of switching circuit 634.
is applied to

In the last case, both lines 7 and 8 of bus 16 may be at a high level. In this case, register 6
Bins 9 and 10 of 10 will be high and bin 4 of decoder 360 will be low. This low level is inverted by inverter 639 and, after being buffered by buffer 640, drives bin 12 of switching circuit 634.

Depending on the above four cases regarding the lines 7 and 8 of the bus 16, it is determined which of the four sound signals is to be generated. As will be described in detail later, the switching circuit 634 generates an IKHz sound signal when the switching bin 13 is driven, and 400Hz, 1300H, z, and 3
It is connected to a NAV-401L generator so that a KHz sound signal is generated.

This line 9 determines whether the marker tone signal is turned on. If line 9 is high, register 6
Bin 12 of 10 goes high, and this high level drives drive bins 13, 5.6 of switching circuit 650 via buffers 641-643. As described in detail below, switching circuit 650 connects bins 13. 5.6
The marker tone signal is connected to the generator so that the marker tone signal is turned on when the marker tone signal is activated.

Line IO of bus 16 determines whether the VOR circuit within the generator is to be enabled.

When line 10 goes high, bin 1 of register 610
3 is driven high, and this high level causes buffer 65
Bin 1 of switching circuit 650 via 1-653.
2 and the bins 13 and 5 of the switching circuit 655.

The circuitry that determines the speed at which the desired final value of VOR heading is approached is virtually identical to the circuitry described with respect to the localizer and glide slope circuits. In particular, the 500 Hz No. 13 generator, shown generally at 660, includes a type 555 integrated circuit 661 and associated timing circuitry, shown generally at 662, for determining the oscillation frequency. There is. Bin 3 of the Type 555 integrated circuit 661 produces a 500 Hz signal. This signal is
Provided to input pin 9 of divider 618. Divider 618
The first divisor Nl is loaded from the register 611 into the register 611.

The 500 Hz signal is therefore divided by the divisor N1 and fed via the output pin 5 to the input pin 9 of the second divider 619. The second divisor N2 loaded from the register 612 is held in the second divider 619. Both divisors in registers 611 and 612 are provided by lines 11-18 of 40 line bus 16.

In this way, the output signal produced at pin 6 of the second divider 619 is a 500 Hz signal divided by the divisor N given by N-81, N2. This frequency division number ti is supplied to pins 2 and 4 of a pair of Nant gates 670 and 671.

Lines 19-32 of the 40-line bus 16 determine the final VOR orientation. The signals on these lines are sent to register 613.
-617 and as the address circuit addresses the VOR, it is compared by a series of comparators 620-623 with the current value of the VOR orientation stored in a series of BCD counters 680-683. In this embodiment of the invention, these BCD counters consist of commercially available Type 74LS192 integrated circuits.

The tracks 37 of the 40 track bus 16 are given computer power to indicate whether to approach the final value of the VOR orientation clockwise or counterclockwise. That is, if line 37 is in a low state, pin 12 of register 617 will be low and Nant gate 67 will be in a low state.
A low level appears on pin 3 of 1 and a high level appears on pin 1 of Nant gate 670 via inverter 690.

Comparator chain 620-623 includes registers 613-6
The desired final value stored in counter 680-6
A high level is generated at pin 3 of the last comparator 623 only if it is exactly equal to the current value in 83. Comparator 62
The state of pin 3 of 3 is monitored by pin 13 of Nant gate 670 and pin 5 of Nant gate 671.

The operation of the VOR direction circuit is as follows. The desired new orientation determined by the computer is stored in register 613.
-617. The computer also uses bus 1
6 line 37 is driven high or low to determine whether the new heading value should be approached clockwise or counterclockwise. The desired final value is the current VORWi
, then pin 3 of comparator 623 will be low, and if a clockwise approach to the final heading value is desired, pin 2 of Nant gate 670 will be low, resulting in that pin 12 goes high, which causes counters 680-683 to begin incrementing counts at (500/N) Hz.

Similarly, if the final value is to be approached counterclockwise, pin 3 of Nant gate 671 goes low and pin 4 of first counter 680 is driven to cause the counts of the counters to decrement. It will be done. counter 680-68
The count continues to increment or decrement by 3 until the current value in the counter is exactly equal to the desired final value stored in registers 613-617, at which point pin 3 of comparator 623 is is driven to a high level, which is inverted by inverter 691 and supplied to Nant gates 670 and 671, resulting in counter 680-6.
Count up signal or count down to 83 t=
The number disappears.

FIG. 9 shows the modifications to be made to FIGS. 5A and 5B to limit the count range from 0 degrees to 360 degrees. As is well known, when the 74LS1912 decimal counter is arranged as shown in FIGS. 5A and 5B, the range of count up/down is 400 degrees from 0 degrees.

U34 and U35 are 7485 type comparators, and U18
and is added between the outputs of U19.

The rBJ side of the comparator is wired for 360 degree input. Pin 6 of U30, which is the A-B output, is at point rAJ
5A and 5B through all 7
It is connected to pin 14 of the 4LS192 counter,
This connection line is a clear line. In this way, 3
A count of 60.0 degrees causes pin 6 of U35 to output a high level, which forces all counters to 0 degrees (zero). This operation (clearing operation) is designed to occur when the count is up, that is, clockwise (CW). A countdown or counterclockwise (ccw) movement through 0 degrees (zero) results in a debt;
Registers U16-U19 now output 399.9 degrees. If this remains, U35 with A>8 output
Bin 5 of will be at a high level. This high level is model 740
0 is supplied to bin 2 of Nantes Gate U36. On the next half cycle of the clock, U22's bin 2 goes high and a low level from U36's bin 3 is output to bin 11 of all counters, resulting in a parallel load pulse for these counters. Bin 15 of these counters.
1. 10.9 is connected to be equal to 359.9 degrees. These counters are forced to 359.9 degrees when bin 11 receives a load pulse and count down (counterclockwise) to the target value as described above.
Continue.

The instantaneous values of VOR orientation provided by counters 680-683 are constantly sensed and used to drive corresponding circuitry within the NAV-401L generator. That is, the current value of counter 680 is buffered by buffer 700-7.03 and drives input bins 6 and 12 of switching circuit 655 and input bins 13 and 5 of switching circuit 710. The current value of the counter 681 is
It is buffered by buffers 711-714 and applied to bins 6 and 12 of switching circuit 710 and bins 13 and 5 of switching circuit 715. The current value of counter 682 is buffered by buffers 716-719 and drives bins 6 and 12 of switching circuit 715 and bins 13 and 5 of switching circuit 720.

Finally, the current value of the counter 683 is buffered by buffers 721 and 722, and the current value of the counter 683 is buffered by the switching circuit 7
20 bins 6 and 12 are driven.

Switching circuit 634, 650, 655, 710.7
No. 15,720 consists of a commercially available model CD4016AE device. These devices require banks of pulley resistors, one of which is shown at 7301, each coupled to a 4:15 V supply at the input pin.

A metal oxide (MOS) device is included within the switching circuit and is activated via an input bin, essentially closing a switch. The outputs of the switches are fed through output bins as shown and connected through terminals 43-74 of an output lug, indicated generally at 740.

This plug is mated to the connector on the modified NAV-401L generator, detailed in connection with FIGS. 6, 7, and 8.

Figures 6, 7, and 8 show standard NAV-
Modifications to the 401L generator are shown in detail.

Figure 6 shows modifications to NAV-401L to automate vOR and marker beacon generation.

A new connector has been added to NAV-401L and NAV
- Provides an interface between the 401L and the control PC board. Switch S7, which controls the VOR and marker beacon audible signals, is placed in the off position for automatic operation. Four conductors are added between this switch and the interface connector, bus 1 in Figures 1A and 1B.
It is possible to control the various tone signals via 27. Switch 5701 is a 3-segment switch that feeds the generator's internal signals to the original NAV-401L circuit.
Place the generator in marker beacon, VOR, localizer, glide slope, or VHF communication generation mode. The inputs to the rotating parts of these switch segments are disconnected and connected to the interface. Also, only the portions of the switch segments that control the operation of the marker beaker crystal mode and the VOR crystal mode are connected to the bus connector of the interface. As a result, all VOR and marker beacon signals are automatically controlled and output, but those in any other mode are not output under zero motion control.

FIG. 8 shows the thumb rotary switch on the NAV-401L, which is typically used to manually select the desired heading output using BCD format. Duplicate conductors are drawn out and connected to the automatic interface. In automatic operating mode, all switches are 0 (zero) or "released".
position and closing the CMOS switches 655, 710, 715 . shown in FIGS. 58-5D.
720.

FIG. 7 shows a modification of NAV-401L to allow automatic control of localizer and glide slope. The 90Hz and 150H2 sound signals are disconnected from manually controlled potentiometers R5 (localizer) and R7 (glideslope) and fed to the interface connector. From here it is Figure 1A,
Power is supplied to the synthesizer printed circuit board via lines 123 and 125 in FIG. 1B. These signals are processed as described above and then sent back to the potentiometer in NAV-401L.

Thereby, the potentiometer is used to compensate for the tolerances of the aircraft receiver.

Switch 8701 is modified as described for the VOR/marker beacon case, except that control is now in localizer crystal mode and glide slope crystal mode.

Both the VOR/marker and workerizer/glideslope generators are equipped with jumper plugs as shown in Figures 6 and 7, which disable internal modifications when inserted into the interface connector. be made into This disconnects the generator from the automatic test equipment section and allows all functions of the generator to be used normally in manual mode.

The above description concludes the disclosure of the automatic simulation device for various signals for air navigation.

Although the preferred embodiments of the invention have been described in detail, it is understood that many changes and modifications may be made thereto without departing from the true spirit and scope of the invention. should be recognized.

[Effects of the Invention] As described above, according to the present invention, the glide slope signal, the localizer signal, and the VOR signal are automatically generated at a desired speed and up to a desired final value. It is possible to obtain a simulation device that can accurately generate navigation signals that change at a speed comparable to the speed at which navigation signals are normally received by aircraft actually in operation.

[Brief explanation of the drawing]

FIG. 1A and FIG. 1B are block diagrams showing an embodiment of the radio navigation simulation device of the present invention. FIGS. 2A, 2B, and 2C are diagrams showing detailed structures of the localizer circuits shown in FIGS. 1A and ffllB. 3A and 3B are diagrams showing the detailed structure of the glide slope circuit shown in FIGS. 1A and 1B. 4A and 4B are diagrams showing detailed structures of the synthesis circuits shown in FIGS. 1A and 1B. FIGS. 5A to 5D are diagrams showing detailed structures of the VOR circuits shown in FIGS. 1A and 1B. Factor 6 is a schematic diagram showing modifications to the regular NAV-401L generator that allow automatic control of the VOR and marker beacons. FIG. 7 is a schematic diagram showing modifications to the NAV-401L generator to enable automatic generation of localizer and glide slope signals. FIG. 8 is a schematic diagram showing modifications to NAV-401L to enable automatic generation of VOR heading signals. FIG. 9 is a schematic diagram showing modifications to the circuit shown in FIGS. 5A-5D. In the figure, 10 is a computer, 20 is a localizer circuit, 22 is a glide slope circuit, 24tiVOR/
-rh sound IJ circuit, 42, 44.46 are speed registers, 52, 54.56 are final values 1/jister, 62.64
．． 76 is a logic circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. -f-iy-H J Kan 7/5B 5 Yarito 8

Claims (4)

[Claims] (1) An automatic simulation device for an aircraft VHF omnidirectional guidance path VOR signal, which generates a digital signal indicating a desired final value of the aircraft VHF omnidirectional guidance path signal and a speed at which the aircraft should approach the desired final value. final value register means for receiving and holding the final value signal; speed register means for receiving and holding the speed signal; and current control means for controlling the aircraft VHF omnidirectional guidance path signal. logic means for holding a value and digitally varying its contents up to said final value stored in said final value register means at a rate determined by a signal held in said rate register means; switching means for effecting actuation of a predetermined switch in response to a state of said logic means; and means for generating a predetermined aircraft VHF omnidirectional guidance path signal in response to a state of said switching means; Automatic simulation device for air navigation signals. (2) the logic means comprises a counter means for storing the instantaneous value of the aircraft VHF omnidirectional guidance path signal, the counter means being operable to increase or decrease the count value; further comprising comparison means for comparing the instantaneous value of the aircraft VHF omnidirectional guidance path signal stored in the counter means with the desired final value stored in the final value register means; , if said desired final value and said instantaneous value are different, operating said counter means at a speed determined by said speed signal stored in said register means, thereby changing the count value of said counter means; increasing or decreasing, thereby changing the instantaneous value towards the desired final value;
An automatic simulation device for air navigation signals according to claim 1. (3) The logic means further comprises: a fixed frequency moderate oscillator for generating a constant frequency speed signal f_r; and dividing the constant frequency speed signal f_r by a divisor N determined by the speed signal stored in the register means. dividing means for generating a signal whose frequency is f_r/N by dividing the frequency; and means for coupling a signal whose divided frequency is f_r/N to the counter means and controlling the degree of change in the count value. The automatic simulation device for air navigation signals according to claim 2, further comprising: (4) the automatic simulation device further includes the ability to automatically simulate aircraft marker beacon sound signals, each of the sound signals representing a distance between the aircraft and a reference position; further comprising: control means including means for generating a digital signal representing a desired marker beacon sound signal; marker beacon sound signal register means for storing said marker beacon sound signal; and means for storing said stored marker beacon sound signal. 2. The automatic air navigation signal simulation apparatus according to claim 1, further comprising means coupled to said marker beacon sound signal generating means and for causing said sound signal generating means to generate a desired sound signal.