JPH0332067A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten writing time by a forming a charge injecting electrode through an insulating film, and arranging one part of a floating gate electrode on the charge injecting electrode through the insulating film, and injecting charge into a charge injecting region through the charge injecting electrode. CONSTITUTION:A charge injecting electrode 13 is formed in belt shape on an insulating film 14 for shield plate, and the electrode 13 is covered with an F-N tunnel insulating film 15 and an interelectrode insulating film 16. Though a floating gate electrode 7 is formed selectively on a first gate insulating film, one terminal of the electrode 7 is arranged on the electrode 13 through the film 15, and a second gate insulating film 5 is overlaid on the electrode 7. In the case that the word line side is biased to high potential, electrons are injected form the electrode 13 to the electrode 7 so as to do elimination. On the hand, in the case that the program side is biased to high potential, the electrons are emitted from the electrode 7 to the electrode 13 so as to do writing. For this reason, the writing can be done at low voltage.

Description

Detailed Description of the Invention [Industrial Application Fields] The present invention relates to an electrically erasable FROM (hereinafter referred to as EEFROM) that can electrically erase data stored in a memory transistor and write new data. ) and other nonvolatile semiconductor memory devices.

[Prior Art] Various types of nonvolatile semiconductor memory devices have been researched and developed in which written data does not disappear even when the power is turned off.

In recent years, development of EEFROM has progressed rapidly, and various products have been put into practical use.

EEFROMs have various structures, and recently, one constructed by connecting memory transistors in series has been proposed (R, 5hlrota et al.
digest of 1988 sy＋＊poslu
mon VLSI Technology, pages 33-34).

Figure 6(a) shows a conventional non-volatile semiconductor memory device (EEP).
A plan view showing an example of a ROM), FIG. 8(b) is a plan view showing an example of a ROM), and FIG.
Fig. 6(c) is a cross-sectional view of -Kl in a), Fig. 6(c) is
6(d) is a cross-sectional view taken along line L-L in a), and FIG. 8(d) is
It is a sectional view taken along the MM line of a).

The semiconductor substrate 21 is divided into a plurality of element forming regions by a field insulating film 22 formed on the surface thereof, and the semiconductor substrate 21 in a region surrounded by each field insulating film 822 is divided into a plurality of element formation regions.
Impurity diffusion layers 23a and 23b are selectively formed on the surface by diffusing impurities of a conductivity type opposite to that of the semiconductor substrate 21. Then, on the substrate 21, a first gate insulating film 24 of the memory transistor and a gate insulating film 28 of the selection transistor are formed.

A gate electrode 29 of the selection transistor is formed on the gate insulating film 26 of the selection transistor. On the other hand, a floating gate electrode 27 is selectively formed on the first gate insulating film 24 of the memory transistor, and a control gate electrode 28 is formed on the floating gate electrode 27 via a second gate insulating film 25. is formed. These gate electrode 29, floating gate electrode 27, control gate electrode 28, etc. are covered with an interlayer insulating film 30.

This interlayer film! A metal wiring 32 is formed on the interlayer insulating film 30 in a predetermined wiring pattern. There is.

In FIGS. 6(a) to 6(d), three memory transistors configured as described above are connected in series between two selection transistors configured as described above. There is.

FIG. 7 is an equivalent circuit diagram of the above-mentioned nonvolatile semiconductor memory device. Using FIG. 7, the operation of the EEFROM when the memory transistor is an N-channel will be explained.

Symbols Q511 and Qsl+1 are selection transistors, and symbols Qs + QMI and 0Ml+2 are memory transistors. Each memory transistor Q M+Q
The control gate electrode 28 of Ml*r+Q□ is connected to the word line X,
, X, ya1 and Xl ya2. In addition, the gate electrode 2 of the selection transistor Qs+ and Q SI+1
9 are the first selection line zl and the second selection line z1 . l
It is connected to the. Furthermore, the selection transistor QIl+
and Qs+++! and memory transistor QMIQM1
．． I and QMl,2 are connected in series between the pit line YJ and the source line S.

The potentials of the bit line, selection line, and word line in each data erase, write, and read mode of this nonvolatile semiconductor memory device are shown in Table 1 below.

However, the unit of all numerical values in the table is pol (V).

To erase data, use word lx+.

With X1+1 and Xl,2 on the positive potential side, bit line Y.

and a high voltage (for example, 13
V) is applied. Then, each memory transistor Q
, Q□, 1 and Q□1, the electric field in the film 24 becomes strong, an F-N electron tunneling phenomenon occurs, and the first gate is removed from the semiconductor substrate 21 and the diffusion layers 23a and 23b. 1
Electrons are injected into the floating gate electrode 27 via the gate isolation 1 [24]. As a result, electrons are injected into the floating gate electrodes 27 of all memory transistors,
The threshold voltages of each memory transistor Qx*Qx+□ and 0Ml+2 rise.

Table 1 This state is a state in which data has been erased.

In this erase mode, there is no selectivity of memory transistors, so data stored in all memories is erased at the same time.

On the other hand, the memory transistor QMIQMt+ or QM
When writing data to I or 2, connect the bit line side J and the memory transistor QMIQMt+ or Q
The word line Xl, X11, or XI+2 of the memory transistor connected to the bit line side than x++z is set to a high potential (for example, 20 V), and the word line X+- connected to the memory transistor QMIQMI□ or 0Ml+2 to be written. X++ or X, +2 and the source line S are set to the ground potential. Then, the first gate insulation 1 [
The electric field in the floating gate electrode 24 becomes stronger, and electrons are emitted from the floating gate electrode 27 due to the F-N electron tunneling phenomenon. At this time, the electric field in the first gate insulating film 24 of the memory transistors other than the memory transistor to which a high voltage is applied to the control gate electrode 28 and the drain electrode becomes small, and the F-N
Since no electron tunneling occurs, no electrons are emitted from the floating gate 27. Thereby, selective writing to the memory transistors is achieved. When there are a plurality of memory transistors to which writing is to be performed, writing is sequentially performed to the plurality of memory transistors connected to one selection transistor Qs+ by the above-described method.

Also, when writing this data, the selection transistor Q
The second selection line z1+ connected to B l * 1
1 must be held in OV. This is because even if the control gate electrode potential of the memory transistor is Ov, there is a channel current flowing through the write memory transistor, and this channel current is blocked.

When reading the data stored in the memory transistor, fix the bit line side JI first selection line zl and second selection line z1□ to 5V, and connect the word line X l # X connected to the memory transistor to be read. +*s or X
Connect only 1+1 to ground potential. Then, when the selected memory transistor is in the erased state, the threshold voltage is positive, so no current flows. On the other hand, if the selected memory transistor is in the write state, the threshold voltage is negative, so current flows. This current can be detected by a sense amplifier or the like, and each state can be treated as information corresponding to "I" or "O".

As described above, in conventional nonvolatile semiconductor memory devices, the electrical connection between the charge injection region, that is, the channel region and the drain region of each memory transistor is performed via the selection transistor and the memory transistor on the bit line side. .

Further, each floating gate electrode covers the entire channel region of the respective memory transistor. Furthermore, a field insulating film is used for element isolation. Furthermore, a high voltage for reading is applied to the charge injection region during reading as well.

[Problems to be Solved by the Invention] However, as described above, in the conventional nonvolatile semiconductor memory device, charge is supplied to the charge injection region via the memory transistor on the bit line side. Writing of data on the line is performed sequentially. For this reason, the time required for writing becomes longer, especially for large-capacity
EFROM has a disadvantage in that it takes an extremely long time to write a long program.

Furthermore, during writing, the drain voltage is always supplied via the selection transistor and the memory transistor on the bit line side, so the back gate voltage of these transistors is applied to the voltage supplied to the drain region of the selected memory transistor. In this case, the threshold voltage becomes a voltage lower than the bit line supply voltage. Therefore, the bit line voltage needs to be higher than the voltage originally required for writing.

Furthermore, when data is selectively written to a memory transistor, if all memory transistors other than this selected memory have already been written, if there is no second selection transistor connected to the source line at ground potential, As soon as the threshold of the selection transistor becomes negative, the channel current flows.

Therefore, when a high voltage is supplied by a circuit with a low current supply capacity, such as a charge pump circuit, the channel current causes a potential drop in the power supply voltage, which may cause a write failure. Therefore, in the conventional nonvolatile semiconductor memory device, a second selection transistor for blocking the channel current is essential, making it difficult to improve the degree of integration of the nonvolatile semiconductor memory device.

Furthermore, as shown in Figure 8, where the horizontal axis represents time and the vertical axis represents the threshold voltage, the fluctuation of the threshold voltage of the memory transistor during writing and erasing is shown. Due to the injection of electrons, the threshold of the memory transistor increases over time. Therefore, excessive erasing significantly increases the threshold value of the memory transistor.

For example, at the time of reading, if there is a memory transistor whose threshold voltage has increased to about 5V in the selected column, the bit line current will decrease because the threshold voltage is approximately the same potential as the control voltage. It is limited by this memory transistor.

Therefore, even if data is written to the selected memory, a sufficient read current may not be obtained.

In particular, when the threshold value of the memory transistor is 5V or more, read failures occur.

Furthermore, the first gate insulating film of the memory transistor has a thickness of 10 mm to obtain good write and erase characteristics.
Although it is common to set it to 0λ or less, the electric field strength on the drain side is therefore strong even during reading, and hot electron phenomena are likely to occur. For this reason, the 8th
As shown in the figure, hot electrons are injected into the floating gate electrode during reading, which tends to cause erroneous erasing.

Furthermore, a field insulating film made of a thick oxide film is formed in the element isolation region. Usually, this field insulating film is LOG OS (Local oxldatlon).
of sl.con) technology. For this reason, there is a problem that a bird's beak is formed.
Another drawback is that the effective channel area is reduced due to the narrow channel effect.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a nonvolatile semiconductor memory device that requires a short time for writing, requires a low power supply during writing, can be highly integrated, and can perform stable reading and erasing.

[Means for Solving the Problems] A nonvolatile semiconductor memory device according to the present invention includes a diffusion layer formed in a predetermined region on the surface of a semiconductor substrate, an insulating film formed on the substrate, and a diffusion layer formed on the insulating film. A charge injection electrode formed in a predetermined pattern, an interelectrode insulating film formed on the charge injection electrode, and an interelectrode insulating film selectively formed on the insulating film on the substrate, one end of which is formed on the interelectrode insulating film. a floating gate electrode disposed above, a gate insulating film formed on the floating gate electrode, and a control gate electrode formed extending from the gate insulating film onto the insulating film on the substrate; It is characterized by having the following.

[Operation] In the present invention, a charge injection electrode is formed on a semiconductor substrate via an insulating film, and one end of the floating gate electrode is placed on this charge injection electrode via an interelectrode insulating film. . A control gate electrode is formed in a region extending from the gate insulating film formed on the floating gate electrode to the insulating film formed on the substrate.

In the nonvolatile semiconductor memory device according to the present invention, when erasing data, charge is injected into the floating gate electrode of each memory transistor from this charge injection electrode. If erasing is performed with an excessive erasing time, the threshold value of the memory transistor is determined by the channel threshold value directly below the control gate electrode, and therefore does not become higher than this channel threshold value. Thereby, the threshold value of the memory transistor becomes a predetermined value, and it is possible to avoid reading failures during reading.

Furthermore, during data writing, electrons are directly emitted from each floating gate electrode toward the charge injection electrode.

Therefore, since the influence of the threshold voltages of other memory transistors can be avoided, data can be written at a low voltage. Furthermore, since the current flowing through this charge injection electrode is only a weak tunnel current, there is no need for a second selection transistor to prevent overcurrent from flowing.

Furthermore, it is also possible to write data to multiple memory transistors simultaneously.

Furthermore, at the time of reading, for example, by setting the charge injection electrode to the ground potential, this charge injection electrode can act as a shield plate electrode.
Highly concentrated channel stopper impurities are not required, and narrow channel effects can be reduced.

Furthermore, since the channel region of the memory transistor is only used for reading, there is no need to make the insulating film under the floating gate electrode extremely thin as in the conventional case. Therefore, by setting the insulating film under the floating gate electrode to an appropriate thickness, the electric field strength during reading can be reduced and the occurrence of erroneous erasing due to hot electrons can be suppressed.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1(a) is a plan view showing the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A in FIG. 1(a), and FIG. 1(a) is a sectional view taken along line B-B, FIG. 1(d) is a sectional view taken along line C-C of FIG. 1(a), and FIG. 1(e) is a sectional view taken along line C-C of FIG. 1(a). FIG. 1(f) is a cross-sectional view taken along line DD and FIG. 1(f) is a cross-sectional view taken along line E-B in FIG. 1(a).

Diffusion layers 3a, 3b, and 3c of conductivity type opposite to that of the substrate 1 are selectively formed in predetermined regions on the surface of the semiconductor substrate 1.

A first gate insulating film 41 and a gate insulating film 6 of a selection transistor are respectively formed in predetermined regions on the substrate 1. Insulation B for shield plate! X14 and a third gate insulating fla17 are formed. A charge injection electrode 13 is formed in a band shape on the shield plate insulating film 14, and an F'-N) channel insulating film 15 and an interelectrode insulating film 16 are deposited on the charge injection electrode 13. . A floating gate electrode 7 is selectively formed on the first gate insulating film 4, and one end of the floating gate electrode 7 is injected with charges via the F-N) channel insulating film 15. It is arranged on the electrode 13. This floating gate? A second gate insulating film 5 is deposited on the tt electrode 7.

Floating game)? 1! A plurality of (three in the figure) strip-shaped control gate electrodes 8 are formed on the pole 7 so as to be perpendicular to the charge injection electrode 13 . A gate electrode 9 of a selection transistor is formed parallel to this control gate electrode 8.

The entire surface is covered with an interlayer insulating film 10. A metal wiring electrode 12 is formed on this interlayer insulating film 10 in a predetermined wiring pattern. This metal wiring electrode 12 is connected to the diffusion layer 3a via a bit line contact hole 11 selectively formed in the interlayer insulation [10].

Next, regarding the case of an N-channel memory transistor,
A method of manufacturing a nonvolatile semiconductor memory device according to this embodiment will be described.

First, arsenic (As) is ion-implanted into a predetermined region of the P-type semiconductor substrate 1 to form a source connection diffusion layer 3c. Thereafter, the surface of the substrate 1 is oxidized to form a shield plate rim plX14 with a thickness of 700 Å.

Next, a polycrystalline silicon film doped with phosphorus (P) is deposited on the entire surface to a thickness of 2,000 μm to form a pattern of multiple parallel strips, and the remaining film is removed. An injection electrode 13 is obtained.

Next, the surface of the substrate 1 is heated to, for example, 900'C and
An oxide film with a thickness of 00λ and a thickness of 500λ is formed on the surface of the charge injection electrode 13, respectively. This oxide film becomes the first gate insulating film 4 and the F-Nl-channel insulating film 15.

Next, a polycrystalline silicon film was deposited on the entire surface to a thickness of 2000λ, and after introducing phosphorus into this polycrystalline silicon film,
The floating gate electrode 7 is formed by patterning into a predetermined shape.

Next, after removing unnecessary residual films on the substrate 1 and the charge injection electrode 13, the substrate is heated to, for example, 1150°C to coat the surface of the substrate.
An oxide film of 350 mm and 350 mm is formed on the surfaces of the charge injection electrode 13 and the floating gate electrode 7, respectively.

The oxide film on this substrate 1 becomes the third gate insulating film 17 and the selection transistor gate insulating film 6, the oxide film on the floating gate electrode 7 becomes the second gate insulating film 5, and the oxide film on the charge injection electrode 13. becomes an interelectrode insulating film 16.

Next, a polycrystalline silicon film was deposited on the entire surface to a thickness of 4000λ, and after introducing phosphorus into this polycrystalline silicon film,
A control gate electrode 8 and a selection transistor gate electrode 9 are formed by molding into a predetermined pattern.

Next, arsenic is selectively ion-implanted into the surface of the substrate 1 to form diffusion layers 3a and 3b which will become the source/drain regions of the memory transistor and the selection transistor.

Next, interlayer insulation [1
After forming the interlayer insulating film 10, a contact hole 11 reaching the diffusion layer 3a from the surface of the interlayer insulating film 10 is formed.

Next, this contact hole 11 is filled with
Metal wiring 12 is formed in a predetermined pattern on the interlayer cotton mgio. As a result, the nonvolatile semiconductor memory device according to this embodiment is completed.

FIG. 2 is an equivalent circuit diagram of the nonvolatile semiconductor memory device according to this embodiment. However, this nonvolatile semiconductor memory device is constructed in such a way that identical transistor groups are formed with the vertical plane passing through the two contact holes 11 shown in FIG. FIG. 2 shows only the second group. The control gate electrode 8 in FIGS. 1(a) to (f) is connected to the word line XII in FIG.
JIXl, J+1 + XIIJ. 21 X l+1.
JI31 X I+I+J. 4゜X l+I+J+ls
It is indicated by. Similarly, the metal wiring 12 is connected to the bit line Ykly
k+t, the charge injection electrode 13 connects the program lines W, , Wk
, , the selection transistor gate electrode 9 is connected to the column selection line Z.
Denoted by llZI+1. In addition, the selection transistor has the symbol Q Sll+l+Q 8 +I+l+ Qsk
+++n Qsk+++++t, and the memory transistors are denoted Q Mk, 1Q Mk+J. .

Q Mll+J and 2+ QMk, r. 31 QMk, +
4+ QMk+J+5+Q Mu◆I, JI QMh◆
I+J+II QMIl+IIJ◆21 QMb・h”
◆3゜Q□1. It is shown as □ or 4+ QMll+I+J+5. The memory transistor includes 11 gate electrode transistors and a 2-layer gate transistor connected in parallel.

The potentials of the word line, program line, bit line, and column selection line in each operation mode of the nonvolatile semiconductor memory device of this example are summarized in Table 2 below.

However, in the table, the numerical unit is pol) (V).

FIGS. 3(a) to 3(h) are circuit diagrams showing potentials of word lines, program lines, bit lines, and column selection lines and operations of memory transistors, focusing on each memory transistor.

When the potential difference between the word line (control gate electrode 8) and the program line (charge injection N pole 13) is 20V as shown in FIGS. 3(a) and (b), that is, in the bias state, F- N) An electric field sufficient to inject charge into the tunnel insulating film 15 is generated, and an FN tunnel phenomenon occurs.

At this time, if the word line side is biased to a high potential as shown in FIG. 3(a), electrons are injected from the charge injection electrode 13 toward the floating gate electrode 7, and erasing is performed. In this case, by applying a voltage as shown in Table 2, it is also possible to erase only the data of a plurality of memory transistors connected to the same word line. However, when all data is to be erased, it is preferable to use the -batch mode, which applies less voltage stress to unselected memory transistors. On the other hand, when the program line side is biased to a high potential as shown in FIG. 3(b), electrons are emitted from the floating gate electrode 7 to the charge injection electrode 13, and writing is performed.

As shown in FIGS. 3(C) to (f), by setting either the word line or the program line to an intermediate potential, for example 10V, the electric field in the F-N channel insulation 1/X15 is relaxed. It is possible to prohibit writing to the same word line and selection line, selectively write to the same program line, etc.

As shown in FIG. 3(g), when there is no potential difference between the word line and the program line, the threshold value of the memory transistor does not change. Then, as shown in FIG. 3(h), information of the memory transistor to which a voltage of 6V is applied to the word line can be read. At this time, M! of the electric field injection region! By appropriately selecting X thickness and film quality,
The electric field generated in the F-Nl-channel insulating film 15 can be made smaller than the electric field strength at which electron tunneling occurs. This makes it possible to avoid fluctuations in the threshold value of the memory transistor during reading.

As described above, in the nonvolatile semiconductor memory device according to this embodiment, writing and erasing to the memory transistor is controlled only by the potential difference between the word line and the program line. At this time, the bit line and column selection line do not affect writing or erasing. However, the program line (charge injection electrode 13)
If a voltage is applied to the bit lines, a parasitic channel will be formed, so it is preferable to keep all the bit lines open.

FIG. 4 is a graph showing the threshold voltage fluctuation characteristics of the memory transistor constituting the nonvolatile semiconductor device of this embodiment, with time plotted on the horizontal axis and threshold voltage plotted on the vertical axis.

This is clear from Figure 4.

Thus, in this embodiment, even if excessive erasing is performed, the threshold value of the memory transistor does not exceed the value determined by the threshold value of the channel directly below the control gate electrode. Therefore, read failures caused by excessive erasing operations can be prevented. However, in this case, care must be taken in setting the number of rewrites because a weak tunneling phenomenon of electrons occurs due to long-term stress and the threshold value fluctuates.

In this embodiment, when charge is injected into the floating gate electrode 7, the floating gate electrode 7 is connected to the charge injection electrode 13 in plan view.
This charge injection region is provided individually for each memory transistor.

Charge is supplied to this charge injection region by a charge injection electrode 13 having low electrical resistance. Therefore, writing to the memory transistors arranged in the column direction can be performed in batches by applying a voltage to the word line according to data. Therefore, the time required to write a program can be reduced compared to the conventional method.

Further, the channel of the memory transistor is constituted by a floating gate electrode 7 and a control electrode 8, respectively.

Therefore, in the equivalent circuit, a transistor whose channel potential is controlled by the control gate 7 and a transistor whose channel potential is controlled by the floating gate electrode 7 are connected in parallel.

Therefore, during writing, the channel threshold value under the floating gate electrode determines the threshold value of the memory transistor, and during erasing, the lower channel region of the two channel regions (usually the one directly below the control gate electrode 8) determines the threshold value of the memory transistor. channel area)
determines the threshold of the memory transistor. Therefore,
Even if excessive erasing is performed during erasing, the value will not exceed this threshold value, so read failures can be avoided.

Furthermore, when reading, fix the program line to Ov,
Charge injection electrode 13 is used as a shield plate.

Thereby, the channels of each memory transistor are electrically isolated by the charge injection electrode 13. Therefore, if the potential of the charge injection electrode 13 is below the threshold of the parasitic channel, adjacent bits can be completely isolated.

FIG. 5(a) is a plan view showing the second embodiment of the present invention, FIG. 5(b) is a sectional view taken along the line F--F in FIG. 5(a), and FIG. 5(a) is a sectional view taken along line GG, FIG. 5(d) is a sectional view taken along line HH in FIG. 5(a), and FIG. 5(e) is a sectional view taken along line HH in FIG. 5(a). FIG. 5(f) is a cross-sectional view taken along line I--I, and FIG. 5(f) is a cross-sectional view taken along line J--J in FIG. 5(a).

This embodiment differs from the first embodiment in that the source wiring is formed of a semiconductor wiring layer such as polycrystalline silicon and placed on the substrate, and the other structure is basically the same as that of the first embodiment. Since it is similar to the example, the same reference numerals are given to the same parts in FIGS. 5(a) to 5(f) as in FIGS. 1(a) to 1(f), and detailed explanation thereof will be omitted.

In the first embodiment, the connection between each diffusion layer 3b is expanded.
Although this was done using the layer 3c, in this embodiment, the semiconductor wiring layer 18 formed on the substrate 1 connects each diffusion layer 3b. Further, a semiconductor wiring layer 18 formed by filling a contact hole 19 is provided between the metal wiring 12a formed on the interlayer insulating film 10 and the diffusion layer 3a on the surface of the substrate 1.

In this embodiment, as described above, the source wiring is formed by the low-resistance semiconductor wiring layer 18 made of polycrystalline silicon or the like, so that the source parasitic resistance can be reduced. Further, by forming the semiconductor wiring layer 18 embedded in the contact hole 19 in a self-aligned manner, there is an advantage that the distance between the bit line contact 11 and the selection transistor gate electrode 9 can be reduced.

In this embodiment as well, the same effects as in the first embodiment can be obtained.

[Effects of the Invention] As explained above, in the nonvolatile semiconductor memory device according to the present invention, a charge injection electrode is formed on a semiconductor substrate with an insulating film interposed therebetween, and a part of the floating gate electrode is formed through an insulating film. Since charge is injected into the charge injection region via the charge injection electrode, charge is simultaneously injected into the memory transistor connected to this charge injection electrode. can do. As a result, it is possible to simultaneously write to a plurality of memory transistors in one column at most, and the time required for program writing can be significantly shortened compared to the conventional method. This effect is particularly effective when using a writing device with a built-in data latch function, especially a writing device that has the function of writing after a large amount of data has been loaded into the buffer memory. It is possible to quickly write programs to non-volatile semiconductor devices.

Furthermore, charge is supplied to the charge injection region during writing directly from the charge injection electrode to each memory transistor. Therefore, since no drop in the write voltage occurs, writing is performed at a low voltage and the reliability of writing is high.

Furthermore, there is no current outflow from the charge injection electrode other than a weak tunnel current. Therefore, there is no need for a selection transistor for suppressing current outflow from the charge injection electrode. Therefore, the degree of integration of the semiconductor device can be improved compared to the conventional method.

Furthermore, the threshold of the erase memory transistor is determined by the threshold of the channel under the control gate electrode. Therefore, even if excessive erasing is performed, the on-current of the non-selected transistors during reading can be ensured. Furthermore, since the threshold value during erasing is constant, stable read operations are possible.

Furthermore, the channel region of the memory transistor is used only for reading. Therefore, it is sufficient for the first and third gate insulating films to have a thickness of about 200 Å or more.

As a result, fewer hot electrons are generated than in the past, and the occurrence of erroneous erasure during reading is suppressed.

Furthermore, the channels of memory transistors in adjacent columns are isolated by setting the charge injection electrodes to ground potential. Therefore, the effective memory transistor channel is less narrowed from the designed value, and a high concentration channel stopper impurity is not required, so that the narrow channel effect is suppressed. Therefore, a large channel current can be obtained.

[Brief explanation of drawings]

FIG. 1(a) is a plan view showing the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A in FIG. 1(a), and FIG. Cross-sectional view taken by B-BAI in Figure 1 (a),
FIG. 1(d) is a sectional view taken along line C-G in FIG. 1(a),
FIG. 1(e) is a sectional view taken along line D-D in FIG. 1(a),
FIG. 1(f) is a cross-sectional view taken along line E-E in FIG. 1(a),
Figure 2 is the equivalent circuit diagram, and Figures 3 (a) to (h)
) focuses on individual memory transistors, word lines,
FIG. 4 is a circuit diagram showing the potentials of the program line, bit line, and column selection line and the operation of the memory transistor. The horizontal axis represents time, and the vertical axis represents the threshold voltage. A graph diagram showing the characteristics, FIG. 5(a) is a plan view showing the second embodiment of the present invention, and FIG. 5(b) is a diagram showing FIG. 5(a).
A cross-sectional view taken along line F-F of FIG. 5(C) is FIG. 5(a)
A cross-sectional view taken along the line G-G of FIG. 6(d) is the same as FIG. 5(a).
5(e) is a cross-sectional view taken along the H-E line of FIG. 5(a).
5(f) is a cross-sectional view taken along line I-I of FIG. 5(a).
FIG. 6(a) is a plan view showing an example of a conventional nonvolatile semiconductor memory device, and FIG. 6(b) is a cross-sectional view taken along line J-J in FIG. 6(a). Figure 6(C) is a cross-sectional view taken along line LL in Figure 6(a), Figure 6(d) is a cross-sectional view taken along line M-M in Figure 6(a), and Figure 7 is a cross-sectional view taken along line LL in Figure 6(a). Similarly, the equivalent circuit diagram of the non-volatile semiconductor memory device, FIG. 8, shows the threshold of the memory transistor during writing and erasing of the conventional non-volatile semiconductor memory device, with time on the horizontal axis and threshold voltage on the vertical axis. FIG. 3 is a graph diagram showing a value variation characteristic. 1.21; Semiconductor substrate, 3am 3b+ 3c+ 23
a, 23b; diffusion layer; 4.24; first gate insulation film;
5.25; second gate insulating film, 6.26; gate insulating film of selection transistor, 7, 27; floating gate electrode,
8.28; Control gate electrode, 9.29; Gate electrode of selection transistor, 10.30; Interlayer insulating film, 11.1
9.31; Contact hole, 12+ 12a+ 32;
Metal wiring, 13; Charge injection electrode, 14; Shield plate monthly supply edge film, 15; F-N) channel insulating film, 16; Interelectrode insulating film, 17; Third gate insulating film, 18; Semiconductor wiring layer

Claims (1)

[Claims] (1) A diffusion layer formed in a predetermined region on the surface of a semiconductor substrate, an insulating film formed on this substrate, a charge injection electrode formed in a predetermined pattern on this insulating film, and a charge injection electrode formed on this charge injection electrode. an interelectrode insulating film formed on the substrate; a floating gate electrode selectively formed on the insulating film on the substrate and having one end disposed on the interelectrode insulating film; and a floating gate electrode formed on the floating gate electrode. 1. A nonvolatile semiconductor memory device comprising: a gate insulating film, and a control gate electrode formed extending from the gate insulating film onto the insulating film on the substrate.