JPH0332103B2 - - Google Patents

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a synchronous control method for memory access in a system equipped with a vector processor, and in particular to a method for controlling memory access with little overhead using POST and WAIT instructions. Regarding synchronous control method.

[Conventional technology]

The scalar unit and vector unit in the vector processor are access sources that perform memory accesses independently, but if these memory accesses are not performed in accordance with the order of instruction execution, synchronization with data updates will be lost. , the problem arises that the program is not executed correctly.
Therefore, synchronous control of memory access is required.

In general, instructions used to synchronize memory accesses from multiple access sources include:
There are POST and WAIT instructions.

First, the POST instruction and WAIT instruction will be explained. During the program as shown in Figure 2.
If POST and WAIT instructions are placed, POST
Memory access by the instruction following the WAIT instruction is not allowed until the memory access performed by the instruction preceding the instruction is completed. In other words, the memory access that precedes the POST instruction,
Guarantees that ordering is performed between the WAIT instruction and memory accesses by subsequent instructions.

In the example shown in Figure 2, there are a POST instruction and a WAIT instruction between the store instruction ST A and the load instruction LOAD A.
Since the instruction is inserted, the order of data between the previous store instruction and the subsequent load instruction is guaranteed. Thus, for example, if ST A is a vector store and LOAD A is a scalar read, the scalar unit is guaranteed to read the data updated by the vector unit. On the other hand, since no POST instruction is inserted between ST B and LOAD A, when data stored in ST B is read in LOAD A, it is difficult to determine whether the data is the data before the update or the data after the update. We cannot guarantee that this will be the case.

[Problem that the invention seeks to solve]

Conventional memory access synchronization control methods using POST and WAIT instructions have the problem of increased overhead because the memory access status is monitored for each access source.

[Means for solving problems]

The present invention uses the POST flag and
It introduces a new POST status signal. Accordingly, the configuration of the present invention includes a vector processor, and synchronizes control of the access order among a plurality of access sources with respect to memory access from the vector processor using the POST instruction and
In a system using the WAIT instruction, each access source sends the POST signal to another access source by the POST instruction if the memory access before the POST instruction has not yet been completed or there is a possibility that the memory access has not been completed. Also, when a WAIT instruction is sent, a memory access to be executed after the WAIT instruction is sent from another access source.
The feature is that it is prohibited until the POST status signal turns OFF.

[Action of the invention]

FIG. 1 is a conceptual diagram of a simplified system for explaining the operation of the present invention. In the figure, 1 is
MSU (main storage unit), 2 is MCU (memory control unit),
3 is a scalar unit SU, 4 is a vector unit VU, 5 and 6 are access transmission units, 7 and 8 are access synchronization control units, 9 is a POST flag, 1
0 is WAIT flag, 11 is access control section, 1
2 is the POST status register.

SU3 and VU4 can each independently issue memory access requests to MSU1.
In other words, it becomes an access source. Access transmitting units 5 and 6 transmit access requests to MCU 2 when a store command or a load command is issued, respectively. The access control unit 11 of the MCU 2 controls access to the MSU 1 in response to this.

When a POST command or a WAIT command is issued in the command control unit (not shown), SU3 and VU
4, the access synchronization control units 7 and 8 operate, and the POST flag 9 and WAIT flag 10 are
Memory access ordering is controlled using the POST status signal and the POST status signal.

Each access source (SU3 and VU4) is an MCU
POST status signals are exchanged with other access sources via the POST status register 12 in the system, and when memory is accessed after a WAIT instruction, all access sources in the system are checked if they have not yet been accessed in a memory access before the POST instruction. It is possible to quickly detect whether or not something is completed. Next, for convenience, we will explain the specific actions.
The explanation will focus on VU4.

Upon detecting a POST instruction, each access source flags its last memory access preceding the POST instruction with a POST flag. and
While the POST flag is in the local access source,
Sends the POST status signal “ON” to other access sources via the MCU. On the other hand, if there is no memory access, a POST state signal "OFF" is sent to the MCU. The POST flag is turned "OFF" after making an access request to the MCU. but
After a memory access request with the POST flag set to "ON" is sent to the MCU, the MCU sends a POST status signal "ON" to other access sources. The POST status signal disappears when a memory access is activated in the MCU. Also, in the MCU,
As soon as there is no longer a memory access request corresponding to that access source, it disappears.

Next, when the WAIT instruction is executed, each access source remembers the WAIT instruction by setting the WAIT flag to “ON,” and when it detects a subsequent memory access request, the other access source sends a POST status signal. Check whether “ON” is output. If the POST state signal is "ON", the memory access is not permitted until the POST state signal becomes "OFF". Further, the WAIT flag is turned "OFF" when memory access is permitted.

〔Example〕

Next, details of the present invention will be explained based on examples.

FIG. 3 is a schematic diagram of a system according to an embodiment of the present invention. In the figure, 1 is MSU (main storage unit), 2
is MCU (storage control unit), 3 is SU (scalar unit), 4 is VU (vector unit), 6 is access transmission unit, 8 is access synchronization control unit, 9 is POST
flag, 10 is WAIT flag, 12 is POST status register, 13 is buffer memory, 14 is BI (buffer invalidation) stack, 14a is
BI POST flag, 15 is store buffer, 15
a is STB POST flag, 16 is OR gate, 1
7 is SU port, 18 is BI address register
BIA, 19 is VU port, 50 is MSU port,
Reference numeral 51 indicates an OR gate, and 52 indicates an inhibition gate.

The basic configuration of this embodiment almost corresponds to the conceptual configuration of the present invention shown in FIG. has become a feature.

In such a system, when the data of the store instruction before the POST instruction remains in the store buffer 15, it means that the data of MSU 1 has not been updated yet, so it cannot be accessed by other sources. It is necessary to prohibit access, and similarly, when the data of MSU1 is updated by the data of the store instruction before the POST instruction, there is a buffer invalidation function that invalidates the corresponding data before the update if it exists in the buffer memory 13. However, access to the buffer memory 13 after the WAIT instruction must be prohibited until the invalidation process is completed.

In this example, access prohibition control when updating these memory data is performed by POST and WAIT.
It is configured to function in conjunction with synchronization control by

First, when a store instruction is executed in the SU3, the store data is immediately stored in the high-speed store buffer 15, and then written to the MSU1 under the control of the MCU2. This allows the SU3 to immediately move on to executing other instructions, allowing the SU3 to operate at high speed.

The store buffer 15 may be composed of a plurality of stores as illustrated in FIG. 4 (described later), in which case a POST flag is provided for each store buffer. Store data read from the store buffer 15 when it is accessible is transferred to the MSU 1 via the SU port 17 and the MSU port 50 of the MCU 2.
written. At this time, the STB POST flag 15a read out from the store buffer 15 at the same time.
is “ON”, the output of the OR gate 51 becomes “1” due to the POST status signal from the time the store data is input to the SU port 17 until it is read, and the prohibition gate 52 transmits the access transmission of the VU4. Access requests originating from section 6 are prohibited.

Next, when the inhibit gate 52 of the MCU2 is in the non-inhibited state, the access transmitter 6 of the VU4
Assume that a store access has been sent to .
Also, at this time, POST flag 9 of VU4 is “ON”
It is assumed that this is set to . As a result, MCU
2's VU port 19, the store address is sent to BI as a buffer invalidation address.
It is stored in the address register BIA18, and from there it is input to the BI stack 14 of SU3. At the same time, the POST status signal based on the POST flag 9 of VU4 is transmitted via the POST status register 12 of MCU2 to the BI POST flag 14a of SU3.
has been entered.

The buffer invalidation addresses stored in the BI stack 14 in this way are then sequentially read out, and when data at the corresponding address exists in the buffer memory 13, a process is performed to invalidate it (invalidation). be exposed. At this time
The OR gate 16 monitors each BI POST flag 14a of all unprocessed buffer invalidation addresses stored in the BI stack 14,
If even one BI POST flag remains "ON", it outputs "1" and prohibits buffer access after WAIT.

FIG. 4 shows a specific example of the circuit configuration of the store buffer 15 in FIG. 3, and is an example having two store buffers. 20 in the diagram
is store address register STA-0, 21 is store address validity flag STA VAL-
0 and 22 are store buffer POST flags STB
POST-0, 23 are store address registers
STA-1, 24 are store address validity flags STA VAL-1, 25 are store buffers
POST flag STB POST-1, 26 to 31
is an AND gate, 32 and 33 are selectors, and 34 is an AND gate.
OR gate, 35 is memory address register
MSAR, 36 is access request latch REQ, 37
is a POST state latch. Note that the store data section is omitted.

The selector 32 selects one of STA-0 to STA-1 and sets the store address therein in the memory address register MSR35.
Selector 33 synchronizes with selector 32 and performs STA
One of VAL-0 to STA VAL-1 is selected and the validity flag V set there is transferred to the access request latch 36. If this validity flag is “ON”, the REQ signal to the MCU is “ON”.

The two inputs of OR gate 34 are each STB
Connected to the outputs of POST-0 and STB POST-1, and also connected to the output of POST-0 and STB POST-1.
When storing data with the POST flag set to "ON", the POST state latch 37 is set to "ON", and the POST state is notified to all other access sources via the MCU.

In addition, AND gates 26 and 27 and AND gate 2
9 and 30 are selectively driven by the STA-0 set signal and the STA-1 set signal, respectively, to set the store address and STA VAL signals to either STA-0 and STA VAL-0 or STA-1. and set to STA VAL-1.
AND gates 28 and 31 are provided for timing, and when a POST command is detected,
Set STB POST-0 and STB POST-1 to “ON” at the same time.

Next, Figure 5 shows the BI stack 1 in Figure 3.
A specific circuit configuration example of No. 4 is shown below. In the figure, 3
8 is a BI POST flag stack, 39 is a BI stack, and 40 is a BI VAL flag stack, each of which is composed of a shift register and operates synchronously. Also, 41 and 42 are transfer registers, 4
3 and 44 are NOR gates.

The NOR gate 43 outputs "OFF" if there is even one "ON" in the BI POST flag stack 38, and the NOR gate 44 outputs an access prohibition signal to the buffer memory when the WAIT flag is "OFF". . BI stack 39
The buffer invalidation address BIA stored in the buffer invalidation address BIA is transferred to the buffer memory by the output BI REQ signal when the corresponding validation flag BI VAL in the BI VAL flag stack 40 is “ON”. decision processing is executed.

〔Effect of the invention〕

As described above, according to the present invention, POST,
Synchronous control of memory access using the WAIT command can be sped up, and overhead can be eliminated.

[Brief explanation of the drawing]

Figure 1 is a conceptual diagram of the method of the present invention, Figure 2 is
An explanatory diagram of synchronization control using POST and WAIT, Fig. 3 is a block diagram of one embodiment of the method of the present invention, Fig. 4 is a circuit diagram of one specific example of a store buffer, and Fig. 5 is a circuit diagram of one specific example of a BI stack. It is a diagram. In the figure, 1 is the main storage unit MSU, 2 is the storage control unit MCU, 3 is the scalar unit SU, 4 is the vector unit VU, 5 and 6 are access transmission units, and 7 and 8
is the access synchronization control unit, 9 is the POST flag, 10
is the WAIT flag, 11 is the access control section, 12
indicates the POST status register.

Claims (1)

[Scope of Claims] 1. A vector processor is provided, and regarding memory access from the vector processor, synchronization control of access order among a plurality of access sources is provided.
In a system that uses POST and WAIT instructions, each access source uses the POST instruction to transmit the POST signal to other sources if the memory access prior to the POST instruction has not yet been completed or may not have been completed. to the access source, and
A memory access synchronization control method characterized in that a WAIT command inhibits memory access to be executed after the WAIT command until a POST status signal sent from another access source turns OFF. 2. The memory according to item 1, wherein the system is equipped with a buffer memory, and when there is a store instruction preceding the POST instruction, memory access is permitted after buffer invalidation accompanying the store is completed. Access synchronization control method. 3. The memory access synchronous control method according to item 1 or 2, characterized in that the system comprises a system store buffer, and the store buffer has an attached information bit indicating POST for each store buffer.