JPH0332103Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field This invention relates to a phase shift circuit, and is particularly applicable to FM
The present invention relates to a phase shift circuit suitable for use in a phase shifter of a quadrature detection circuit of a stereo receiver or a phase compensation circuit of a stereo multiplex circuit.

(b) Prior Art A phase shift circuit is known which can generate an output signal having the same level as an input signal and whose phase difference with the input signal corresponds to the frequency shift of the input signal. There is. Such a phase shift circuit is described, for example, in the book "FM Stereo Receiver" published by Nikkan Kogyo Shimbun on July 10, 1975, page 150 and
It is disclosed on page 151, and as shown in Fig. 1, a transistor 2 with input terminal 1 connected to its base.
and connect the collector of transistor 2 to the power supply (+
Vcc), a second resistor 4 that connects the emitter to ground, and a third resistor 5 and capacitor 6 that are connected in series between the collector and the emitter.
It is composed of: In FIG. 1, the values of the first and second resistors 3 and 4 are set equal to R ₁ ,
If the input signal is 1 υ, signals υ and 1 υ are generated at the collector and emitter of the first transistor 2, which have the same level and a phase difference of 180 degrees. At this time, if the value of the third resistor 5 is R ₂ , the capacitance of the capacitor 6 is C, the current flowing through the third resistor 5 and the capacitor 6 is I, and the output signal obtained at the output terminal 7 is υ ₀ , then The formula holds true.

(R ₂ +1/jωC)I=2υ…(1) 1/jωCI=υ ₀ −(−υ)…(2) (where ω is the angular frequency of the input signal) Therefore, Equation (1) and If I is eliminated from equation (2), υ ₀ /−υ=−1−jωCR ₂ /1+jωCR ₂ ...(3), and from equation (3), the phase angle between the input signal and the output signal is: tan ^-1 2ωCR ₂ /1−(ωCR ₂ ) ² …(4). Here, if the angular frequency at which 1/ωC=R ₂ is ω ₀ , then equation (4) is as follows: = tan ^-1 2(ω/ω ₀ )/1−(ω/ω ₀ ) ² …( 5), and as is clear from equation (3), the level ratio between the input signal and the output signal is 1. FIG. 2 shows the change in phase angle when the angular frequency ω of the input signal is changed in equation (5). Figure 2 shows ω
When = ω ₀ , that is, when ω/ω ₀ = 1, it becomes = 90 degrees, and when the angular frequency ω shifts from ω ₀ ,
This shows that the phase angle changes accordingly.

Therefore, by using the phase shift circuit shown in FIG. 1, it is possible to obtain an output signal at the output terminal 7 that has the same level as the input signal and has a phase difference with respect to the input signal corresponding to the frequency shift of the input signal. . However, in the phase shift circuit shown in FIG. 1, even if the saturation resistance of the first transistor 2 is set to 0Ω, the signal obtained at the collector of the first transistor 2 only has an amplitude of 1/2 Vcc at maximum, as shown by the solid line in FIG. The phase shift circuit shown in FIG. 1 had the disadvantage of a narrow output dynamic range. Note that the dashed dotted line in FIG. 3 is a signal obtained at the collector of the first transistor. Further, since the phase shift circuit shown in FIG. 1 has a gain of 1, a separate circuit must be connected in order to perform amplification or attenuation.

(c) Purpose of the invention The present invention has been made in view of the above-mentioned points, and aims to provide a phase shift circuit having a wide output dynamic range and a gain.

(d) Structure of the invention The phase shift circuit according to the invention consists of a differentially connected first
and a second transistor, a resistor and a capacitor connected in series between the collectors of the first and second transistors, and first and second transistors connected between the collectors of the first and second transistors and a power supply, respectively. It includes a load resistor, an input terminal connected to the base of the first transistor, and an output terminal connected to a midpoint between the resistor and the capacitor.

(E) Embodiment FIG. 4 is a circuit diagram showing an embodiment of the present invention.
8 is a first transistor whose base is connected to the first input terminal 9 and whose emitter is connected to the constant current source 10; 11 is a second transistor whose base is connected to the second input terminal 12 and whose emitter is connected to the constant current source 10; , 13
is the collector of the first transistor 8 and the power supply (+
A first load resistor 14 connected between the collector of the second transistor 11 and the power supply (+
A second load resistor 15 is connected between the collector of the first transistor 8 and the output terminal 1
6, and 17 is the resistor connected between the second
This is a capacitor connected between the collector of the transistor 11 and the output terminal 16. 1st and 2nd
Transistors 8 and 11 are differentially connected,
A differential amplifier circuit is configured to differentially amplify input signals applied to the first and second input terminals 9 and 12 in opposite phases to each other. Now, the input signal applied to the first input terminal 9 is -υ, the input signal applied to the second input terminal 12 is υ, and the first and second transistors 8
If the gain of the differential amplifier circuit consisting of the transistors 1 and 11 is A, the signal obtained at the collector of the first transistor 8 is Aυ, and the signal obtained at the collector of the second transistor 11 is -Aυ. Then, the value of the resistor 15 is R, the value of the capacitor 17 is C, and the resistor 15 is
And if the current flowing through the capacitor 17 is I, then (R+1/jωC)I=2Aυ...(6), and if the output signal obtained at the output terminal 16 is υ ₀ , then 1/jωCI=υ ₀ - ( −Aυ) …(7). From equations (6) and (7), the input signal (−
The ratio between υ) and the output signal (υ ₀ ) is υ ₀ /−υ=−A1−jωCR/1+jωCR …(8), and the phase angle between the input signal and the output signal is = tan ^{− 1} 2ωCR/1−(ωCR) ² …(9). Here, if ω ₀ is the angular frequency at which 1/ωC=R, then Equation (9) is as follows: = tan ^-1 2 (ω/ω ₀ ) 1 - (ω/ω ₀ ) ² ...(10) Therefore, the phase angle and the angular frequency ω of the input signal are correlated. When formula (10) is graphed, it becomes approximately as shown in Fig. 2.

Further, the maximum amplitude of the signal Aυ obtained at the collector of the first transistor 8 is as shown by the solid line in FIG. It will be like this. That is, the maximum amplitude υ _MAX of Aυ and -Aυ of the signal is as follows: υ _MAX = Vcc - Va (11) (where Va is the operating voltage of the current source (10)), and the Va is approximately 0.5V. From, approximately 1st
It is possible to obtain twice the dynamic range of the phase shift circuit shown in the figure.

FIG. 6 shows another embodiment of the present invention,
It is characterized in that a first emitter resistor 18 is connected between the emitter of the first transistor 8 and the current source 10, and a second emitter resistor 19 is connected between the emitter of the second transistor 11 and the current source 10. 6th
As shown in the figure, the first and second emitters are connected to resistors 18
and 19, the input dynamic range can be expanded and the distortion rate can be improved.

FIG. 7 shows still another embodiment of the present invention, in which a resistor 20 is connected between the emitters of the first and second transistors 8 and 11, and a resistor 20 is connected between the emitter of the first transistor 8 and the ground. Current source 2
1 is characterized in that a second current source 22 is connected between the emitter of the second transistor 11 and the ground. However, if the configuration is as shown in Figure 7,
As in the case of FIG. 6, it is possible to expand the input dynamics range. Furthermore, since there is no voltage drop across the resistor 20, it is possible to expand the output dynamic range.

FIG. 8 shows yet another embodiment of the present invention, which is characterized in that a resistor 23 is connected between the common connection point of the first and second load resistors 13 and 14 and the power supply (+Vcc). do. By connecting the resistor 23, the first and second load resistors 13 and 14
The DC level at the common connection point of the output terminal 16 decreases, and the DC level of the output terminal 16 decreases accordingly, making it easier to match the output terminal 16 with a subsequent circuit (not shown) connected to the output terminal 16. In that case,
Since the common connection point of the first and second load resistors 13 and 14 serves as a grounding point for the AC signal, the AC signal is not affected by the insertion of the resistor 23.

In addition, in FIG. 8, a resistor 23 is used to lower the DC level of the output terminal 16, but
In place of the resistor 23, a voltage source such as a diode connected in series may be used.

(f) Effects of the invention As described above, according to the invention, a phase shift circuit with a wide output dynamic range can be provided. Further, according to the present invention, there is an advantage that a phase shift circuit having an arbitrary gain can be created with a simple circuit configuration. Further, according to the present invention, since the output dynamics range is wide, the degree of freedom when directly connecting to subsequent stage circuits increases, and there is an advantage that a circuit suitable for IC implementation can be provided.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional phase shift circuit;
The figure is a characteristic diagram showing the frequency vs. phase angle characteristics.
1 is a characteristic diagram showing the output signal waveform of FIG. 1, FIG. 4 is a circuit diagram showing an embodiment of the present invention, FIG. 5 is a characteristic diagram showing the output signal waveform, and FIGS. 6, 7, and FIG. 8 is a circuit diagram showing another embodiment of the present invention. Explanation of main figure numbers, 8...first transistor, 11
...Second transistor, 13, 14...Load resistance, 1
5...Resistor, 17...Capacitor.

Claims (1)

[Claims for Utility Model Registration] First and second transistors connected differentially and collectors of the first and second transistors are connected in series, and signals obtained at the collectors and having mutually opposite phases are applied to both ends. a resistor and a capacitor; first and second load resistors respectively connected between the collectors of the first and second transistors and a power supply; and an input terminal connected to the base of the first transistor and the resistor. and an output terminal connected to the midpoint of the connection with the capacitor, and is characterized in that the phase of the output signal obtained at the output terminal is changed depending on the input signal applied to the input terminal. Phase shift circuit.