JPH0332122Y2 - - Google Patents

Description

[Detailed Description of the Invention] (A) Field of Industrial Application The present invention relates to data transfer between control devices, and relates to a device capable of detecting data errors caused by disturbances such as noise or static electricity.

(B) Prior Art As a method for detecting data errors in such data transfer, there is an echo back method disclosed in Japanese Patent Laid-Open No. 108844/1983. This is to check for errors during data transfer by having the receiving side send the same data back to the sending side. However, when data is transferred serially using three signal lines: a synchronization signal line, an input signal line, and an output signal line, even if the synchronization signal changes due to noise etc. and a deviation occurs in the synchronization signal, this can be corrected by echo back. It could not be detected. In other words, in the timing chart of FIG. 4, data of "L" and "H" are transmitted during the period when the synchronization signal is "L", but the receiving side echoes back by receiving the data, so the data is transmitted at t 1 and t ₁ . When "L" and "H" are detected at time _t2 , the transmitting side determines that each data transfer was positive. However, if the synchronization signal that is currently being transmitted changes to "L" as shown by the dotted line due to noise etc. and is input to the receiving side, the receiving side will use the data D ₁ during this changed period T as the transmitted data. You will recognize it.
Therefore, from the receiving side's point of view, this means that there is a shift in the synchronization signal, and data is read at an extra timing that does not originally need to be read and is mistakenly recognized as transmission data. Moreover, in this case, the receiving side returns echo back data _D2 , but
Since this echo back data _D2 is an "L" level signal and matches the data _D1 read by the receiving side, the transmitting side cannot detect that there is an error in the data transfer.

(c) Problems to be solved by the invention As described above, in the conventional technology, even if the synchronization signal changes due to noise or the like and causes a shift, it is not possible to detect this.

In view of the above points, the present invention provides a device that can reliably detect deviations in synchronization signals in a device that serially transfers data using three signal lines: a synchronization signal line, an input signal line, and an output signal line. It is.

(d) Means for solving the problem In order to solve the above problem, the data transfer device of the present invention connects the sending side and the receiving side with a synchronization signal line, an input signal line, and an output signal line, On the sending side,
a synchronization signal output device that alternately outputs a first level signal and a second level signal to the synchronization signal line, and a synchronization signal output device that outputs a first level signal and a second level signal to the synchronization signal line; a data output device that sequentially outputs data to the output signal line; and a data output device that outputs inverted data of the data output by the data output device in synchronization with the synchronization signal output device outputting a second level signal to the output signal line. an inverted data output device for outputting to the synchronizing signal line, and an echo back check device; a data input device that takes in data on a signal line, and when the signal level of the synchronization signal line switches from a first level to a second level, the data input by the data input device during the period of the first level is used as echo back data. an echo back data output device that outputs to the input signal line, and the echo back check device outputs the data input by the data output device and the data input at this time when the synchronization signal switches from the second level to the first level. The configuration is such that a shift in the synchronization signal is determined by determining whether the data matches the data output by the echo back data output device.

(e) Effect With the above configuration, in synchronization with the synchronization signal output device outputting the first level signal to the synchronization signal line,
The data output device outputs data to the output signal line. Next, when the synchronization signal output device outputs a second level signal to the synchronization signal line, in synchronization with this, the inversion data output device outputs the inverted data of the data output by the data output device to the output signal line. do.

In response to such an operation on the transmitting side, the data input device on the receiving side is
The data on the output signal line is taken in in synchronization with the level. Furthermore, when the data input device takes in data, the echo back data output device outputs the data as echo back data to the input signal line.

Then, when the signal output by the synchronization signal output device to the synchronization signal line switches from the second level to the first level, the echo back check device on the transmitting side checks the data output by the data output device and the input signal line at this time. It is determined whether the data outputted to the echo back data match, and if they match, it is determined that the data transmission was normal.

However, if the synchronization signal output device outputs the first level signal, noise is added to the synchronization signal line, and as a result, the second level signal is erroneously input to the receiving side. Based on this signal, the data that the receiving side inputs from the output signal line becomes inverted data. Therefore, in order for the echo back data output device to echo back this data, the echo back check device must determine whether the transmitted data and its inverted data match, and therefore determine that they do not match. Can be detected.

(F) Embodiment Figure 1 shows a control unit 1 on the transmitting side and a control unit 2 on the receiving side.
What is synchronization signal CL, data input SI, data output SO
It is connected by three signal lines. The control unit 1 uses a synchronization signal output device 3 that alternately outputs two levels of "H" and "L" signals to the synchronization signal line CL, and outputs the transfer data in synchronization with the output of the "L" level signal. Data for each bit is output sequentially to the signal line SO.
The data output device 4 includes a data output device 4 that outputs data to an output signal line SO, an inverted data output device 5 that outputs inverted data of output data to an output signal line SO in synchronization with an "H" level signal, and an echo back check device 6. The control unit 2 also includes a data input device 8 that inputs data on the output signal line SO when an “L” level signal is output on the synchronization signal line CL, and a data input device 8 that inputs data on the output signal line SO when a signal at the “L” level is output on the synchronization signal line CL, and When the level is switched from the "L" level to the "H" level, the echo back data output device 9 outputs the data inputted by the data input device 8 during the "L" level period to the output signal line SI as echo back data. include.

The operation of the data transfer device having the above configuration will be explained with reference to FIGS. 2 and 3.

In this example, 5-bit data “L・H・H・
This shows the case of transferring "L and H", and in the standby state, the synchronization signal output device 3 outputs "H" level to the signal line CL.When it comes to data transfer operation, first step S1 is started. This is to transfer bits, and the synchronization signal output device 3 sets the signal line CL to "L" for 400 μsec, and then in the next step S2, the synchronization signal output device 3 sets the signal line CL to "H". In response to such an operation of the control section 1, the data input device 8 of the control section 2 inputs the signal line CL to "L" when the signal line CL becomes "L".
If it is detected that it is longer than a predetermined period, it is determined that it is a start bit and data input is started. In the control unit 1, the data output device 4 outputs the most significant bit of data (“L” in this example) to the signal line SO in step S3, and at the same time, the synchronization signal output device 3 outputs the signal line CL in step S4. Set to “L” for 180μsec period. After that, in step S5, when the synchronization signal output device 3 sets the signal line CL to "H", the echo back check device 6 inputs the data on the signal line SI, and checks the echo back in the next step S6. .

By the way, when the data input device 8 takes in data, the echo back data output device 9 of the control unit 2 outputs the data as echo back data to the signal line SI, so in this case, the output of the signal line SI is It continues to be held at the "L" level. Therefore, both the transmission data and the echo back data (output Q) output by the data output device 4 are "L", and when the echo back check device 6 determines that both data match (A), the processing of the control unit 1 is performed. The process advances to step S7.

In step S7, the inverted data output device 5 outputs inverted data to the signal line SO. The timing to output the inverted data is when the synchronization signal output device 3 changes the output to the signal line CL from "L" to "H".
It is synchronized to switch to. and,
After outputting the inverted data to the signal line SO for 180 μsec, the process of the control section 1 proceeds to step S8.

In step S8, the echo back check device 6 again determines whether the transmission data output by the data output device 4 and the echo back data (output R) match. The check here is to determine the deviation of the synchronization signal, which will become clear later. If it is determined that both data are "L" and match (B), it is assumed that there is no shift in the synchronization signal and the process proceeds to step S9. Then, in step S9,
After confirming whether all data has been transferred, the process returns to step S3 and data transfer of the next bit is started.

However, if the echo back check device 6 detects in step S6 or S8 that the transmitted data and echo back data do not match, it sets an error in step S10. Then, when the echo back check device 6 makes an error determination (E), the operation returns to step S1, and the synchronizing signal output device 3 starts outputting again from the start bit.

The echo back check in step S6 is to determine whether the output data from the control section 1 has been reliably received by the control section 2 without being affected by noise or the like, based on the echo back data from the control section 2. . A feature of the present invention is that a shift in the synchronization signal is detected by the echo back check in step S8. In other words, the transmitted data is compared with the echo back data while outputting the transmitted data and its inverted data to the signal line SO. This allows the deviation of the synchronization signal to be corrected when noise is added to the synchronization signal line CL. Can be detected. For example, when noise shown by a dotted line appears on the signal line CL, the data input device 8 of the control unit 2 causes the signal line CL to go "L" due to this noise.
During the period _T1 , the data on the signal line SO is recognized as transmission data, resulting in an error in reading the data. However, according to the present invention, at this time, in order to output the inverted data "H" to the signal line SO following the "L" transmission data, the control unit 2 outputs this signal when the signal line CL becomes "L" due to noise. The inverted data "H" is read and echoed back to the signal line SI (output P). Therefore, when the echo back check device 6 checks the echo back at time t, it detects that the echo back data P is "H" while the transmitted data is "L", which causes a shift in the synchronization signal due to noise. can be detected.

This process is repeated, and when the data output device 4 detects in step S9 that all 5 bits of data have been transferred without causing a shift in the synchronization signal, the control section 1 ends the data transfer.

The data transfer device described above includes a control unit 1 on the sending side.
is a synchronization signal output device 3 that alternately outputs "H" level and "L" level signals to the synchronization signal line CL.
The data output device 4 outputs each bit of the transferred data to the output signal line SO in synchronization with the "L" level signal, and the inverted data of the output data is output in synchronization with the "H" level signal. It is equipped with an inverted data output device 5 that outputs to the signal line SO, an echo back check device 6, and a control section 2 on the receiving side.
is a data input device 8 that inputs data on the output signal line SO when a first level signal is output on the synchronization signal line CL, and an echo back data device that outputs the input data as echo back data to the input signal line. It is equipped with an output device 9. The echo back check device 6 checks the signal level of the data output by the inverted data output device 5 and the echo back data from the input signal line when the synchronization signal line switches from the "L" level to the "H" level. If they do not match, it is determined that the synchronization signal has changed due to noise or the like and has been supplied to the control unit 2.

(g) Effects of the invention According to the invention, in a device that serially transmits and receives data in a synchronous manner, a shift in the synchronization signal due to disturbances such as noise or static electricity can be detected, and a data transfer device with fewer errors is provided. .

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the connections between the control units on the sending side and the receiving side, Fig. 2 is a timing chart explaining data transfer, Fig. 3 is a flow chart showing the operation of the control unit on the sending side, and Fig. 4 is a timing chart illustrating the shortcomings of the prior art. 1... Sending side control unit, 2... Receiving side control unit, 3
... Synchronization signal output device, 4 ... Data output device,
5...Reverse data output device, 6...Echo back check device, 8...Data input device, 9...Echo back data output device, CL...Synchronization signal line,
SI...Input signal line, SO...Output signal line.

Claims (1)

[Scope of utility model registration request] The transmitting side and the receiving side are connected by a synchronizing signal line, an input signal line, and an output signal line, and the transmitting side has a synchronizing signal that alternately outputs first level and second level signals to the synchronizing signal line. an output device; a data output device that sequentially outputs data for each bit of transfer data to the output signal line in synchronization with the output of the first level signal by the synchronization signal output device; and the synchronization signal output device. an inverted data output device that outputs inverted data of the data outputted by the data output device to the output signal line in synchronization with outputting a second level signal; and an echo back check device; a data input device that takes in data on the output signal line in synchronization with the synchronization signal output device outputting a first level signal through the synchronization signal line; an echo back data output device that outputs data inputted by the data input device during the period of the first level to the input signal line as echo back data when switching from the level to the second level; is synchronized by determining whether the data output by the data output device matches the data output by the echo back data output device at this time when the synchronization signal switches from the second level to the first level. A data transfer device characterized by determining signal deviation.