JPH0332225B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a complementary semiconductor device.

[Conventional technology]

Complementary semiconductor devices have been increasingly used in recent years due to their excellent features such as low power consumption, high operating speed, stable operation and resistance to fluctuations in power supply voltage, and large noise margin. It is expanding. However, despite having these excellent characteristics,
It had drawbacks such as not increasing the degree of integration and causing the latch-up phenomenon. These drawbacks are interrelated, but the degree of integration has been alleviated by recent VLSI technology, and the biggest problem with complementary semiconductor devices is that there is no best way to prevent the latch-up phenomenon. .

A complementary semiconductor device generally has a structure as shown in FIG. 1, for example. That is, a P-type region 2 is formed on one side of an N-type silicon substrate 1, and MOS transistors 3 and 4 consisting of a source S, a drain D, and a gate G, which operate in opposition to each other, are formed in this region 2 and the substrate 1. However, when an input signal is applied to the input terminal _Vio , an output signal is obtained at the output terminal _Vput . In a complementary semiconductor device having such a structure including a CMOS circuit, the latch-up phenomenon occurs as follows. That is, the parasitic PNP transistor and the parasitic NPN transistor formed on the substrate 1 are coupled at their collectors and bases, respectively, and are connected to the P ⁺ diffusion layer of the p-channel MOS transistor 4, the N-type substrate 1, and the P-type well region 2. , N-channel MOS transistor 3
When this ^thyristor structure operates, a large current flows, inhibiting the operation of the complementary type semiconductor device, and eventually the complementary type semiconductor device A phenomenon that destroys semiconductor devices. This phenomenon is called the latch-up phenomenon. The conditions for this latch-up phenomenon are that a PNPN structure is formed and the external noise voltage is applied to a thyristor (PNPN structure).
to enter.

The thyristor turns on.

The turn-on state must be maintained.

The following three conditions must be satisfied. In order to prevent this latch-up phenomenon, at least one of the above three conditions should not occur.

Conventionally, such latch-up phenomenon has been prevented as follows. That is, the first means is to prevent the formation of a parasitic thyristor structure (PNPN structure) by connecting each MOS transistor 3, 4.
This is a method to separate the A prime example of this is SOS
(Silicon On Saphier). With this structure, each transistor is separated by sapphire or oxide, so a thyristor structure is not formed, and no latch-up phenomenon occurs. However, this method has the disadvantage that the manufacturing method is complicated.

The second means, as disclosed in Japanese Patent Application Laid-Open No. 50-98791, is to
This is a method of forming a layer that blocks an electrical path between a PNP transistor and an NPN transistor.
Although this method simplifies the manufacturing process, it requires a separate blocking layer, which increases the area of the semiconductor device and has the disadvantage that the degree of integration cannot be improved.

The third method is to make the base of the lateral PNP transistor shown in FIG. 1 longer and lower the current amplification factor of the transistor, thereby preventing the thyristor turn-on condition from being satisfied. This method also has the drawback that, like the second method, the area of the semiconductor device increases and the degree of integration cannot be increased because the base is made long enough to prevent it from being turned on.

[Problem to be solved by the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device that prevents the latch-up phenomenon, does not reduce the degree of integration, and does not require a complicated manufacturing method.

[Means and actions for solving the problem]

The semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in a surface region of the semiconductor substrate, and a first well region formed in a surface region of the semiconductor substrate, and a first well region formed in a surface region of the semiconductor substrate. a second well region of a second conductivity type having a resistance value per unit area smaller than that of the well region; a first conductive channel type MOS transistor formed in the first well region; and a second conductive channel type MOS transistor formed in the semiconductor substrate. a plurality of first complementary MOS circuits each including a channel MOS transistor; a first conductive channel MOS transistor formed in the second well region; and a second conductive channel MOS transistor formed in the semiconductor substrate. a plurality of second
The first complementary MOS circuit is formed with a high degree of integration, and the second complementary MOS circuit is characterized in that occurrence of a latch-up phenomenon is suppressed.

In this semiconductor device, since the resistance value of the second well region is smaller than that of the first well region, the resistance value of the second well region is smaller than that of the first well region.
When external noise is input to the second well region, a voltage drop generated in the second well region is smaller than a voltage drop generated in the first well region.

Among the causes of the latch-up phenomenon mentioned above,
The larger the voltage drop in the well region, the more likely the thyristor turns on. This is because when the voltage drop in the well region is large, the condition for turning on the bipolar transistor parasitically formed in the well region is easily satisfied.

In this invention, since the voltage drop occurring in the second well region is small, it is possible to suppress the latch-up phenomenon in the second complementary MOS circuit.

〔Example〕

Hereinafter, a case where an embodiment of the present invention is applied to a complementary MOS-RAM (random access memory) will be described with reference to FIGS. 2 and 3.
In the N-type silicon substrate 21 and P-type well regions 22 and 23 shown in FIG. 2, a large number of P-channel MOS transistors and N-channel MOS transistors similar to those in FIG. 1 are formed, respectively. Here, in order to make it easier to understand the structure of the P-type well regions 22 and 23, which is a feature of the present invention, illustration of these transistor elements is omitted. Similarly, in FIG. 3, only an N-type silicon substrate 31 and P-type well regions 32 and 33 are shown, and MOS transistors formed in these substrates and each region are shown.
Transistors are omitted.

In FIG. 2, the main surface region of the N-type silicon substrate 21 has a depth of 5 μm and an impurity concentration of 7×15 ¹⁵
cm ^-3 P-type well region 22 and 7×10 ¹⁵ cm ^-3 with a depth of 8 μm and the same impurity concentration as the P-type well region 22
A P-type well region 23 is formed. In this case, the resistance value per unit area of the P-type well region 22 is about 9 kΩ/□, and the resistance value per unit area of the P-type well region 23 is about 6 kΩ/□. Here, the resistance value per unit area means the P-type well region 22,
23 is the average resistance value to a current flowing in a direction parallel to the main surface area of the substrate 21.

The substrate 21 and the P-type well region 22 are provided with a large number of first transistors each composed of a P-channel MOS transistor and an N-channel MOS transistor.
A complementary MOS circuit is formed. These first complementary MOS circuits constitute circuits such as memory cells, row decoders, and column decoders in the RAM. Similarly, a large number of second complementary MOS circuits are formed in substrate 21 and P-type well region 23, each consisting of a P-channel MOS transistor and an N-channel MOS transistor. These second complementary MOS circuits constitute a power supply circuit, a signal input/output circuit, etc. within the RAM.

The first complementary MOS circuit and the second complementary MOS circuit differ in the likelihood of latch-up occurring. This is because the P-type well regions 22 and 23 have different resistance values per unit area. Among the three causes of latch-up mentioned above, the turn-on of the thyristor is more likely to occur as the voltage drop in the well region becomes larger. This is because if the voltage drop in the well region is large, the condition for turning on the bipolar transistor parasitically formed in the well region is easily satisfied.

In this embodiment, the P well region 22 is
Since the resistance value per unit area of the P-type well region 23 is smaller, when external noise is input to the P-type well regions 22 and 23, the voltage drop generated within the P-type well region 23 is lower than that of the P-type well region 22. smaller than the voltage drop generated within the

Therefore, the second complementary MOS constituted by the N-type silicon substrate 21 and the P-type well region 23
The circuit is less likely to latch up than the first complementary MOS circuit.

Furthermore, when the P-type well region 23 is formed deeper than the P-type well region 22 in this way, the width of the P-type well region 23 in the lateral direction is also formed wider due to the influence of lateral diffusion of impurities. It ends up.
Therefore, the degree of integration of the second complementary MOS circuit formed using the P-type well region 23 is higher than that of the first complementary MOS circuit formed using the P-type well region 22.
Inferior to MOS circuits.

Therefore, in this embodiment, a first complementary MOS circuit that is more likely to cause latch-up but has a higher degree of integration, and a second complementary MOS circuit that is less likely to cause latch-up but have a lower degree of integration are formed on the same substrate. Ru.

In a RAM, the power supply circuit and the input/output circuit occupy a small chip area, but are susceptible to external noise and are therefore susceptible to latch-up. On the contrary, memory cells, row decoders and column decoders have 60 to
Although it occupies a high chip area of 70%, it is difficult for external noise to enter, so latch-up is less likely to occur.

Therefore, as described above, the memory cells, row decoders, and column decoders are configured using the first complementary MOS circuit, and the power supply circuit and signal input/output circuit are configured using the second complementary MOS circuit. As a result, the occurrence of the latch-up phenomenon can be suppressed without causing a decrease in the degree of integration of the complementary MOS-RAM as a whole.

In the above embodiments, an example of an N-type silicon substrate has been described, but a P-type silicon substrate may also be used, and in that case, an N-type may be used as the opposite conductivity type. Further, an example has been described in which the P-type semiconductor regions 22 and 23 are formed to have depths of 5 μm and 8 μm, respectively, but the depths may be different, for example, a combination of depths of 4 μm and 10 μm or 3 μm and 7 μm, respectively. At that time, the impurity concentration of the P-type semiconductor regions 22 and 23 is approximately 10 ¹⁵ to 10 ¹⁶ cm.
^-3 is optimal. Furthermore, the P-type semiconductor region 22,
The circuit formed in 23 is not particularly limited, as long as the circuit that is likely to cause the latch-up phenomenon is formed in a deeper P-type semiconductor region.

Next, another embodiment of the present invention will be described with reference to FIG. This embodiment is also applied to a complementary MOS-RAM like the above embodiments. In FIG. 3, the main surface of an N-type silicon substrate 31 is covered with a phosphorescent material having a depth of 5 μm and an impurity concentration of 7×10 ¹⁵ cm ^-3.
P-type well region 32 and a P-type well region 32 with a depth of 5 μm and an impurity concentration of 1.6×10 ¹⁶ cm ^-3 higher than that of the P-type well region 32.
A shaped well region 33 is formed. in this case,
The resistance value per unit area of the P-type well region 32 is approximately
The resistance value per unit area of the P-type well region 33 is approximately 6 kΩ/□.

The substrate 31 and the P-type well region 32 are provided with a large number of first transistors each composed of a P-channel MOS transistor and an N-channel MOS transistor.
A complementary MOS circuit is formed. These first complementary MOS circuits constitute circuits such as memory cells, row decoders, and column decoders in the RAM. Similarly, a large number of second complementary MOS circuits each consisting of a P channel MOS transistor and an N channel MOS transistor are formed in the substrate 31 and the P type well region 33. These second complementary MOS circuits constitute a power supply circuit, a signal input/output circuit, etc. within the RAM.

In this embodiment, the P well region 32 is
Since the resistance value per unit area of the P-type well region 33 is smaller, when external noise is input to the P-type well regions 32 and 33, the voltage drop generated within the P-type well region 33 is lower than that of the P-type well region 32. smaller than the voltage drop generated within the

Therefore, the second complementary MOS constituted by the N-type silicon substrate 31 and the P-type well region 33
The circuit is less likely to latch up than the first complementary MOS circuit.

Furthermore, when the P-type well region 33 is formed with a higher impurity concentration than the P-type well region 22, due to the influence of lateral diffusion of impurities,
The width of the P-type well region 33 in the lateral direction is also increased. Therefore, the degree of integration of the second complementary MOS circuit formed using the P-type well region 33 is
This is inferior to the first complementary MOS circuit formed using the P-type well region 32.

Therefore, as described above, the memory cells, row decoders, and column decoders are configured using the first complementary MOS circuit, and the power supply circuit and signal input/output circuit are configured using the second complementary MOS circuit. As a result, the occurrence of the latch-up phenomenon can be suppressed without causing a decrease in the degree of integration of the complementary MOS-RAM as a whole.

In the above embodiment, an example using an N-type silicon substrate has been described, but a P-type silicon substrate may also be used. In that case, an N-type may be used as the opposite conductivity type. Furthermore, the P-type semiconductor regions 32 and 33 have impurity concentrations of 7×10 ¹⁵ cm ^-3 and 1.6×10 ¹⁶ cm ^{-3 ,} respectively.
Although an example has been described in which the impurity concentration is different, any impurity concentration may be used as long as the resistance value per unit area is different. For example, 8×10 ¹⁵ cm ^-3 and 2×10 ¹⁶ cm ^-3 or 4×
A combination of 10 ¹⁴ cm ^-3 and 1×10 ¹⁶ cm ^-3 may also be used.
Furthermore, the circuits formed in the P-type semiconductor regions 32 and 33 are not particularly limited, as long as circuits that are more likely to cause latch-up phenomena may be formed in the P-type semiconductor regions with a higher impurity concentration.

In addition, in the above embodiment, the case where it is applied to RAM was explained, but for example, ROM (read/read/
Even if it is applied to a semiconductor device such as a microprocessor (only memory) or a microprocessor, its effects remain the same. In other words, the ROM is also divided into areas such as memory cells, row decoders, column decoders, power supply circuits, and signal input/output circuits.The memory cells, row decoders, and column decoders have the largest area, while the power supply circuits and input The output circuit is susceptible to external noise, but its area is small. Therefore,
In ROM as well, the power supply circuit and signal input/output circuit, which are prone to latch-up, are formed using well regions with low resistance, and the memory cells, row decoders, and column decoders, which are less prone to latch-up, are formed using well regions with high resistance. By forming using the RAM, the same effects as in the above-mentioned RAM embodiment can be obtained. In addition, not only semiconductor memories such as RAM and ROM, but also microprocessors that include memories such as RAM and ROM on the same chip, the power supply circuit and signal input/output circuit in the memory are connected to well regions with low resistance. By forming the memory cell, row decoder, and column decoder using a well region having a large resistance value, the occurrence of latch-up can be suppressed without reducing the degree of integration.

〔Effect of the invention〕

As described above, according to the present invention, a complementary semiconductor device can be realized in which the occurrence of latch-up can be suppressed without reducing the degree of integration.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining a conventional complementary semiconductor device, FIG. 2 is a sectional view for explaining one embodiment of the present invention, and FIG. 3 is a sectional diagram for explaining another embodiment of the present invention. FIG. 21, 31...N-type silicon substrate, 22, 2
3, 32, 33...P-type semiconductor region.

Claims (1)

[Claims] 1. A semiconductor device having a memory circuit for storing data and a peripheral circuit for inputting/outputting signals or supplying power to the memory circuit, comprising: a semiconductor substrate of a first conductivity type; a first well region of a second conductivity type formed in the semiconductor substrate so that the resistance value thereof has a first value; and a second well region having a resistance value per unit area that is smaller than the first value. a second well region of a second conductivity type formed in the semiconductor substrate so as to have a second conductivity type;
a first conductive channel type formed in the well region;
A plurality of first complementary MOS circuits each including a MOS transistor and a second conductive channel type MOS transistor formed in the semiconductor substrate and forming the memory circuit, and a first complementary MOS circuit formed in the second well region. A conductive channel type MOS transistor and a plurality of second complementary type MOS circuits each including a second conductive channel type MOS transistor formed on the semiconductor substrate and forming the peripheral circuit, the peripheral circuit comprising: A second well region having a lower resistance value per unit area than the first well region.
1. A semiconductor device, characterized in that the well region is configured to suppress the occurrence of a latch-up phenomenon more than the memory circuit. 2. The first and second well regions have the same impurity concentration, and the second well region is formed deeper into the substrate than the first well region. The semiconductor device described. 3. The first and second well regions are formed at the same depth in the substrate, and the second well region has a higher impurity concentration than the first well region. The semiconductor device described.