JPH0332242A - Reception timing generation system for data signal - Google Patents

Abstract

PURPOSE:To allow a data signal reception circuit to surely receive a data signal with a timing margin by generating a reception timing signal of a data signal in the data reception circuit while a signal retarding an output signal of a clock signal transmission circuit by a prescribed time as a reference signal. CONSTITUTION:An input terminal of a delay circuit 7 connects to an output terminal of a buffer 1 and a clock signal outputted from the buffer 1 is retarded by a prescribed time and the result is used as a reference signal to generate a reception timing signal of a data signal in a data reception circuit 6. Thus, even when the delay in the leading time of the clock due to stray electrostatic capacity when plural A/D converters and D/A converters (CODEC) are in operation takes place, the gate of the data signal reception circuit 6 is opened in the delayed timing. Thus, the data signal reception circuit receives surely the data signal from the CODEC with a timing margin.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a reception timing generation method for a pig signal in a reception circuit of a data transmission system used in a PCM time-division automatic private branch exchange device, etc. It is something.

(Prior art) In a PCM time-division type automatic private branch exchange system, analog/digital and digital/
It has an analog converter (hereinafter referred to as CODEC) and sends and receives PCM data signals to and from the time division switching circuit.

At this time, in order to reliably receive the PCM data signal from the CODEC, it is necessary to set the data signal reception timing at an appropriate time in the time division switching circuit.

FIG. 3 shows the configuration of a circuit using a conventional data signal reception timing generation system. In the figure, 1 is a buffer that amplifies the power of a clock signal to drive a plurality of CODECs. 2 and 3°·n are CODECs, which convert the audio signals manually input from the audio signal lines of the respective CODECs into PCM data and send the data. A plurality of CODECs are usually used, and the number n means the final CODEC.

The purpose of the output end of the buffer 1 is to provide a reception timing generation method for data signals that can be used by all CODECs 2 to n.

[Structure of the Invention] (Means for determining the problem) In the present invention, the reception timing signal of the data signal in the data reception circuit is generated based on a signal obtained by delaying the output signal of the clock signal transmission circuit by a certain period of time. This achieves the above objectives.

(Function) In the present invention, the reception timing signal of the data signal in the data reception circuit is generated based on a signal obtained by delaying the output signal of the clock signal transmission circuit by a certain period of time. Therefore, even if a clock signal is delayed due to stray capacitance when multiple CODECs are operating, the gate of the data signal receiving circuit is opened at a timing corresponding to the delay. Therefore, the data signal receiving circuit can reliably receive the data signal from the CODEC with sufficient timing.

(Fruit color example) FIG. 1 shows an embodiment of the present invention, which differs from the conventional configuration shown in FIG. 3 in that the input terminal of the delay circuit 7 is connected to the output terminal of the buffer 1.

According to this configuration, when the number of connected C0DECs is small, the stray capacitance of the signal transmission path is small, so the clock No. 15 output from buffer 1 is expressed.

On the other hand, the output data signal from C0DEC is expressed as VPC'' in FIG. After that, at time tGA, the gate of the data signal receiving circuit 6 opens and receives data from CODEC.

When a large number of C0DECs are connected, the stray capacitance of the transmission line increases, so the rise and fall of the clock signal output from buffer 1 becomes slow, and its waveform becomes similar to that of the VCO shown in Figure 2(c). '

Therefore, the delay in the output timing of the data signal of C0DEC increases, so the timing of the output data signal becomes as shown in FIG. The gate of the data signal receiving circuit 6 opens after a delay time TI) after vco' rises after Co' is input, that is, at time tGB'(tGB'>tGA'). Even in this case, the data is received by the pig signal receiving circuit 6 with sufficient timing margin.

In this way, in this embodiment, the gate of the data signal receiving circuit 6 is opened at a timing corresponding to the delay in the rise time of the clock signal output from the buffer 1, so even if the delay in the data signal output timing of the C0DEC is large, The data signal receiving circuit 6 can reliably receive the output data signal from the CODEC.

〔Effect of the invention〕

As explained above, according to the present invention, the reception timing signal of the data signal in the data receiving circuit is generated based on the signal obtained by delaying the output signal of the cross/select signal sending circuit by a certain period of time. The data signal output from the data output circuit can be reliably received and transmitted without being affected by the number of data output circuits connected to the signal line.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of signals in the conventional system and the embodiment of the invention, and FIG. 3 is a circuit diagram showing the circuit configuration of the conventional system. 1. Buffer, 2.3-n-C0DEC, 5. Buffer, 6. Data signal receiving circuit, 7. Delay circuit.

Claims (1)

[Claims] It is composed of a clock signal sending circuit, a circuit that receives a clock signal from the clock signal sending circuit and sends out a data signal in synchronization with the clock signal, and a receiving circuit that receives the data signal from the data sending circuit. In a data transmission system, the data signal reception timing generation is characterized in that a reception timing signal of the data signal in the data reception circuit is generated based on a signal obtained by delaying the output signal of the clock signal transmission circuit by a certain period of time. method.