JPH033238B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention corresponds to a musical sound waveform generation method or apparatus that generates a frequency proportional to a frequency control value, and provides the following features:
This relates to a device that calculates frequency control values, and its purpose is to generate a portamento effect and to simplify the configuration by combining calculation methods that are compatible with the structure of the musical scale. Conventionally, various proposals have been made for musical tone generators using digital methods. Among these, digital data of a sine wave or a musical sound waveform is stored in memory, and this is read out sequentially to create a continuous musical sound waveform, which is then multiplied by envelope data corresponding to an envelope signal. hand,
By changing the amplitude value, a musical tone signal from the rise to the fall of the sound is formed. In order to change the frequency of the generated waveform, it is sufficient to skip over a predetermined number of samples and read each sample of the digital data, instead of reading each sample sequentially. If the jump number is J, the frequency can be set in direct proportion to J. Instructions on how to generate such signals were published in 1969 by THE MIT
The book “The Technology” published by PRESS
of Computer Music", pages 134 to 138. Also, the magazine IEEE Trans.on Audio
and Eectroacoustics, Volume 19, No. 1, 48-58,
1971 Document A Digital Frequency Synthesize
shows the specific configuration. A more specific and practical system based on these known examples is described in Japanese Patent Application Laid-open No. 58-65493. For these musical tone synthesis methods, it is necessary to generate and supply the jump number J. The present invention relates to a method for generating and supplying a jumping number J, and is particularly devised to efficiently generate various frequencies. Next, the relationship between the method of the present invention and the conventional example will be described. Conventionally, music synthesizers generate a key voltage V _K corresponding to each key on the keyboard, and then superimpose a frequency setting voltage V _F and a vibrato voltage V _V on this voltage to obtain V ₁ = (V _K + V _F + V _V ) is obtained through an index converter to obtain V ₀ =K ₁ e×p (V _K +V _F +V _V ), and the oscillation frequency of the voltage controlled oscillator (VCO) is determined by V ₀ . When the voltage V _F is 0V, the key voltage V _K
A frequency determined by , that is, a frequency corresponding to the musical scale (261.625 Hz for C ₃ ) is generated. Normally, the standard key voltage V _K is 1V per octave. When 1V is added as voltage V _F ,
It rises one octave and generates 513.25Hz. This hits C ₄ as well as the second harmonic of C ₃ . If a voltage other than 1V is applied as the voltage V _F , arbitrary harmonic components such as the third and fourth harmonic components can be obtained. The vibrato voltage V _V modulates the frequency up and down around the above frequency, but what is important here is that even if V _K and V _F take various values, the rate of frequency fluctuation, that is, the pitch The fluctuation of is a point that remains constant if V _V is constant. In Japanese Patent Application Publication No. 2003-130001, this method was replaced with digital calculation.
54−81824 is known. However, such conventional devices have drawbacks such as being unstable because they are made of analog circuits, and requiring a large number of highly accurate digital arithmetic units. The present invention solves these problems and provides a frequency control device that can be easily configured in practice. Another conventional example is JP-A-56-74298. This expresses frequency information on a cent scale and controls the generation of the portamento effect on that scale. However, since the entire range of the cent scale is expressed in a simple binary system, it has the disadvantage that cent errors occur at each pitch position of the 12 chromatic scale. The purpose of the present application is to provide a frequency control device that does not cause such problems. Another object of the present application is to provide a device in which the portamento effect is uniformly applied throughout a wide range of sounds, and the effect is not too fast or slow depending on the range. FIG. 1 is a block diagram of an electronic musical instrument employing the frequency control device of the present invention. 1 is a keyboard section, 2 is an operation section consisting of a tone tablet switch, a vibrato effect on/off switch, a volume for setting the depth of the vibrato effect, etc., and 3 is a central processing unit (CPU), which is used in computers etc. 4 is a read/write storage device (random access memory, usually
5 is a read-only storage device (read-only memory, usually called ROM) in which the program that determines the operation of the CPU 3 is stored; 6 is a
A ROM 7 stores envelope parameters among parameters for synthesizing timbres, and a ROM 7 stores data related to frequencies among parameters for synthesizing timbres. 8 is a frequency control device of the present invention, 9 is the above-mentioned sine wave generator, 10 is an envelope data generator, 1
1 is a multiplier that multiplies the sine wave and envelope data; 12 is a time slot control device that adds predetermined results from the time-division multiplexed multiplication results or replaces them with the order of time-division multiplexing;
13 is a time-division multiplexed phase modulator, 14 is a digital-to-analog converter, and 15 and 16 are electroacoustic transducers. Keyboard section 1, operation section 2, CPU 3, RAM 4,
ROM5, ROM6, ROM7, frequency control device 8, and envelope data generator 10 are coupled by a data bus, an address bus, and a control line. The method of connecting the data bus, address bus, and control line in this way is as follows:
This is a well-known method for configuring minicomputers and microcomputers. Eight to 16 data buses are used, and data is transmitted and received on these bus lines not in one direction but in multiple directions in a time-division manner. A plurality of address buses, for example 16, are prepared, and normally the CPU 3 outputs the address code, and other parts receive the address code. As the control line, a memory request line (MREO), an I/O request line (IORQ), a read line (RD), a write line (WR), etc. are usually used. MREQ indicates reading and writing memory
IORQ indicates retrieving the contents of an input/output device (I/O), RD indicates timing to read data from memory or I/O, and WR indicates timing to write data to memory or I/O. Using such a control line,
An example of this is Zilog's microprocessor Z80. Next, the operation of the electronic musical instrument shown in FIG. 1 will be described. The keyboard section 1 is configured such that a plurality of key switches are divided into a plurality of groups, and the ON-OFF states of the key switches in the groups can be collectively sent to the data bus. For example, for a 5-octave keyboard, 61
The keys are divided into 11 groups, 10 groups of 6 keys (half octave) and 1 group of only 1 key, and each group is assigned an address code.
Allocate one by one. An address code indicating one of the above groups arrives on the address line,
When IORQ and RD are applied, the keyboard section 1 decodes the address code and outputs 6-bit or 1-bit data indicating ON/OFF of the key switches in the corresponding group to the data bus. These can be constructed using decoders, bus drivers and some gate circuits. Of the operating section 2, the tablet switch can have the same configuration as the keyboard section 1. Regarding the setting state of the volume, the voltage output from the volume is converted into a digital code by an analog-to-digital converter, and this is read out using the address code and control lines IORQ and RD. The CPU 3 reads the instruction code from the address of the ROM 5 that corresponds to the code of the internal program counter, decodes it, performs arithmetic operations,
Performs tasks such as logical operations, reading and writing data, and jumping instructions by changing the contents of the program counter. The steps for these tasks are
It is written by ROM5. First, CPU3
A command for importing data of the keyboard section 1 is read from the ROM 5, and codes indicating ON/OFF of each key of the keyboard section 1 are fetched for each group. and,
The key code being pressed is assigned to a finite channel of the tone generator. Next, the CPU 3 sequentially reads a group of instructions from the ROM 5 for importing data from the operating section 2, decodes them, outputs the address code and control signals IORQ and RD corresponding to the operating section 2, and outputs them to the data bus. The CPU outputs the code that expresses the switch and volume status of the operation section 2.
Load within 3. Then, the CPU 3 knows which tone of musical tone signal should be synthesized. Now that it has become clear which channel of the musical tone generation section should generate which tone at which frequency, the CPU 3 selects the desired tone from the ROM 7 which stores data regarding the frequency of each tone. The address code storing the frequency parameters and the control signals MREQ and RD are output, and the desired frequency parameters are read out onto the data bus, taken into the CPU 3, and written into the frequency control device 8. In order to write, the frequency control device 8
CPU3 outputs the address code corresponding to the data register provided inside the CPU3, and at the same time outputs the IORQ and
When WR is output, data representing the frequency parameter being output on the data bus at the rising edge of the WR signal is written into the data register. Next, timbre parameters representing the contents of the timbre to be output are read from the ROM 6 and written into a register inside the envelope generator 10. Next, when a sound output command is given to both the frequency control device 8 and the envelope generator 10, the frequency control device 8 gives the jump number J to the sine wave generator 9, and the envelope generator 10 generates envelope data. . The sine wave data output from the sine wave generator 9 and the envelope data are multiplied to give an envelope to the sine wave. The sine wave data and envelope data are generated by being time-division multiplexed, respectively. Time division multiplexing is, for example, 160 multiplexing, and 20 sine waves are assigned to each channel, providing 8 channels. Normally, one musical tone is synthesized by combining 20 sine waves. Therefore, as known from the Fourier series formula, 20 sine wave data are added. For this purpose, the time slot converter 12 performs data addition between time slots. The time slot converter adds predetermined data from among the sine wave data strings modulated with envelope data, which are time-division multiplexed and input into 160 time slots, to reduce the number of time slots, or This is a device for exchanging time slots like the time division multiplex converter described in Japanese Patent Publication No. 10324/1983. The time-division multiplex phase modulator 13 is a digital musical tone modulator disclosed in Japanese Patent Application Laid-Open No. 58-83894.
In this method, multiple types of modulation are performed simultaneously using time division multiplexing. Time division multiplex phase modulation device 13
The output of
It is output from 6. Although not shown in FIG. 1, the time slot converter 12 and time division multiplexing phase modulation device 13 are also connected to the CPU 3 via address buses, data buses, and control lines, and are controlled by the operating section 2. The time slot conversion and modulation conditions can be changed and set in accordance with the tone color and modulation effect settings that are made at the same time. In the frequency control of the present invention, first, the note octave of each key, the frequency of each harmonic, etc. are arranged on a cent scale and processed. The note and octave position of the fundamental wave of the musical tone to be output, the position of harmonics relative to the fundamental wave, the relative shift of non-harmonics, etc. are expressed in cent units, and the cent address on the cent point degree is expressed. Addition and subtraction are performed to obtain the cent address for the cent value of the actual frequency component, and this is subjected to exponential conversion. In order to digitize the system and find the jump number J for a large number of spectra, consideration is given to quantizing and handling one octave on the cent scale and performing arithmetic processing by time division multiplexing. Also, the timing is considered so that the calculated J is appropriately transferred to the sine wave generator 9. The present invention realizes a function, as a part of an electronic musical instrument as shown in FIG. This relates to the frequency control device 8. One embodiment is shown in FIG. The frequency control device in Fig. 2 includes a data bus DB,
Address bus ADR, control lines IORQ and WR
It is connected to the CPU 3 through the chip select line CS, receives frequency parameters, and is connected to the address bus by the microcomputer interface circuit (MIF) 25.
The code of ADR is decoded and written to the internal register group, and the required number of Ji is calculated through the internally provided mechanism for calculating the jump number J.
The signal is supplied to a sine wave generator 9. First, the constituent elements will be explained. 21 is a program counter (PC) that supplies timing pulses; 22 is a timing pulse that extracts logic from timing pulses to create necessary address codes, or receives control flag (FLG) signals to create control signals. Generator (TPG), 23 is a sequencer (SEQ) which is read out by timing pulses and control signals and stores the contents and procedures of arithmetic operations and logical operations, which will be described later.
24 is an instruction that decodes the contents of the sequencer and outputs address codes, output command signals (OC1-12), write command signals (WR0-3), operation command signals (OP code), etc. It is a decoder. 25 is the microcomputer interface circuit (MIF) described earlier. 26 is an arithmetic unit (ALU) that performs addition, subtraction, and comparison between two inputs, the A bus and the B bus, outputs the operation result to the C bus, and records the sign, upper bit, etc. of the operation result. Output as FLG. FLG is
It is supplied to TPG22. 27 is the working register (WREG)
It consists of two words of memory, WREG1 and WREG2, and accepts input from the C bus and supplies output to the B bus. AD2 selects one of the two words and writes it at the rising edge of WR1, and provides an output when OC8 is "H". 28 is a RAM consisting of 160 words x 15 bits, which receives input from the C bus and supplies output to the D bus. The 160 words are divided into 8 channels of 20 words each, and any one word within the 20 words can be converted into a 5-bit address code.
Specified by AD1, any one of the 8 channels
The channel is selected with the 3-bit address code AD4, data on the C bus is written at the rising edge of WR2, and the output remains on the D bus. However, the upper five bits of the output are supplied to the buffer memory 29. Buffer memory 29 is 160 words x
17-bit RAM, C bus data and RAM2
The upper 5 bits of 8 are accepted as input. 160
The words are divided into 8 channels of 20 words each, and one word out of the 20 words is used as an address code.
Select with AD3, select one of the 8 channels with address code AD4, write input data at the rising edge of WR3, and output when OC9 is "H". The output of buffer memory 29 is supplied to octave shifter 30. Based on the code of the upper 5 bits of the buffer memory 29, the lower data is bit-shifted by a predetermined number of bits and output. This output is transferred to a register corresponding to a predetermined address among the registers provided inside the sine wave generator 9 and storing the jump number. 33 is note octave register (NOD(n))
The latest note octave data is accepted from the CPU 3 via the data bus DB, and output to the A bus when necessary. Write is performed with MRW2, and read with OC2. 34 is a note octave register (NOD(n-1)) which accepts the previous note octave data from the CPU 3 via the data bus DB, and outputs it to the B bus when necessary. It also receives and stores intermediate processing data from the B bus. Write data from DB using MRW3,
Writing from the B bus is performed using WRO, and output to the B bus is performed using OC3. 35 is a harmonic data memory (HMD), which is composed of a ROM of 64 words x 13 bits. Which of the 64 words to select is determined by partial number memory 3.
It is determined by the 6-bit code output by 6. Partial number memory 36 is 20 words x 6
Bit RAM accepts input from data bus DB. Select 1 word out of 20 words with address code AD1 and write at the rising edge of MRW4. Output is always harmonic data memory 35
is supplied to The output of the harmonic data memory is output to the A bus when OC4 is "H". 3
7 is non-harmonic memory (INH), 20 words x 6
Consists of bits of RAM. One word among the 20 words is selected by address code AD1, and data on data bus DB is written at the rising edge of MRW5. When OC5 is "H", it is output to the A bus. 38 is an index conversion table (E×
P) and is configured by ROM. The D bus is input, and when OC6 is "H", its contents are output to the A bus. 39 is a differential index conversion table (DE×
P) is composed of ROM, takes the D bus as input, and outputs the stored contents to the B bus when OC6 is "H". The contents of these two tables will be described later. 40 is a gate which inputs the D bus and outputs to the B bus when OC7 is "H". 32 is a portamento register (PRT) which accepts a code representing portamento speed from the data bus and stores it at the rising edge of MRW1. 31 is a portamento data converter which generates frequency increase/decrease data based on the contents of the portamento register 32, and when OC1 is "H"
Output to the A bus when . The same contents as the normal portamento register 32 are output. 42 is a vibrato data generator, which generates a code representing a vibrato waveform, and when OC10 is “H”
When OC11 is "H", VIB (n) is output to the A bus, and when OC12 is "H", VIB (n-1) is output to the B bus. VIB(n)
represents the current vibrato data and VIB(n
-1) represents the previous vibrato data. 41
is a status flip-flop (SFF) that stores data on the data bus DB at the rising edge of MRW6.
The contents are supplied to the TPG22. The TPG 22 outputs an interrupt signal INT when the frequency control device requests new data from the external CPU 3.
The interrupt vector code indicating the interrupt contents is sent to the data bus.
Output on DB. When the output command signals OC1 to OC12 are "L", the outputs of the memories and registers corresponding to them become high impedance and A
We are trying not to have any impact on buses or B buses. <Data Structure> Next, the data structure before and after the index conversion mechanism C for frequency control performed in the present invention will be described. One octave has a frequency ratio of 1:2. As a number directly proportional to the frequency, the jumping number J
is defined as follows. Assume that the memory that stores one waveform of a sound source consists of ²¹⁸ words (samples). Set the sample readout frequency to _c
If KHz is used, the frequency of the output waveform will be _c /2 ¹⁸ Hz when all samples are read out one sample at a time.
This corresponds to the jump number J=1. Generally, the frequency for the jump number J can be expressed as = _c / 2 ¹⁸ × J ... (1). In the present invention, one octave is quantized on the cent scale, and by exponential transformation, the calculated frequency value expressed in the cent scale is converted into an interlaced number that is directly proportional to the frequency. The method of index conversion will be described next. One octave is expressed in cents,
It will be 1200 cents. The ratio of the two frequencies _A and _B in cent scale CE is as follows. CE (cent) = 1200log ₂ ( _A / _B ) …(2) If the jump numbers of frequencies _A and _B are J _A and J _B , then Let J _B correspond to C on the equal-tempered 12 chromatic scale,
And if its value is 2048 and J _A is expressed as J, then becomes. If this is written for the range of CE = 0 to 1200 (cents), it will look like Figure 3 A. Equation (5) is a curved line, which can be approximated by a broken line as follows. If you divide CE (0-1200) into 12 equal parts, you will get 100 cent intervals. This corresponds to the chromatic scale of 12 equal temperaments. Divide the 100 cents into 8 equal parts, making them 12.5 cents apart. Doing this will result in 12 x 8 = 96 points. Let J be J _i for these 96 points CE _i =12.5×i (i=0 to L-1, L=96). Between i and i+1, further divide 12.5 cents into 8 equal parts. CE _i,j = 12.5i + 12.5/8j ...(7) (i = 0 ~ L-1, L = 96 j = 0 ~ M-1, M = 8) CE _i,j of equation (7) ( For j=1 to 7), linearly interpolated values are used. That is, J _i,j becomes the following formula. In general J _c : Number of jumps at the reference point L: Number of divisions in one octave M: Number of divisions within the linear interpolation interval i = 0, 1, 2, L-1 j = 0, 1, 2, M-1 Expressed as Can be done. As mentioned earlier, if L=96 and M=8
The 1200 cent interval is quantized into 768 points at intervals of 1.5625 cents. The error will be less than ±0.78125 cents. Assign addresses to these 768 points.
Let this be the cent address. Next, a method for calculating J _i,j in equation (8) will be explained. According to Figure 3, J is for one octave,
It is represented by 2048 to 4096 in binary 12 bits. Figure 3B shows the range of CE=0 to 100 (cents) in detail. Within 100 cents
It is divided into equal parts such as 12.5 cents. Equation (8) is It can be expressed as Express i as a binary coded 96-decimal number. Since 96 = 4 x 3 x 8, the upper digits can be represented by two binary digits, the middle digit by a binary coded ternary number, and the lower part by three binary digits. Since 2 bits are sufficient for the middle level, the total is 7 bits. j is represented by three binary digits and is the lower order of i.
In other words, 96 x 8 = 768 points within 1200 cents is the 4th point.
It can be represented by 10-bit codes _N3 to _N0 and _S5 to _S0 in Figure A. This code is called a cent address, of which N ₁ and N ₀ are expressed in binary coded ternary notation. For such a value of (i, j), J _i,p
Prepare 96 values for E×P38 in FIG. Assuming 96 addresses, each with 12 bits, 96×
12 = 1152 bits of ROM. This J _i,p corresponds to the first term of equation (10). Next, as a difference, it is a part of the second term of equation (10). Prepare in DEXP39 in Figure 2. Since the maximum value of DJ _i,j is DJ _95.7 =25.784 when i=95 and j=7, DJ _i,j can be expressed as a 5-bit binary number.
Furthermore, (i, j) has 96×8=768 ways. Therefore, 768 St. Addresses, 768 x 5 =
It becomes a 3840-bit ROM. The cent address input to the ROM of the EXP38 is the 7 bits {N ₃ to N ₀ , S ₅ to _{S 3 }} in FIG. N ₀ , S ₅
~S ₀ } 10-bit code. EXP
By adding the outputs of 38 and DEXP39, the equation (10) can be obtained.
J _i,j is obtained as a 12-digit binary number. FIG. 4A represents a binary number or extended cent address representing a quantized pitch on a cent scale. O ₄ , O ₃ , O ₂ , O ₁ , O ₀
represents an octave. N ₃ , N ₂ , N ₁ , and N ₀ represent each note of the 12 equal-tempered chromatic scale within one octave. Of these, (N ₁ , N ₀ ) is binary evolution 3
Represents base numbers (0, 0), (0, 1), (1, 0), and (1, 1) does not occur. Therefore, (N ₃ ,
N ₂ , N ₁ , N ₀ ) are decimal numbers. In Figure 5 (N ₃
~N ₀ ) and the musical scale. _S5 , _S4 , _S3 , _S2 ,
S ₁ and S ₀ are 6-bit binary numbers that represent each pitch of the semitone interval divided into 64 equal parts. One octave is
Since it is 1200 cents and a semitone is 100 cents, {S ₅
~S ₀ } represents an interval of 100 cents at intervals of 1.5625 cents. FIG. 4B shows the data format of NOD(n), where the lower 4 bits indicate a note and the upper 4 bits indicate an octave. NOD(n) corresponds to the fundamental frequency ₁ of the musical tone with the specified octave and note. Figure 4c shows harmonic data representing the ratio of the frequency _R of each harmonic component included in a harmonic musical tone to the fundamental frequency ₁ in cents.
HMD _k . HMD _k = 1200log ₂ ( _R / ₁ ) ... (12) (k = 1, 2, 3, ..., 64) expressed in binary. (H ₁₂ ~ _{H 0} )
Using 13 bits, the accuracy is ±0.78125 cents,
2 ⁸ = up to 256th harmonic can be achieved. {H ₇ , H ₆ } are expressed in binary coded ternary numbers like {N ₁ , N ₀ }. FIG. 4D is a format of inharmonicity data INH _k representing non-harmonicity. INH
_is expressed as _a deviation of several cents from the HMD data in FIG. FIG. 4E expresses transient or steady fluctuations such as vibrato and glide on a cent scale. If the range of fluctuation is within ±100 cents, it can be represented by a 7-bit code {V ₆ to V ₀ }. Of these, _V6 becomes the sign bit. The procedure for determining the desired jump number J from the data shown in FIG. 4 will be explained. first,
Each symbol shall have the following meaning. (1) NOD(n): The pitch frequency for note octave data (pitch information) at time n, expressed in cents address. (2) HMD _k : The cents expression of the kth positive harmonic frequency relative to the fundamental frequency. Once expressed in binary (positive harmonic difference cent address) HMD _k = 1200log ₂ ( _R / ₁ ), _R = k ₁ (k = 1
，
2, 3...64) ...(13) (3) INH _k : Frequency deviation from the k-th positive harmonic frequency expressed in cents and in binary (non-harmonic difference cent address). If _k = k ₁ + d _k , then INH _k = 1200log ₂ (k ₁ + d _k /k ₁ )... (14) is the basic formula, but when INH _k exceeds 100 cents, INH of less than 100 cents is To find _k , do the following. INH _k+p = 1200log ₂ k ₁ + p ₁ + (d _k − p ₁ )/k ₁ +
p ₁ ...(15) (p = 0, 1, 2, 3, ... and d _k -p ₁ 0) In other words, it is a harmonic of the kth order shifted by d _k , but it is expressed as (k + p ) harmonic to (d _k −
p ₁ ). (4) VIB(n): Displays the frequency deviation due to vibrato and glide at time n in cents,
and expressed in binary. (Modulation cent address) From the above variables, the cent display of the frequency of the k-th harmonic, that is, the cent address, can be determined with the symbol LOGJ (i,
j), LOGJ _i,j = NOD (n) + VIB (n) + HMD _k +
INH _k ……(16) becomes. LOGJ _i,j has the data format shown in FIG. 4A. Among these, {N ₃ , N ₂ , N ₁ , N ₀ , S ₅ ,
The 7 bits of S ₄ , S ₃ } are in 96-decimal notation and represent i in equation (10). Similarly, the three bits {S ₂ , S ₁ , S ₀ } represent j. These codes can be converted to the EXP38 mentioned above.
By giving the address data of the exponent conversion table of DEXP39 and the differential exponent conversion table, exponent conversion can be performed according to equation (10). This is expressed by the following formula. J _i,j = EXP〔LOGJ _i,p 〕＋DEXP〔LOGJ _i,j 〕
...(17) From Figure 3A, the exponent conversion table has a range of only one octave. J _i,j indicates a value within this range. If the range exceeds an octave, J _i,j may be bit-shifted according to the octave data {O ₄ , O ₃ , O ₂ , O ₁ , O ₀ } shown in FIG. 4A. For example, when {O ₄ -O ₁ }=(00011), it is sufficient to shift 3 bits upward. As for how many bits to shift, use the sine wave generator 9
All you have to do is match it to the bit position. The above describes the data structure and the number of jumps J based on it.
The calculation procedure has been clarified. Although it is possible to realize a configuration in which equations (16), (17), and (18) are executed all at once, the embodiment of the present invention (Fig. 2)
Now, let's do it step by step. Various methods can be considered to execute equations (16), (17), and (18) step by step. Table 1 shows the procedure according to the configuration shown in FIG. 2 described above.

[Table] In Table 1, of instruction groups A, B, and C, A
and B show the procedure for calculating the jump number J for 8 channels and 20 spectra in each channel. Instruction group A is instructions 4 to 7, instruction group is instruction 8.
It consists of ~11. The content of each command is indicated by the command content. For example, instruction 4 is NOD(n)
and VIB(n), and write the working register
This means storing in WREG2. Instruction 5 reads the contents of working register WREG2 and harmonic data HMD(I), adds them, and stores them in WREG2. Instruction 6 is WREG
2 contents and Inharmonity data INH(I)
are added and stored in register LOGJ (K, I). Instruction 7 uses the contents of register LOGJ (K, I) as an address code and converts it to an exponent conversion table.
It is applied to EXP 38 and differential index conversion table DEXP 39, and the respective outputs are added and stored in buffer memory BUF (K, I) 29. Here, I represents a processing time slot (PTS), which will be described later, and also represents the spectrum number in each channel. I=1, 2,...20.
K stands for channel time slot (CHS). K=1, 2, ..., 8. CHS
This will be discussed later. Regarding instruction group B, the meaning of the operation contents can be similarly read from Table 1. △ in instruction 8 is set to zero. Command group A is executed when note octave data NOD(n) is changed, and thereafter command group B is executed. In instruction group B, NOD(n), HMD(I), and INH(I) do not change, so these calculations are not performed and the previous value LOGJ is
Subtract VIB(n-1) from (K, I) to get VIB(n)
Perform calculations on the new value of and perform exponential transformation. When the note octave data NOD(n) is updated, the program returns to instruction group A, and then executes instruction group B again. In Table 1, ITS is an instruction time slot, and there are ITS1 to ITS4, indicating that instructions 04 and 8 are executed in ITS1. Also shown are write lines, write pulses, and output control lines that are activated when each instruction is executed. To execute the above instructions, the program counter 21, timing pulse generator 22, sequencer 23, and instruction decoder shown in FIG. 24 needs to work. less than,
Explain timing. FIG. 6 is a diagram showing the timing of the embodiment of FIG. FIG. 6A shows a sample arrangement of sinusoidal waveforms, and the sampling period of one sinusoidal waveform is 20 μs. FIG. 6B is an enlarged view of 20 μs, in which there are 8×20=160 time slots and 160 samples.
Each supply is processed in 125ns steps. Channel 1 (CH1) has 20 samples.
The same applies to CH2 to CH8. On the other hand, Fig. 6C shows A
This is the timing to calculate the jump number J in synchronization with . Channel time slots CHS 1 to 8 are provided in units of 160 μs.
In CHS1, J calculation for channel 1 is performed,
The J calculations for the corresponding channels are performed in the following order. J calculation for each channel is repeated at a cycle of 160×8=1280 μs (1.28 ms). FIG. 6D shows the inside of each channel time slot CHS, and as an example, CHS1 is enlarged.
In CHS1, there are processing time slots PTS 1 to 32 in units of 5 μs. PTS(I), I=
1 to 20 calculates the number of jumps that determine the frequencies corresponding to the 20 spectra (sine waveforms) in channel 1. And 2.5μs in the first half of PTS21
The 20 calculated J values are transferred to the sine wave generator 9 (FIG. 1) in 125 ns steps as shown in FIG. 6F. The timing of this transfer is
Different for CHS1-8. For example, in CHS8, PST
It will be executed in the second half of 24th. FIG. 6E is an enlarged view of the contents of each processing time slot PTS1 to PTS20. PTS1-20 are divided into four parts, instruction time slots ITS1-4, respectively. Each is 1.25μs long. The instructions in Table 1 above are executed in these instruction time slots ITS. During PTS1 to PTS20, calculations are mainly performed in the ALU 26 in the embodiment shown in FIG. Between PTS21 and PTS32, new data is written mainly to MIF25 in FIG. 2 via data bus DB, and VIB(n) and VIB(n-1) data are updated. There are various methods for creating the timing shown in FIG. FIG. 7 and FIG. 8 show an example. Figure 7 shows a timing counter, and 51 is a 14-stage counter with CK as input.
Output P ₀ to P ₁₃ . P ₀ to P ₂ perform binary coded quinary counting, and P ₃ to P ₁₃ perform binary counting.
{P ₅ , P ₄ } are codes representing instruction time slots ITS1 to ITS4, 5 bits of {P ₁₀ to P ₆ } are codes representing processing time slots PTS 1 to 32, {P ₁₃ ,
P ₁₂ , P ₁₁ } is the channel time slot CHS
It corresponds to a 3-bit code representing 1 to 8. The counter 52 is a 20-decimal counter consisting of five stages.
Output {Q ₄ , Q ₃ , Q ₂ , Q ₁ , Q ₀ }. Counters 51 and 52 are synchronized. counters 51 and 5
From the output of 2, the timing pulse shown in Figure 8 is obtained.
Created inside TPG22. CK is 125ns
(8MHz) frequency. _P1 , _P2 , _P3 , _P4 , _P5
Therefore, WRC, ITS1-4, and WRC1-4 are obtained. ITS1 to 4 signals are the output command signals shown in Figure 2.
WRC, the signal that creates OC1-12
1 to WRC4 are signals from which write command signals WR0 to WR3 are generated. Figure 9 shows the address codes AD3 and AD4 added to the buffer memory 29 and the output command signal OC.
9. This is an example of a circuit that generates the write command signal WR3. Address code AD4 is {P ₁₃ , P ₁₂ , P ₁₁ },
In AD3, either {P ₁₀ to P ₁₆ ) or {Q ₄ to _{Q 0} } is selected by the selector 69. WR3 is a processing time slot created by the AND gate 70 with invert input and the OR gate 71 with invert input.
WRC4 corresponding to ITS4 in PTS1-20
It is. And gate 60, 61, 62, 63
detects {P ₁₀ , P ₉ , P ₈ }={1,0,1}.
This corresponds to PTS21-24. At this time, the selector 69 selects _Q4 to _Q0 . EXOR gates 64, 65, and 66 perform a match determination between {P ₇ , P ₆ , P ₅ } and {P ₁₃ , P ₁₂ , P ₁₁ }. The AND gate 67 selects the half section of the PTS that matches the CHS number among the PTS21 to 24, and outputs OC9 when the output is "H". Therefore, to summarize, in ITS4 among PTS1-20, AD4
and AD3 designate K and I, respectively, output WR3 at ITS4, and write to buffer memory 29 (BUF (K, I)) of instruction 7 or 11 in Table 1. CHS between PTS21-24=K
OC9 becomes “H” for 2.5 μs corresponding to
The contents of I=1 to 20 of BUF (K, I) are output according to address codes AD4 and AD3. FIG. 10 shows an example of the format of the instruction code stored in the sequencer 23 in FIG. 2 bit OP code for operation,
It consists of a 3-bit destination code that indicates the data transfer or storage destination, a 3-bit source 1 code that indicates the register from which the data is taken out, and a 4-bit source 2 code. The meaning of each code is shown in FIGS. 10B-E. The OP code specifies the function of the ALU 26. The operations of the 12 instructions shown in Table 1 are expressed by the instruction codes shown in FIG. Figure 10 E ZERO
means to output ZERO to the A bus. Based on the instruction code in Figure 10 and the CHS, PTS, ITS, write line, output control line, etc. in Table 1, using the same idea as illustrated in Figure 9,
The instruction decoder 24 and circuits that generate necessary control signals and timing pulses can be designed. FIG. 11 shows the timing of execution switching between instruction groups A and B in Table 1. From the top, channel time slot, operation execution, J transfer, interrupt pulse, data transfer, and KON flag are shown. Operation A or B is the processing time slot
PTS 1 to 20 (Figure 6) are executed 20 times.
At the end of the 20th time, the interrupt pulse INT is as shown in Figure 2.
The TPG 22 outputs the signal to the CPU 3 shown in FIG.
At this time, a code {P ₁₃ , P ₁₂ , P ₁₁ } indicating CHS8 is simultaneously outputted to the data bus DB in FIG. 2 as an interrupt vector. The CPU 3 reads this interrupt vector {P ₁₃ , P ₁₂ , P ₁₁ } and executes the next CHS.
is 1, and if the pitch to be played on channel 1 is changing, data transfer is performed.
Data transfer is performed from the data bus of the CPU 3 to the data bus DB shown in FIG. And NOD
(n) Write predetermined data to 33, PNO 36, INH 37 and status FF 41. and,
In particular, it sets the KON flag flip-flop (FF) contained in the status FF. KON
The flag indicates that the pitch of the sound corresponding to CHS1 has been changed. When the KON flag is “1”,
Instruction group A is read and executed during CHS1. When the execution is finished, an interrupt pulse is generated again.
An interrupt vector indicating CHS1 is output. at the same time
KON flag FF is reset. interrupt pulse
Corresponding to INT and interrupt vector {P ₁₃ , P ₁₂ , P ₁₁ }
Does CPU3 remain at the previous pitch in the next CHS2?
Data transfer will not occur if the same pitch is to be played. Therefore, the KON flag remains at "0". At this time, instruction group B is 20
Executed times. The instruction group A is a program that calculates J based on new NOD(n) data, and the instruction group B is a program that corrects only changes in vibrato data with respect to the previous J. The reading and switching of the instruction groups A and B are performed within the time indicated by the processing time slot codes {P ₁₀ -P ₆ } of the counter 51 in FIG. This can be done by reading out groups A and B, selecting one using the KON flag, and outputting it. In the embodiment of FIG. 2, the amount of data to be transferred from the CPU 3 to the frequency control device of the present invention is as follows:
NOD(n) 1 word, PNO 20 words, INH
20 words, 1 word for status FF, 1 word for PRT
A total of 43 words is sufficient. In the above description, one vibrato data generator 42 is common to eight channels. In case of glide effect, glide data GL(n,k)
and GL(n-1,k), (k=1,2,...,8) are provided independently for each channel, and each CHS1
By outputting the respective data corresponding to 8, an independent glide can be applied to each channel. In the above explanation, as the buffer memory 29,
Although 160 words have been prepared, one transfer is performed in units of 20 words, so 20 words may be prepared. Regarding the partial number memory 36 and harmonic data memory 35 in FIG. 2, the former may have 13 bits per word, and the latter may have 6 bits per word. The maximum harmonic order is set to 64, but when increasing it, the number of words in the partial number memory
64 and further increase one word of harmonic data from 6 bits. Although the harmonic data may be transferred directly from the CPU 3, the amount of data to be transferred can be smaller in the embodiment shown in FIG. Moreover, in the embodiment of the present invention,
By omitting some of the many harmonic orders, it is possible to generate a jumping number J that is a toothless frequency control value. In addition, the partial number memory 36
Although it was explained that a different partial number is given to the 20 words of RAM, the same partial number can be stored in arbitrary multiple words and the non-harmonic memory 37
By writing slightly different INH data to , it is possible to generate two or more frequency components with very close frequencies. In other words, a chorus effect can be obtained. Among keyboard instruments, the pitch of the piano tends to be lower in the low range and higher in the high range compared to the range of the keyboard, and the frequency ratio of one octave is not exactly 1:2. This phenomenon can be called pitch extend. To do this, a ROM is provided to generate this shift, and this ROM is accessed by NOD(n) data to output the amount of shift corresponding to the note octave, and this amount is used as the difference address.
It may be added by ALU26. Further, the above deviation can also be included in the data written to the non-harmonic memory 37. It goes without saying that in order to generate a musical tone that does not have non-harmonic properties, it is sufficient to write a zero value as the INH data. In the above explanation, part of the data is displayed in binary coded ternary notation. Alternatively, it is also possible to display binary coded base, binary coded hexadecimal, etc. Alternatively, you can obtain octave data by displaying and calculating data in complete binary representation, and then converting it into binary coded ternary notation for higher-order digits, including the note data part. good. For this purpose, a binary-ternary conversion ROM may be provided. In the embodiment shown in FIG. 2, there is only one register for NOD(n). These registers and
If the number of RAMs is provided for 8 channels, the calculation procedure can be reduced to only group A. As described above, there is a relationship between the configuration and the calculation procedure, and there are various types other than those in this embodiment, but a description thereof will be omitted. In the above description, the procedure is described as a procedure for calculating the jump number J for sine wave synthesis, but it can also be used for frequency control of a waveform generator that reads out waveforms other than sine waves. For example, when generating only one J for one waveform instead of 20 harmonic components, an optimal configuration can be achieved using the same concept as above. <Portamento Effect> In the embodiment shown in FIG. 2, the number of jumps J can be gradually changed in response to the portamento effect. In the embodiment shown in FIG. 2, portamento is applied only to one channel, that is, CHS1. First of all, as mentioned earlier, in portamento mode,
This note octave data is NOD(n)33
, the previous note octave data is NOD (n-
1) Stored in 34. At the same time, portamento speed and key press interval NOD (n) - NOD (n - 1)
Data representing the increment Δ corresponding to is stored in the PRT32. Here, the increment Δ is a value that is proportional to the portamento speed setting value and also proportional to the key depression interval. Making it proportional to the key press interval, regardless of its size,
This is to enable the transition time to be the same when the pitch gradually changes from the key NOD(n-1) to the key NOD(n). The increment Δ is read by the CPU 3 from the setting states of the keyboard 1, tablet 2, etc. and stored in the PRT 32 via the data bus DB. This data is stored in the portamento converter either as is or after some transformation. Instruction group C in Table 1 determines whether portamento is increased or decreased. Instruction O adds an increment Δ to the previous NOD(n-1). Instruction 1 determines whether the result has reached or exactly matched the target value NOD(n).
Compare and judge whether you have surpassed it. CP means compare. As a result of this comparison, ALU 26 sets its internal flag FLG. The flags FLG of ALU26 include zero flag Z and sign flag S.
will be established. These flags are attached to a normal adder/subtractor, and the zero flag Z is a flip-flop that becomes "1" when all bits of the operation result are "0" and becomes "0" otherwise.The sign flag S is a flip-flop. , is composed of a flip-flop which becomes "1" when the most significant bit of the operation result is "1" and becomes "0" otherwise. The comparison result of instruction 1,
With △S representing the sign of the increment △, instructions 2 and 3 are
One of the two is executed. Instruction 2 adds △ to the current note octave data NOD(n-1) and adds it to new note octave data NOD(n-1).
1). Command 3 is the final goal
Store NOD(n) as a new NOD(n-1). With the above instruction group C, in the portamento effect, by adding the increment △, it is determined whether the pitch has not reached the target note octave data NOD(n), has just reached it, or has exceeded the target value. Then, based on the results, execute command group B that increases the frequency on the cent scale of the fundamental wave or harmonic by an increment of △, or set it to the target value.
The user is asked to select whether to execute instruction group A that performs an operation at the arrival point based on NOD(n). FIG. 12 shows which of the instructions 0 to 11 will be executed depending on the combination of three flags ΔS, Z, and S. command 0
and 1 are executed every time. Depending on the flags Z, S and △S, which are the operation results of instruction 1, there are cases in which instruction 3 and instruction group A (instructions 4 to 7) are executed, and instruction 2 and instruction group B (instructions 8 to 11). It is classified into cases in which it is executed. The former case is a case where the target value NOD(n) is exactly reached or exceeded by accumulating the increments Δ. The latter is a case where the target value NOD(n) is not yet reached even after accumulating the increments Δ. FIG. 13 is a timing chart in portamento mode. In the processing time slot PTS in which the operation is performed, instruction group C is executed in PTS32, and instruction groups A and B are executed in PTS1-20. An interrupt pulse is generated at the end of PTS20 or the beginning of PTS21 and is sent to CPU3 in Figure 1.
Request new data. At this time, the CHS code {P ₁₃ , P ₁₂ , P ₁₁ } is output to the data bus DB as an interrupt vector, and CPU3
You can also find out what the next CHS is. If the key has been changed and it is time to move to a new note octave, CPU3 will change the new NOD(n) and the previous NOD.
(n-1), PNO, INH group data and status flag data are transferred. The status data includes the KON flag,
Set KON flag FF to “1”. In portamento mode, calculations can be performed regardless of this KON flag. First, the CHS immediately before CHS1
The PTS 32 of No. 8 executes instructions 0 to 3 of the instruction group C. However, execution of one of instructions 2 and 3 is ignored due to flags ΔS, Z, and S in FIG. Thereafter, instruction group A or B is executed in PTS1 to PTS20 of CHS1 according to the status of the flags. When reading instruction group C, PTS is 32, that is, processing time slot code {P ₁₀ to P ₆ } is {111111}.
At the timing when the address code indicating instructions 0 to 3 is
What is necessary is to read instructions 0 to 3 in addition to the ROM. In order to ignore one of instructions 2 and 3, the read instruction output may be gated according to the codes of flags ΔS, Z, and S. Regarding the selection of instruction groups A and B, the 2 bits of the lower address code for reading instruction groups A and B are selected by {P ₅ , P ₄ } at the timing when the processing time slot codes {P ₁₀ to P ₆ } indicate 0 to 19. cause it to occur,
By specifying the upper 2 bits of the address code that distinguishes instruction groups A and B by a combination of flags △S, Z, and S, and adding a 4-bit address, instructions 4 to 7 and 8 to 11 in the instruction ROM are specified. What is necessary is to read out selectively. FIG. 14 shows an example of an adder in the ALU 26 that performs operations on data having the data structure shown in FIG. Since N ₁ and N ₀ are binary coded ternary numbers, the carry Cs from the lower S ₅ and the N ₁ on the A bus,
With N ₀ and N ₁ , N ₀ on the B bus as inputs, the outputs N ₁ , N ₀ on the C bus and carry C _N to the higher order are determined as shown in the truth table of FIG. 14. B is an example of hardware. 80 is S ₅ on A bus and B bus
A binary adder that takes 6 bits of _S0 as input, 82 is A
A binary adder 81 which receives O ₅ to _{O 0} , N ₃ , and N ₂ on the bus and B bus as input is a read-only memory (ROM) having a truth table pattern. C _s is a carry of the binary adder 80, and C _N is a carry output from the ROM 81. Subtractors and comparators can also be constructed using a similar idea. The vibrato data generator 42 in FIG. 2 may be a digital sine wave generator or the like. For example, if you have memorized the waveform of a vibrato signal,
The ROM may be read from the ROM and written to the registers at the timing when VIB(n) and VIB(n-1) are updated. The octave shifter 30 has a buffer memory 29
By adding multiple sets of codes obtained by shifting the output of 1 bit to the required bit to the respective gates, one set of these gates is converted to {O ₄ , O ₃ ,
The selection may be made using the code O ₂ , O ₁ , O ₀ }. In this example, the octave code has 5 bits, so 2 ⁵ = 32 different octaves can be taken, but the frequency range that humans can hear is from 20KHz to
As 20Hz, it is 10 ³ times 10 octaves, so
There are about 10 possibilities for bit shift. In this case, the MSB O ₄ may be omitted. In Figure 4, the data are 15 from O ₄ to S ₀ .
I thought it would be possible to handle bits. It goes without saying that when the data length is 15 bits or less as shown in FIGS. 4B to 4E, the extra bits above and below it may be arranged with "0"s. For negative numbers, 2
The difference depends on whether the display is a complement of 1 or a complement of 1, but in the latter case, "1" is output to the topmost position and "0" is output to the others. In the former case, all upper bits may be outputted as "1". In the case of one's complement, the sign bit V ₆ may be used as the most significant in the case of FIG. 4E. As mentioned above, in the embodiment shown in FIG.
The jump number J is calculated by calculating each data in the format explained with the drawings in a step-by-step manner. Portamento mode (13th
To switch between the normal mode (Fig. 11) and the normal mode (Fig. 11), enter the status FF in Fig. 2.
Prepare the NORMAL/PORTAMETO mode bit, and send "1" to this bit from the CPU 3 to set it to normal mode, and send "0" to this bit to set it to portamento mode, and change the instruction reading according to the mode bit. . In addition,
In normal mode, zero is written to PRT32 (Figure 2). Make sure that △ becomes zero. FIG. 15 is another example of index conversion. 3
8 stores J _i,p in EXP38, which is the same as in FIG.
39-1 is a differential ROM having addresses for 7 bits {N ₃ to S ₃ }, and stores differential values (J _i+1,0 −J _i+0 ) of 96 index sample values. The output is 5 bits. 39-2 This is a simplified multiplication ROM for outputting an interpolated value of equally divided values according to the three bits {S ₂ , S ₁ , S ₀ }. That is,
(J _i-1,0 −J _i,0 )×j/8 is stored. This will increase the quantization error a little, but the memory size will change from 768 x 5 = 3840 bits to 96 x 5 + 2 ^{5 + 3} x
5 = 1760 bits. In FIG. 3A above, one octave is assigned to 2048 to 4095. Therefore, it is 12 bits. In this case, the 12 equal temperament notes will be within an error of ±0.78125 cents. However, at low frequencies, the bits are shifted according to the octave code, and it is also conceivable that the bits are shifted to the lower side. At this time, the lower 12 bits are truncated, sometimes resulting in 8 to 9 bits. At this time, the above error increases. For 9 bits, 3
Since it was bit shifted, the error is 8 times ±
It becomes 6.25 cents. However, as is well known, in 9 bits, 239, 253, 268, 284, 301,
For the combination of 12 numbers 319, 338, 358, 379, 402, 451, the error from 12 equal temperament is less than ±1.2 cents. Therefore, instead of 2048, 253 x 8 = 2024 is set as C, and 23 x 16 = 3824.
If we let B be the most accurate 12-bit cent address, we can convert it to an interlaced number. To summarize the above, the present application provides pitch information corresponding to the pitch frequency of the fundamental tone of a musical tone to be generated consisting of a fundamental tone and harmonics, positive harmonic frequency information regarding the harmonic order of the musical tone, and frequency increase/decrease due to portamento. Incremental data is input, at least one octave interval is divided into a plurality of intervals having predetermined cent intervals at equal intervals, an address on the cent scale is assigned to the boundary of the interval, and the pitch information is expressed in the form of a cent address. The positive harmonic frequency information is output as a cent address in the form of a difference from the pitch information, the cent address of the pitch information and the difference cent address corresponding to the positive harmonic frequency information are added, and The above-mentioned incremental data is accumulated (subtracted) to obtain a sum cent address, and is added to a converter that converts the sum cent address to a frequency control value directly proportional to the frequency to obtain the frequency control value, storage means for storing pitch information, positive harmonic number information, and incremental data; and at least one for information transmission coupled to said storage means.
a main bus line, an addition/subtraction calculation unit connected to the bus line, a storage means for storing the calculation result, a device for outputting the calculation result to the bus line, and the converter; The address is divided into sections by expressing the middle digit of the cent address number within one octave section in a binary coded multiple of 3 format, and the means for generating data representing the increment of frequency deviation due to portamento is as follows: Incremental data is generated corresponding to the cent difference between the previous pitch frequency and the current pitch frequency and the portamento speed setting, and the means for storing the pitch information is configured to store the previous pitch information storage means and the current pitch frequency. By adding (subtracting) the above-mentioned increment data to the previous pitch information, a sum (difference) cent address is obtained, and this is added to a converter to convert it into a frequency control value. In the above cumulative addition (subtraction) operation, if the sum (difference) cent address exceeds the cent address of the current pitch information, the cent address of the current pitch information is used instead of the cumulative result. This is a frequency control device characterized by realizing linear portamento on the top. Therefore, it is possible to realize a linear portamento on the cent scale, and the frequency can be moved with almost the same pitch accuracy over the entire range.Moreover, even if the range changes, the portamento speed is the same as the address increment data △ is kept constant for . Furthermore, reliable portamento can be achieved without exceeding the cent address for the target note octave. The present invention also provides a first storage device that stores frequency control values corresponding to L cent addresses in one octave, and a first storage device that stores frequency control values corresponding to L cent addresses at intervals of M, and adjacent frequencies among the L cent addresses. Since the second storage device that stores the interpolated value based on the difference value of the control value is used, the cent address can be calculated with high accuracy without complicated logarithmic conversion calculation.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a digital electronic musical instrument to which the present invention is applied, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of an index conversion table, and Fig. 4 is a diagram of the above embodiment. FIG. 5 is a diagram showing an example of the data format used in the above embodiment, FIG. 6 is a diagram showing an operation timing chart of the above embodiment, and FIG. 7 is a diagram showing a counter for timing pulse generation. 8 is a diagram showing a timing pulse chart, FIG. 9 is a diagram showing a decoder, FIG. 10 is a diagram showing an example of an instruction code format, and FIG. 11 is a general timing chart in normal mode. , FIG. 12 is a diagram showing the instruction execution pattern in portamento mode, FIG. 13 is a diagram showing the global operation timing chart in portamento mode, FIG. 14 is a diagram explaining the operation of the adder, and FIG. 15 is an exponent diagram. It is a figure which shows an example of a conversion table. 1...Keyboard section, 2...Operation section, 3...CPU,
4...RAM, 5...ROM, 6...Envelope parameter ROM, 7...Frequency parameter
ROM, 8... Frequency control device, 9... Sine wave generator, 10... Envelope data generator, 11
... Multiplier, 12 ... Time slot control device,
13...Phase modulator, 14...Digital-to-analog converter, 21...Program counter, 22...
...Timing pulse generator, 23...Sequencer, 24...Instruction decoder, 25...Microcomputer interface circuit, 26...Arithmetic unit, 27...Working register, 28...RAM, 29...Buffer memory, 30... ...octave shifter, 31
... Portamento data converter, 32 ... Portamento register, 33, 34 ... Note octave register, 35 ... Harmonic data memory, 36 ... Partial number memory, 37 ... Non-harmonic memory, 38 ... Exponential conversion table, 39
...Difference index conversion table, 40...Gate, 4
1...Status flip-flop, 42...Vibrato data generator.

Claims (1)

[Claims] 1. Pitch information corresponding to the pitch frequency of the fundamental tone of a musical tone to be generated consisting of a fundamental tone and harmonics, positive harmonic frequency information regarding the harmonic order of the musical tone, and corresponding to frequency increase/decrease due to portamento. Inputs incremental data, divides one octave section into multiple sections with predetermined cent intervals at equal intervals, assigns addresses on the cent scale to the boundaries of the sections, and outputs the pitch information in the form of cent addresses. The positive harmonic frequency information is output as a cent address in the form of a difference from the cent address corresponding to the fundamental frequency of the harmonic, and the cent address of the pitch information and the difference cent address corresponding to the positive harmonic frequency information are output. and further accumulates (subtracts) the above incremental data to obtain a sum cent address, and in addition to a converter that converts the sum cent address into a frequency control value directly proportional to frequency, the device obtains a frequency control value. storage means for storing the pitch information, positive harmonic number information, and incremental data; at least one bus line for information transmission coupled to the storage means; and an addition/subtraction unit connected to the bus line. a computing unit for
It comprises a storage means for storing the calculation result, a device for outputting the calculation result to the bus line, and the converter, and the cent address is divided into sections by the middle digit of the number of cent addresses within one octave section. The means for converting the representation into a binary coded multiple of 3 format and generating data representing the increment of frequency deviation due to portamento is to set the cent difference between the previous pitch frequency and the current pitch frequency and the portamento speed. The means for storing the above-mentioned pitch information includes a previous pitch information storage means and a current pitch information storage means, and the means for accumulating (decreasing) the above-mentioned incremental data on the previous pitch information. )
By calculating, the sum (difference) cent address is obtained, and this is added to the converter to convert it into a frequency control value, and in the above cumulative (subtraction) calculation, the sum (difference) cent address is the current pitch information. A frequency control device characterized in that when the cent address is exceeded, the cent address of current pitch information is used instead of the cumulative result, thereby realizing linear portamento on the cent scale. 2. In the statement of claim 1, a predetermined one of the storage means for pitch information, the storage means for positive harmonic frequency information, the storage means for incremental data, and the storage means for calculation results corresponds to the number of sound generation channels. Each of the storage means is coupled to at least one bus line, an arithmetic unit is coupled to the bus line, and the arithmetic operations of each of the information are performed in the arithmetic unit in a time division multiplexed manner. Frequency control device. 3 In the description of claim 1, the middle digit of the cent address is binary coded decimal, binary coded 6
A frequency control device that displays in one of decimal, binary or ternary format, and uses the middle part of an arithmetic unit to perform calculations corresponding to the above display. 4 In the statement of claim 1, the cent address is expressed in binary, the arithmetic unit is a binary arithmetic unit, and the middle of the cent address of the calculation result is expressed in binary.
A converter that converts into one of decimal, binary coded hexadecimal, or binary coded ternary code is used to separate the code into an octave code and a note code, and the note code is added to the converter and its output is bit-shifted using the octave code. A frequency control device obtained by obtaining a frequency control device. 5. In the description of claim 1, the converter has at least a first memory that stores frequency control values corresponding to L cent addresses at M intervals among the number of cent addresses (L×M) within one octave interval. and a second storage device storing an interpolated value based on the difference value between adjacent frequency control values among the L frequency control values, and a cent address is added to the first and second storage devices to store both. A frequency control device that obtains a frequency control value corresponding to the above interval by adding the outputs of the device using an arithmetic unit. 6 In the description of claim 5, the second
The storage device includes a third storage device that stores the difference value between adjacent frequency control values, and a fourth storage device that receives the output of the third storage device and a predetermined lower bit of the cent address as input. Consisting of the above 4th
A frequency control device characterized in that the output of the storage device becomes the output of the second storage device.