JPH0332444U - - Google Patents

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Publication number
JPH0332444U
JPH0332444U JP8590290U JP8590290U JPH0332444U JP H0332444 U JPH0332444 U JP H0332444U JP 8590290 U JP8590290 U JP 8590290U JP 8590290 U JP8590290 U JP 8590290U JP H0332444 U JPH0332444 U JP H0332444U
Authority
JP
Japan
Prior art keywords
field effect
effect transistor
diode
shaped semiconductor
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8590290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8590290U priority Critical patent/JPH0332444U/ja
Publication of JPH0332444U publication Critical patent/JPH0332444U/ja
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図Aは従来例によるレベルシフト回路装置
の等価回路図、同図Bは同回路装置の平面パター
ンの説明図、第2図Aは第1図の回路装置におけ
るFET2の−特性を示すグラフ、同図Bは
同回路装置におけるダイオードの−特性を示
したグラフ、第3図Aは本考案の実施例の等価回
路図、同図Bはその平面パターンの説明図、第4
図は同実施例におけるダイオードの−特性を
示すグラフ、第5図は第3図Bの素子の断面構造
を示す説明図、第6図はレベルシフト回路装置の
使用例を示す回路図である。 図中、1……第2の電界効果トランジスタ、2
……第1の電界効果トランジスタ、3……ダイオ
ード、11,12,13……半導体層である。
1A is an equivalent circuit diagram of a conventional level shift circuit device, FIG. 1B is an explanatory diagram of a plane pattern of the circuit device, and FIG. 2A is a graph showing the characteristics of FET 2 in the circuit device of FIG. 1. , FIG. 3B is a graph showing the characteristics of the diode in the same circuit device, FIG. 3A is an equivalent circuit diagram of the embodiment of the present invention, FIG.
5 is an explanatory diagram showing the cross-sectional structure of the element in FIG. 3B, and FIG. 6 is a circuit diagram showing an example of use of the level shift circuit device. In the figure, 1... second field effect transistor, 2
. . . first field effect transistor, 3 . . . diode, 11, 12, 13 . . . semiconductor layer.

補正 平2.9.12 考案の名称を次のように補正する。 考案の名称 半導体装置の製造装置 実用新案登録請求の範囲を次のように補正する
Amendment 2.9.12 The name of the invention is amended as follows. Title of invention: Semiconductor device manufacturing device The scope of claims for utility model registration is amended as follows.

【実用新案登録請求の範囲】 基板上に設けられた第1の島状半導体に形成さ
れ、定電流源として働く第1の電界効果トランジ
スタと、 前記第1の島状半導体と分離して基板上に設け
られた第2の島状半導体に形成され、アノード電
極の両側に共通接続されたカソード電極を備える
プレーナ形ダイオードと、 前記第1及び2の島状半導体と分離して基板上
に設けられた第3の島状半導体に形成され、前記
第1の電界効果トランジスタ及びプレーナ形ダイ
オードを負荷抵抗としソースホロアとして働く第
2の電界効果トランジスタとを備え、 第2の電界効果トランジスタのゲートに加わる
入力電圧を該ダイオードの電圧降下分だけレベル
シフトして該ダイオードと第1の電界効果トラン
ジスタとの直列接続点から出力するレベルシフト
回路装置を形成するにおいて、 前記第1、第2及び第3の島状半導体は、基板
上に成長された1つエピタキシヤル半導体層を互
いに分離することで形成されることを特徴とする
半導体装置の製造装置。
[Claims for Utility Model Registration] A first field effect transistor formed on a first island-shaped semiconductor provided on a substrate and serving as a constant current source; a planar diode formed on a second island-shaped semiconductor provided on the substrate and having a cathode electrode commonly connected to both sides of an anode electrode; a second field effect transistor formed in a third island-shaped semiconductor with the first field effect transistor and a planar diode serving as a load resistance and serving as a source follower; In forming a level shift circuit device that level-shifts a voltage by a voltage drop of the diode and outputs it from a series connection point between the diode and the first field effect transistor, the first, second and third islands 1. An apparatus for manufacturing a semiconductor device, characterized in that a shaped semiconductor is formed by separating one epitaxial semiconductor layer grown on a substrate from each other.

Claims (1)

【実用新案登録請求の範囲】 基板上に設けられた第1の島状半導体に形成さ
れ、定電流源として働く第1の電界効果トランジ
スタと、 前記第1の島状半導体と分離して基板上に設け
られた第2の島状半導体に形成され、アノード電
極の両側に共通接続されたカソード電極を備える
プレーナ形ダイオードと、 前記第1及び2の島状半導体と分離して基板上
に設けられた第3の島状半導体に形成され、前記
第1の電界効果トランジスタ及びプレーナ形ダイ
オードを負荷抵抗としソースホロアとして働く第
2の電界効果トランジスタとを備え、 第2の電界効果トランジスタのゲートに加わる
入力電圧を該ダイオードの電圧降下分だけレベル
シフトして該ダイオードと第1の電界効果トラン
ジスタとの直列接続点から出力するレベルシフト
回路装置を形成するにおいて、 前記第1、第2及び第3の島状半導体は、基板
上に成長された1つエピタキシヤル半導体層を互
いに分離することで形成されることを特徴とする
半導体装置の製造方法。
[Claims for Utility Model Registration] A first field effect transistor formed on a first island-shaped semiconductor provided on a substrate and serving as a constant current source; a planar diode formed on a second island-shaped semiconductor provided on the substrate and having a cathode electrode commonly connected to both sides of an anode electrode; a second field effect transistor formed in a third island-shaped semiconductor with the first field effect transistor and a planar diode serving as a load resistance and serving as a source follower; In forming a level shift circuit device that level-shifts a voltage by a voltage drop of the diode and outputs it from a series connection point between the diode and the first field effect transistor, the first, second and third islands 1. A method of manufacturing a semiconductor device, characterized in that the shaped semiconductor is formed by separating one epitaxial semiconductor layer grown on a substrate from each other.
JP8590290U 1990-08-15 1990-08-15 Pending JPH0332444U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8590290U JPH0332444U (en) 1990-08-15 1990-08-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8590290U JPH0332444U (en) 1990-08-15 1990-08-15

Publications (1)

Publication Number Publication Date
JPH0332444U true JPH0332444U (en) 1991-03-29

Family

ID=31635265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8590290U Pending JPH0332444U (en) 1990-08-15 1990-08-15

Country Status (1)

Country Link
JP (1) JPH0332444U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011040888A (en) * 2009-08-07 2011-02-24 Dainippon Printing Co Ltd Semiconductor electronic circuit, transmission circuit, and flip-flop circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53118374A (en) * 1977-03-25 1978-10-16 Nec Corp Integrated diode device
JPS5586222A (en) * 1978-12-23 1980-06-28 Fujitsu Ltd Level shift circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53118374A (en) * 1977-03-25 1978-10-16 Nec Corp Integrated diode device
JPS5586222A (en) * 1978-12-23 1980-06-28 Fujitsu Ltd Level shift circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011040888A (en) * 2009-08-07 2011-02-24 Dainippon Printing Co Ltd Semiconductor electronic circuit, transmission circuit, and flip-flop circuit

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