JPH033245A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To more enlarge the part where a gate electrode and a drain diffusion layer overlap each other so as to obtain a semiconductor device which can suppress electric field concentration by providing a mask at the gate electrode formation part of a polycrystalline silicon for gate electrode formation, and successively performing thermal oxidation. CONSTITUTION:A semiconductor for gate electrode, for example, polycrystalline silicon 13a is stacked on a gate oxide film 12, and thereon a mask 14 of silicon nitride film to become a mask in thermal oxidation process is formed. Next, when thermal oxidation process is done, the polysilicon excluding the mask 14 becomes an oxide layer 13b. Next, when the Si3N4 film 14 is removed and the SiO2 layer 13b is removed by dry etching, a gate electrode 13 in the shape of downward slowly tapering can be obtained. Successively, ions of n-type impurities are implanted so as to form an n-type region 15. The profiles of these source and drain diffusion layers 15 reflect the shape of the gate electrode 13, and take downward slowly inclined shapes, whereby electric field concentration disappears, and creation of hot carriers is prevented.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, especially a method for manufacturing a semiconductor device, especially an LDD (Light
Regarding a method for manufacturing a semiconductor device (MOS FET) with a lightly doped drain (lyDoped drain) structure, in the LDD structure of a MOS FET, the overlapping portion of the gate electrode and the drain diffusion layer can be made larger, and therefore, The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can further suppress electric field concentration, by forming a gate oxide film on a semiconductor substrate, and forming a semiconductor layer and an oxide-resistant material on top of the gate oxide film to form a gate electrode. A step of forming a mask by patterning the oxide-resistant member in accordance with the gate electrode to be formed, and forming an oxide layer by oxidizing the semiconductor in a portion except under the mask by thermal oxidation. and a step of removing the mask and the oxide layer and introducing impurities using the remaining semiconductor gate electrode as a mask to form source and drain diffusion layers. Contains and composes.

(Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, particularly to a method for manufacturing a semiconductor device.
A semiconductor device with a lightly doped drain structure (MOS FET)
).

[Conventional technology]

In recent years, with the miniaturization of semiconductor devices, the generation of hot carriers due to electric field concentration near the edges of gate electrodes has increased significantly, and as a result, deterioration of device characteristics has become a problem.

As one means for solving this problem, an LDD structure has been proposed and studied. FIG. 3 is a cross-sectional view of the conventional example. Referring to the conventional MO3FET shown in the same figure, hot carriers are generated in the lower part of the edge of the gate electrode, which is shown with an x symbol in the same figure, and the effective In addition to the short channel effect, which shortens the channel length, it is known that hot carriers are injected into the gate oxide film.

In FIG. 3, 21 is a silicon substrate, 22 is a gate oxide film, 23 is a gate electrode with a length of g, 24 is a Sin layer, 25 is an n-61 region, and 26 is an n'' region Drain diffusion layer ), and the illustrated structure in which the n' region 26 is deeply formed below the edge of the gate electrode by penetrating the shallowly formed n- region is called an LDD structure.

Hot carriers generate new electron/hole pairs in the silicon substrate, and although most of the newly generated electrons are sucked into the drain by the drain electric field, some are avalanche hot carriers. - They become electrons and are injected into the gate oxide film 22. The holes flow through the silicon substrate 21 and become a substrate current, but some of them are also injected into the gate oxide film 22. Electrons or holes injected into the gate oxide film are trapped in the gate oxide film or generate a level at the interface between the silicon of the substrate and the gate oxide film, thereby increasing the threshold voltage (shift M). It acts by changing the value in the positive direction and decreasing the mutual conductance.
In order to solve this problem, LDD structures are attracting attention.

(Problem to be Solved by the Invention) However, in the LDD structure, in the case of an n-channel MOS transistor, it is necessary to fabricate a low concentration impurity region (n- region) and a high 4 degree impurity region (n'' region). This leads to two ion implantation steps.Furthermore, since the overlapping portion between the gate electrode and the drain diffusion layer, indicated by Δl in FIG. 3, is small, electric field concentration cannot be sufficiently alleviated.

Further, as shown in FIG. 4(a), the polycrystalline silicon layer is etched using the resist 36 as a mask to form a gate electrode 33 having a trapezoidal cross section. Even if the drain 35 is formed, there will be a portion where the gate electrode and the drain overlap, but the gate electrode 33 is formed by etching using the resist 36 as a mask.
It is not possible to form the slope of the side surface gently, and the overlapping part cannot be made large.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which the overlapping portion of the gate electrode and the drain diffusion layer can be increased in the LDD structure of a MOS FET, thereby further suppressing electric field concentration. purpose.

[Means to solve the problem]

The above problem is to form a gate oxide film on a semiconductor substrate, to grow a semiconductor layer and an oxide-resistant material in order to form a gate electrode on the gate oxide film, and to make the oxide-resistant material correspond to the gate electrode to be formed. a step of forming an oxide layer by oxidizing the semiconductor except under the mask by thermal oxidation; and a step of removing the mask and the oxide layer and removing the remaining semiconductor. The problem is solved by a method for manufacturing a semiconductor device, which includes a step of introducing impurities using the gate electrode as a mask to form source and drain diffusion layers.

[Function] The shapes of the source and drain of the LDD structure MOSFET obtained by the present invention are shown in FIG. In the present invention, a mask (SizN4 film) is provided on the gate electrode formation portion of polycrystalline silicon (polysilicon) for forming the gate electrode, and then thermal oxidation is performed. The shape of the gate electrode formed by this thermal oxidation (FIG. 2) reflects the shape of the bird's beak created during thermal oxidation, and has a gently sloped shape as shown in the figure. Next, the mask and oxide film are removed and impurity implantation is performed to form the source and drain diffusion layers, resulting in an impurity distribution that reflects the shape of the gate electrode (
A source and a drain with a profile (profile) are formed as shown in FIG.

As a result, it is possible to increase the overlap between the gate electrode and the drain diffusion layer, which is a problem in the LDD structure, and it is possible to significantly reduce electric field concentration.
Since the shape of the drain diffusion layer is gently tapered downward, it is possible to prevent the short channel effect, which is a problem in fine transistors.

An embodiment of the invention is shown in cross-section in FIGS. 1(a)-(d). First, referring to FIG. 2A, a semiconductor substrate (silicon substrate) 11 is prepared, and then a gate oxide film 12 is formed to a thickness of 500 nm on the surface of the silicon substrate 11 by thermal oxidation. A semiconductor for the gate electrode, such as polycrystalline silicon (polysilicon) 13a, is deposited on the film 12 to a thickness of 4000 nm by, for example, chemical vapor deposition (CVD), and then thermal oxidation is performed on the film 12 by, for example, CVD. In the process, a silicon nitride film (Si3N4 film) that serves as an oxide resistant material (mask) is grown to a thickness of 500 to 1,000 layers, and patterned to correspond to the length (G) of the gate electrode to be formed as a mask. form 14.

Next, referring to FIG. 1(C), when a thermal oxidation process is performed in a dry or wet atmosphere, the polysilicon under the mask 14 is not oxidized, but the polysilicon that is not masked is covered with an oxide layer (SiOx layer) 13b. becomes. In this thermal oxidation, the SiO□ layer 13b forms the known bird's beak, so that the unoxidized polysilicon
It has a tapered shape that gently expands downward. This polysilicon becomes the gate electrode 13.

Next, the 5iJ4 film 14 is removed using phosphoric acid boiling, followed by dry etching using, for example, CF, +O□.
When the h layer 13b is removed, a gate electrode 13 having a shape that is gently tapered downward as shown in FIG. 1(d) is obtained. In this step, the SiO□ layer 13b may be removed first, and then the 5iJn 11114 may be removed using phosphoric acid boiling.

Next, an n-type impurity, such as phosphorus (P), is added at an acceleration voltage of 40 KeV and a dose of (2 to 4) XIOISc.
The n-type region (source and drain diffusion layer) 15 was formed by ion implantation at a dose of m-''. The shape is inclined to eliminate electric field concentration and the generation of hot carriers.

In the conventional example, the length Δ2 of the overlapping portion of the n- region 25 and the gate electrode in FIG. 3 and n? in FIG. , the length Δ2' of the overlapping portion of the I region 35 and the gate electrode was about 20007, but in the example of the present invention shown in FIG.
There were approximately 3,000 people.

[Effects of the Invention] As described above, according to the present invention, when forming a fine MO3FET, since the shape of the source and drain diffusion layers extends gently, electric field concentration and generation of hot carriers can be suppressed, and The effect of suppressing the shift of the threshold voltage in the positive direction can also be obtained.

[Brief explanation of the drawing]

Figures 1 (al to d) are cross-sectional views of an embodiment of the present invention, Figure 2 is a cross-sectional view for explaining the present invention, and Figures 3 and 4 are cross-sectional views for explaining a conventional example. In the figure, 11 is a silicon substrate, 12 is a gate oxide film, 13 is a gate electrode (polysilicon), 13a is polysilicon, 3b is a Sin layer, 14 is a mask (Si3N4 film), and 15 is an n region (source, drain). diffusion layer).

Claims (1)

[Claims] A gate oxide film (12) is formed on a semiconductor substrate (11), and a semiconductor layer (13a) for forming a gate electrode is formed on the gate oxide film (12).
) and an oxide-resistant member in order, and patterning the oxide-resistant member to form a mask (14) corresponding to the gate electrode (13) to be formed; A step of oxidizing the semiconductor in a portion other than the above to form an oxide layer (13b), and removing the mask (14) and the oxide layer (13b), and using the remaining semiconductor gate electrode (13) as a mask. A method for manufacturing a semiconductor device, comprising the step of introducing impurities to form source and drain diffusion layers (15).