JPH0332892U - - Google Patents

Info

Publication number
JPH0332892U
JPH0332892U JP9110789U JP9110789U JPH0332892U JP H0332892 U JPH0332892 U JP H0332892U JP 9110789 U JP9110789 U JP 9110789U JP 9110789 U JP9110789 U JP 9110789U JP H0332892 U JPH0332892 U JP H0332892U
Authority
JP
Japan
Prior art keywords
circuit
delay element
expander
mid
compressor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9110789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9110789U priority Critical patent/JPH0332892U/ja
Publication of JPH0332892U publication Critical patent/JPH0332892U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示すブロツク図、
第2図は従来例を示すブロツク図である。 2……ローパスフイルタ、3……コンプレツサ
、4……BBD、6……エキスパンダ、11……
プリエンフアシス回路、12……デイエンフアシ
ス回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing a conventional example. 2...Low pass filter, 3...Compressor, 4...BBD, 6...Expander, 11...
Pre-emphasis circuit, 12... de-emphasis circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アナログ遅延素子と、該アナログ遅延素子の前
段に設けられたコンプレツサと、上記アナログ遅
延素子の後段に設けられたエキスパンダとを有す
る遅延回路において、上記コンプレツサの前段に
中高域増強回路を設け、上記エキスパンダの後段
に中高域減衰回路を設けたことを特徴とする遅延
回路。
In a delay circuit having an analog delay element, a compressor provided before the analog delay element, and an expander provided after the analog delay element, a mid-high range enhancement circuit is provided before the compressor; A delay circuit characterized in that a mid-high frequency attenuation circuit is provided after the expander.
JP9110789U 1989-08-02 1989-08-02 Pending JPH0332892U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9110789U JPH0332892U (en) 1989-08-02 1989-08-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9110789U JPH0332892U (en) 1989-08-02 1989-08-02

Publications (1)

Publication Number Publication Date
JPH0332892U true JPH0332892U (en) 1991-03-29

Family

ID=31640607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9110789U Pending JPH0332892U (en) 1989-08-02 1989-08-02

Country Status (1)

Country Link
JP (1) JPH0332892U (en)

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