JPH033349A - Automatic wiring-method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To select in a short time the pattern of a wiring which has been already formed and is to be eliminated, and easily perform re-wiring after the elimination, by judging whether the conformity with the design rule does not exist after all of the wirings between two points are completely performed, and executing the change of wiring with regard to the part where the design rule breach exists. CONSTITUTION:In a layout designing method of semiconductor integrated circuit, a cell realizing a previously designed unit function is arranged and wired on a semiconductor substrate, thereby realizing a desired circuit. In the case where the conformity with the design rule of wiring patterns of different potential does not exist in the result that wiring processing has been performed to satisfy connection requirements by a previously determined wiring condition, a specified region R is set in the vicinity of X mark showing the breach position, and all of the wiring patterns passing the region R are eliminated. Then wiring is newly performed by changing the wiring condition for the eliminated wiring pattern, thereby eliminating the design rule unconformity. Hence the selection of wiring to be eliminated which requires a lot of time in the conventional method can be performed in a short time, and re-wiring after elimination is facilitated.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to layout design of a semiconductor integrated circuit,
In particular, the present invention relates to an automatic wiring method for semiconductor integrated circuits that automatically performs wiring processing.

(Prior Art) In the automatic wiring method used in the layout design of semiconductor integrated circuits, in many cases, as shown in FIG.
Wiring between points is performed sequentially to form the entire wiring pattern. In Figure 2, al and 82, bl and b2, hl
and h2 indicate two points to be connected, and the solid line and broken line connecting these are the wiring pattern. The two points to be connected and the wiring patterns connecting them must each have the same potential, and different wiring patterns must not touch or cross, and must be insulated from each other. In the example of Figure 2,
The solid lines are horizontal wiring patterns, and the broken lines are vertical wiring patterns, and the vertical and horizontal patterns have different wiring layers. However, as shown in Fig. 3, when the wiring between x1 and x2 is performed next, the pattern of the existing wiring (g
2), a design rule violation such as contact or intersection occurs at the position indicated by the X mark, for example.

According to the conventional method, processing as shown in FIG. 6 is performed in order to avoid violation of design rules when performing automatic wiring. First, after inputting wiring data, before wiring between two points of interest, the possibility of wiring is checked. As a result, wiring is performed if possible, and if it is not possible, an existing wiring pattern that allows wiring is selected and deleted, and wiring between the two points of interest is performed first.

After that, wiring between two points from which the existing wiring pattern has been deleted is performed. In this case, the existing wiring pattern to be deleted is determined and selected based on the wiring situation at that time (for example, as disclosed in Japanese Patent Application Laid-open No. 72384/1984).

However, this type of method has the following problems. That is, at the stage of checking the possibility of wiring, the violation position cannot be specified because no wiring is performed between the two points of interest, and it takes time to select the wiring pattern to be deleted. In addition, 2
There has been a problem in that the rewiring pattern between points is likely to cause a new design rule violation with other existing wiring patterns.

(Problem to be Solved by the Invention) As described above, in the conventional automatic wiring method, in order to avoid violation of design rules due to contact or intersection of wiring patterns of different potentials, existing wiring patterns are deleted and wiring is performed. , it takes time to check the possibility of wiring and select the existing wiring pattern to be deleted, and furthermore, there is a risk that other violations of design rules will occur due to rewiring between two points after deleting the wiring pattern. There was a problem that there was.

The present invention has been made in consideration of the above circumstances, and its purpose is to be able to select existing wiring patterns to be deleted in a short time, and to facilitate rewiring after deletion. An object of the present invention is to provide an automatic wiring method for semiconductor integrated circuits that can contribute to improving the efficiency of automatic wiring processing.

[Structure of the Invention (Means for Solving the Problems) The gist of the present invention is not to check the possibilities of wiring before wiring between two points, but to virtually connect all the wiring between two points. determine whether a design rule violation exists after performing the
The purpose is to change the wiring in areas where design rule violations exist.

That is, the present invention provides an automatic wiring method for semiconductor integrated circuit layout design in which a desired circuit is realized by arranging and wiring cells that realize pre-designed unit functions on a semiconductor substrate. As a result of wiring processing to meet connection requirements based on wiring conditions, if there is a design rule violation such as contact or intersection of wiring patterns with different potentials, a designated area is placed near the violation location to remove the design rule violation. In this method, after deleting all wiring patterns passing through the area, new wiring is performed by changing the wiring conditions such as the wiring order for the deleted wiring pattern.

(Operation) According to the present invention, after a design rule violation occurs, an arbitrary area is set in the vicinity of the violation position, and a wiring pattern that passes within the set area is set as a wiring pattern to be deleted. The selection of wiring patterns to be deleted, which takes time in conventional methods, can be performed in a short time. Furthermore, by changing the wiring conditions for rewiring performed after deletion, the influence on other existing wiring patterns can be minimized, and rewiring after deletion becomes easy.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a flowchart for explaining an automatic wiring method for semiconductor integrated circuits according to an embodiment of the present invention.

Figure 2 shows wiring al-a2, bl-b2, etc. on the wiring surface.
It is a diagram showing a state where hl-h2 has been applied. The wiring order is al-a2. bl-b2. -, hl-h2.

In this example, the solid line indicates the horizontal wiring pattern,
The broken lines indicate the vertical wiring pattern, and the vertical and horizontal wiring layers are different. FIG. 3 is a diagram showing a state in which a wiring xIX2 is added to the wiring state shown in FIG. 2. In Figure 3, the wiring gl-g2 is connected at the position indicated by the X mark.
The horizontal wiring patterns of xi-x2 and xi-x2 are in contact with each other, resulting in a violation of the wiring design rules.

The process for removing the wiring design rule violation indicated by the X mark in FIG. 3 will be described with reference to the flowchart in FIG. 1.

First, in the process of inputting wiring data (step Sl), wiring data including the wiring results shown in FIG. 3 is input. Next, in a process of checking whether a violation of wiring design rules exists (step S2), the wiring data is checked to see if a violation of wiring design rules exists in the input wiring data. If there is no violation of the wiring design rules, the process ends, and if there is a violation of the wiring design rules, the process proceeds to the next process (step S3).

Next, in the process of setting a wiring pattern deletion area (step S3), an area including the wiring design rule violation position indicated by an X in FIG. 4 is set. In this example,
The above area is set as a circle (R) centered on the wiring design rule violation position.

Next, in the process of finding a wiring pattern to be deleted (step S4), a wiring pattern to be deleted is found among the wiring patterns shown in FIG. In FIG. 4, the wiring cl-c2. di-d2. gl-g2.
Since the wiring pattern xi-x2 passes through the deletion area, these are the wiring patterns to be deleted. Next, in the process of deleting the wiring pattern (step S5), the wiring c 1 c 2 * d shown in FIG.
1-d 2 + g 1-g 2 + X 1-x2
The wiring pattern is deleted.

Next, in a process for changing wiring conditions (step S6), wiring conditions are changed.

In this embodiment, the case where the order of wiring is reversed is explained as an example of changing the wiring conditions. The wiring order in this case is xi-x2. gl-g2゜di-d2. cl-c2
becomes. Other methods for changing wiring conditions include the maze method,
Line search method.

There may be cases in which the wiring method such as the channel wiring method is changed, or wiring rules such as the wiring width and the wiring pitch are changed.

Next, the process of newly wiring the deleted wiring pattern (
In step S7), wiring is performed under the wiring conditions set in step S6.

Figure 5 shows the wiring results. As shown in the figure, violations of wiring design rules have been removed. Next, in the process of outputting the wiring results (step S8), the results of the wiring performed in step S7 are output, and the process returns to step 1.

Thus, according to the method of this embodiment, after a design rule violation occurs, an arbitrary region R is set in the vicinity of the violation location, and the wiring pattern passing through the set region R is set as the wiring pattern to be deleted. As a result, it is possible to select a wiring pattern to be deleted in a short time, which was time-consuming in the conventional method. Moreover, by changing the wiring conditions (for example, wiring order) for rewiring performed after deletion, the influence on other existing wiring patterns can be minimized, and rewiring after deletion becomes easy. In other words, you can efficiently identify locations that violate wiring design rules that occur during automatic wiring processing.
Moreover, it can be effectively removed, and is extremely effective in designing the layout of semiconductor integrated circuits.

Note that the present invention is not limited to the embodiments described above. For example, instead of deleting all wiring patterns that pass through a set area, you can create a parameter parameter for deleting wiring patterns based on the distance from the wiring design rule violation position, the wiring pattern length, the number of bends in the wiring pattern, etc. may be set, and wiring patterns passing through the area set probabilistically may be deleted.

In addition, if the violation of wiring design rules cannot be removed by removing and rewiring the wiring pattern by setting the area, change the shape of the area by gradually enlarging the area near the violation location or changing the shape of the area. is possible. Further, the present invention can be applied during the wiring process or after the -through wiring process is completed.

In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to select a wiring pattern to be deleted in a short time, which was time-consuming in the conventional method, and to facilitate rewiring after deletion. It becomes possible to do this. Therefore, it becomes possible to efficiently and effectively eliminate violations of wiring design rules that occur during wiring processing.

[Brief explanation of the drawing]

FIG. 1 is a flowchart for explaining an automatic wiring method for a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the progress of wiring, and FIG. 3 is a diagram showing locations of violations in wiring design. , FIG. 4 is a diagram showing the area where the wiring pattern is deleted, FIG. 5 is a diagram showing the state in which the violation of the wiring film:1 rule has been removed, and FIG. 6 is a flowchart for explaining the conventional automatic wiring method. It is. 81 to S8...Various processing X...Position of wiring design rule violation R...Wiring pattern deletion area

Claims (1)

[Claims] A semiconductor integrated circuit layout design method for realizing a desired circuit by arranging and wiring cells that realize pre-designed unit functions on a semiconductor substrate, comprising predetermined wiring conditions. If, as a result of performing wiring processing to meet the connection requirements, there is a violation of the design rules for wiring patterns with different potentials, a predetermined area is set near the violation location, and all wiring patterns that pass through the area are An automatic wiring method for semiconductor integrated circuits, characterized in that a design rule violation is removed by deleting the pattern of the deleted wiring and then changing wiring conditions and performing new wiring.