JPH0333961A - Receiver for data processor - Google Patents

Abstract

PURPOSE:To accelerate a processing by receiving transmission data sent from a transmitter via an interface signal line, and deciding whether reception data is transfer data or control information. CONSTITUTION:When data processed at the processing circuit 110 of the transmitter 10 is sent from a transmission circuit 120, the reception circuit 210 of a receiver 20 receives the data via the interface signal line 30, and sends it to a deciding circuit 220. The circuit 220 decides a parameter signal 301 included in the data, and stores the transmission data 302 in a control information buffer 230 when it is the control information '1'. Also, when it is the transfer data '0', the data 302 is stored in a transfer data buffer 240, and the signal 301 in the transmission data received just before is decided again, and when a judged result shows the control information '1', '1' is set at a flag memory 250. When it shows the transfer data '0', '0' is set at the flag memory 250.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a data receiving device in data processing. The present invention relates to an inter-device interface that connects data processing devices and transfers control information and transfer data on a set of signal lines in a time-division manner, and particularly relates to a device for receiving data from a data processing device connected to this interface. .

〔overview〕

The present invention provides a method for determining whether the transferred data is transfer data or control information in a receiving device of a data processing device that transfers and processes control information and transfer data in a time-division manner on a set of interface signal lines. By determining and individually processing the received data in advance, it is possible to eliminate delays in waiting for processing due to the order of reading when using received data and increase processing speed.

[Conventional technology]

Conventionally, this type of data processing device has generally been configured with one receive buffer that receives data on the interface signal line, and the data received from the interface signal line is temporarily stored in the receive buffer and then used as needed. They were read and processed sequentially according to the

[Problem that the invention seeks to solve]

In this way, in conventional data processing devices, received data is sequentially read and processed, so it is necessary to decode control information and process transferred data in the order in which the buffers are read. Even if you try to process the other data, the processing of the other data is not completed, so
The data could not be read and had to wait, causing a reduction in processing speed.

The present invention solves such problems, and the present invention aims to solve such problems by providing control information,
It is an object of the present invention to provide a device that can individually prefetch and process transfer data without reducing processing speed.

[Means for solving problems]

The present invention provides a receiving circuit that receives data on an interface signal line, a receiving buffer that temporarily stores data received by this receiving circuit, a data processing circuit that processes data transferred from this receiving buffer, and this data processing circuit. In the receiving device of the data processing apparatus, the receiving buffer is divided into two parts: a transfer data buffer that stores transfer data and a control information buffer that stores control information. A determination circuit is provided that determines whether data received by the circuit is transfer data or control information based on an added parameter signal and stores it in each buffer according to the determination,
The present invention is characterized in that it includes a flag memory that holds a flag indicating whether or not corresponding control information has been received and stored immediately before the transfer data stored in the entry.

[Effect]

Transmission data sent from the transmitting device is received via an interface signal line, and it is determined whether the received data is transfer data or control information.

If the result of the judgment is transfer data, it is stored in the transfer data buffer, and each en) corresponding to each transfer data buffer is stored in the transfer data buffer.
A flag indicating whether or not control information was received and stored immediately before the data stored in the IJ is set in the flag memory.

By referring to the contents of this flag memory and independently and parallelly processing control information and transfer data, it is possible to speed up the processing.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the invention, and FIG. 2 is a diagram showing the format of data on an interface signal line in the embodiment of the invention.

In the embodiment of the present invention, a receiving device 20 is connected to a transmitting device 10 including a processing circuit 10 and a transmitting circuit 120 via an interface signal line 30, and the receiving device 20 receives data on the interface signal line 30. Receiving circuit 2
10, a reception buffer that temporarily stores data received by this reception circuit, a data processing circuit 280 that processes data transferred from this reception buffer, and a control circuit 270 that controls this data processing circuit 280. The buffer is a transfer data buffer 240 that stores transfer data.
and a control information buffer 230 that stores control information. A determination circuit 220 is provided to store the data in each buffer 230 and 240 according to the determination, and (b) a flag memory retains a flag indicating whether or not corresponding control information has been received and stored immediately before the transfer data stored in the IJ. 250.

The signal transmitted from the transmitter 10 includes a parameter signal 301 and transmission data 302, as shown in FIG.

In this embodiment, when the parameter signal is "1", it indicates that the transmission data is control information, and when it is "0", it indicates that the transmission data is transfer data. In addition, the transfer data buffer 240
, control buffer 230, and flag memory 250 are each composed of first-in/first-out stack memories.

Next, the operation of the embodiment of the present invention configured as described above will be explained. FIG. 3 is a flow chart showing the flow of operation of the determination circuit 220 according to the embodiment of the present invention, FIG. 4 is a flow chart showing the flow of operation of the data processing circuit 280 according to the embodiment of the present invention, and FIG. 3 is a flowchart showing the flow of operation of the control circuit 270. FIG.

When the data processed by the processing circuit 110 of the transmitting device 10 is sent out from the transmitting circuit 120, the receiving circuit 210 of the receiving device 20 receives the data via the interface signal line 30 and sends it to the determination circuit 220.

The determination circuit 220 determines the parameter signal 301 included in the data, and stores the transmission data 302 in the control information buffer 230 when the parameter signal 301 is “l” control information. Further, when the transmission data is "0", the transmission data 302 is stored in the transmission data buffer 240, and the parameter signal 301 of the transmission data received immediately before is determined again, and the determination result is control information of "1". At times, "1" is set in the flag memory 250. When the transfer data is "0", "0" is set in the flag memory 250.

The control circuit 270 determines whether the control information buffer 230 is empty, and if it is not empty, reads one word,
The read control information is decoded and control instruction information is generated according to the instructions. Next, it is determined whether there is a control instruction request from the data processing circuit 280, and if "yes", a control instruction is given to the data processing circuit 280, and if "absent", the control instruction request is awaited.

The data processing circuit 280 also includes the transfer data buffer 24
It is determined whether or not 0 is empty, and if it is not empty, 1 word is read from the flag memory 250, and the content of the read flag is determined.

As a result of this determination, if the flag is "1" indicating that control information has been received immediately before, a control instruction is requested from the control circuit 270, and when the control instruction is received, the data is processed according to the control instruction. Execute. If the flag is "0" indicating that no control signal has been received immediately before, one word is read from the transfer data buffer 240 and the read data is processed.

In processing the data received in this way, the contents of the flag memory 250 are used to control the control circuit 270 that processes control information, and the data processing circuit 28 that processes transfer data.
By synchronizing with 0 and operating each circuit independently, processing speed can be increased.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to configure a reception buffer that has no delay when using received data and can separately process control information and transfer data in advance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram showing the data format on the interface signal line in the embodiment of the present invention. FIG. 3 is a flowchart showing the operation flow of the determination circuit according to the embodiment of the present invention. FIG. 4 is a flowchart showing the operation flow of the control circuit according to the embodiment of the present invention. FIG. 5 is a flowchart showing the operation flow of the data processing circuit according to the embodiment of the present invention. 10... Transmitting device, 20... Receiving device, 30...
Interface signal line, 110...processing circuit, 120
...Transmission circuit, 210...Reception circuit, 220...
Judgment circuit, 230... Control information buffer, 240...
・Transfer data buffer, 250...Flag memo IJ,
270... Control circuit, 280... Data processing circuit.

Claims (1)

[Claims] 1. A receiving circuit that receives data on an interface signal line, a receiving buffer that temporarily stores data received by this receiving circuit, and a data processing circuit that processes data transferred from this receiving buffer; In the receiving device of the data processing apparatus including a control circuit that controls the data processing circuit, the receiving buffer is divided into two parts: a transfer data buffer that stores transfer data and a control information buffer that stores control information. A determination circuit is provided which determines whether the data received by the receiving circuit is transfer data or control information based on an added parameter signal and stores the data in each buffer according to the determination. 1. A receiving device for a data processing device, comprising a flag memory that holds a flag indicating whether or not corresponding control information has been received and stored immediately before transferred data.