JPH0334045B2 - - Google Patents
Info
- Publication number
- JPH0334045B2 JPH0334045B2 JP57216318A JP21631882A JPH0334045B2 JP H0334045 B2 JPH0334045 B2 JP H0334045B2 JP 57216318 A JP57216318 A JP 57216318A JP 21631882 A JP21631882 A JP 21631882A JP H0334045 B2 JPH0334045 B2 JP H0334045B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- transparent conductive
- metal
- bar
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 57
- 239000000758 substrate Substances 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000004973 liquid crystal related substance Substances 0.000 claims description 19
- 239000010409 thin film Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000007743 anodising Methods 0.000 claims 1
- 239000011159 matrix material Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 238000007740 vapor deposition Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910006404 SnO 2 Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000010407 anodic oxide Substances 0.000 description 3
- 238000002048 anodisation reaction Methods 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000007738 vacuum evaporation Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 210000002858 crystal cell Anatomy 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003792 electrolyte Substances 0.000 description 2
- 239000008151 electrolyte solution Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000007733 ion plating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- -1 Si 3 N 4 Inorganic materials 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 150000003346 selenoethers Chemical class 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- WYXIGTJNYDDFFH-UHFFFAOYSA-Q triazanium;borate Chemical compound [NH4+].[NH4+].[NH4+].[O-]B([O-])[O-] WYXIGTJNYDDFFH-UHFFFAOYSA-Q 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Landscapes
- Physics & Mathematics (AREA)
- Liquid Crystal (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
Description
【発明の詳細な説明】
＜技術分野＞
本発明は各画素にスイツチング素子として薄膜
トランジスタ（Thin Film Transistor、以下
TFTと略す）を配置したマトリツクス型液晶表
示装置の製造技術に関するものである。[Detailed Description of the Invention] <Technical Field> The present invention uses a thin film transistor (hereinafter referred to as a thin film transistor) as a switching element in each pixel.
The present invention relates to manufacturing technology for matrix-type liquid crystal display devices (abbreviated as TFT).
＜従来技術＞
薄膜トランジスタは、近年、EL素子や液晶等
を用いる表示装置のスイツチング素子としてその
応用が検討されている。しかし、本来の半導体デ
バイスに比べて特性が劣りまた信頼性も低いた
め、未だ実用するには至つていない。<Prior Art> In recent years, the application of thin film transistors as switching elements for display devices using EL elements, liquid crystals, etc. is being considered. However, they have inferior characteristics and low reliability compared to original semiconductor devices, so they have not yet been put into practical use.
一般に、TFTは第１図に示すような構造であ
る。１は絶縁基板、２はベースコート、３はゲー
ト電極、４はゲート絶縁膜、５，６は電極でソー
ス、ドレインに対応する。７はチヤネルを形成す
る半導体層である。 Generally, a TFT has a structure as shown in FIG. 1 is an insulating substrate, 2 is a base coat, 3 is a gate electrode, 4 is a gate insulating film, and 5 and 6 are electrodes corresponding to a source and a drain. 7 is a semiconductor layer forming a channel.
絶縁基板１にはセラミツクやガラスが用いられ
る。ベースコート２は、下地をなめらかな表面に
すること及び絶縁基板１から素子部へ汚染物質又
は不純物イオンが拡散するのを阻止するために設
けられ、SiO2、Si3N4、Al2O3やTa2O5などが使
われる。ゲート電極３は金属たとえばAu、Cr、
AlあるいはTaなどで蒸着によつて形成される。
ゲート絶縁膜４としては、たとえばSiO、SiO2、
Al2O3、Ta2O5等が真空蒸着、CVDあるいは陽極
酸化法等によつて形成される。特に、絶縁性が良
好なことから、Al2O3やTa2O5等の陽極酸化膜が
広く用いられる。半導体７は、例えばａ−Si（ア
モルフアスシリコン）、Ｐ−Si（多結晶シリコン）、
CdS、CdSe、Te等の一つを成分とし、真空蒸
着、イオンプレーテイング、スパツタリング、グ
ロー放電等の種々の方法で形成される。電極５，
６は例えばNi、Cr、Auなどの金属の蒸着等で形
成される。 Ceramic or glass is used for the insulating substrate 1. The base coat 2 is provided to make the underlying surface smooth and to prevent contaminants or impurity ions from diffusing from the insulating substrate 1 to the element portion, and is made of SiO 2 , Si 3 N 4 , Al 2 O 3 , etc. Ta 2 O 5 etc. are used. The gate electrode 3 is made of metal such as Au, Cr,
It is formed by vapor deposition of Al or Ta.
As the gate insulating film 4, for example, SiO, SiO 2 ,
Al 2 O 3 , Ta 2 O 5 , etc. are formed by vacuum evaporation, CVD, anodic oxidation, or the like. In particular, anodic oxide films such as Al 2 O 3 and Ta 2 O 5 are widely used because of their good insulation properties. The semiconductor 7 is, for example, a-Si (amorphous silicon), P-Si (polycrystalline silicon),
It contains one of CdS, CdSe, Te, etc. as a component and is formed by various methods such as vacuum evaporation, ion plating, sputtering, and glow discharge. electrode 5,
6 is formed, for example, by vapor deposition of a metal such as Ni, Cr, or Au.
TFTの動作は電界効果トランジスタと同じで、
ソース電極５とドレイン電極６間で半導体７中に
流れる電流をゲート電極３に印加する電圧で制御
する。 The operation of TFT is the same as that of field effect transistor.
The current flowing in the semiconductor 7 between the source electrode 5 and the drain electrode 6 is controlled by the voltage applied to the gate electrode 3.
このようなTFTは、その特徴として、ガラス
基板上に真空蒸着、スパツタリング、CVD等の
確立された技術により比較的容易に形成すること
ができ、前述の表示装置に適用した場合に表示面
の大形化を達成することができると期待される。 A characteristic of such TFTs is that they can be formed relatively easily on glass substrates using established techniques such as vacuum evaporation, sputtering, and CVD. It is hoped that this will be possible.
上述の材料でTFTを形成し、例えばTN−
FEM（ツイストネマテイツク電界効果）型のマト
リツクス型液晶表示装置の各画素にスイツチング
素子として配置した場合、ゲート・バー及びソー
ス・バーもそれぞれゲート電極及びソース電極と
同じ金属材料を用いると、各画素の周囲に金属の
枠が現われ、表示が暗くなると同時に視角によつ
てはそれぞれのバーの反射のために表示品位を著
しく低下させることになり、スイツチング素子を
具備することによる利点よりも逆にこの点での欠
点が目立つ結果になる。その対策としてTFTの
電極の部分のみに金属を用い、ゲート・バー及び
ソース・バーに透明導電膜を用いれば上述の欠点
を解消することができる。TFTを用いたマトリ
ツクス型液晶表示装置において、ゲートバー及び
ソースバーを透明導電膜で形成する方式について
は特願昭57−152013号（特開昭59−42584号）に
て出願されている。 Form a TFT with the above-mentioned materials, e.g. TN-
When disposed as a switching element in each pixel of an FEM (twisted nematic field effect) type matrix liquid crystal display device, if the gate bar and source bar are made of the same metal material as the gate electrode and source electrode, respectively, each pixel A metal frame appears around the bar, which darkens the display and at the same time, depending on the viewing angle, the display quality can be significantly degraded due to the reflection of each bar. This results in noticeable defects in points. As a countermeasure, the above-mentioned drawbacks can be overcome by using metal only for the electrode portion of the TFT and using a transparent conductive film for the gate bar and source bar. A method of forming gate bars and source bars with transparent conductive films in a matrix type liquid crystal display device using TFT has been filed in Japanese Patent Application No. 57-152013 (Japanese Unexamined Patent Publication No. 59-42584).
第２図はゲートバー及びソースバーをそれぞれ
透明導電膜で形成したマトリツクス型液晶表示装
置の薄膜トランジスタ及びその周辺部の拡大構成
図である。透明導電膜から成るゲート・バー８と
ソース・バー９で行及び列方向の電極ラインを構
成し、ゲート・バー８にゲート電極１０を連結し
てこの上にゲート絶縁膜１１を介してTFTの半
導体層１２を堆積し、更にソース・ドレイン電極
１３を形成するとともにソース電極とソース・バ
ー９を連結しドレイン電極と表示の絵素電極１４
を連結することによりTFTの基板が構成されて
いる。TFTの動作に応答して絵素電極１４に印
加される電圧によりドツトマトリツクス表示が実
行される。以下、従来の方式に即して第２図に示
すゲート・バーとソース・バーをそれぞれ透明導
電膜で形成したTFT及びマトリツクス型液晶表
示装置の製造方法について説明する。 FIG. 2 is an enlarged configuration diagram of a thin film transistor and its peripheral portion of a matrix type liquid crystal display device in which a gate bar and a source bar are each formed of a transparent conductive film. A gate bar 8 and a source bar 9 made of a transparent conductive film constitute electrode lines in the row and column directions, and a gate electrode 10 is connected to the gate bar 8, and a TFT is connected thereon via a gate insulating film 11. A semiconductor layer 12 is deposited, and a source/drain electrode 13 is further formed, and the source electrode and the source bar 9 are connected to form a drain electrode and a pixel electrode 14 for display.
The TFT substrate is constructed by connecting the two. A dot matrix display is performed by the voltage applied to the picture element electrode 14 in response to the operation of the TFT. Hereinafter, a method of manufacturing a TFT and matrix type liquid crystal display device in which the gate bar and source bar shown in FIG. 2 are each formed of a transparent conductive film will be explained in accordance with the conventional method.
第３図は薄膜トランジスタ部の各製作工程を示
す断面図である。まずガラス等の絶縁基板１５上
にベースコート１６を施し、その上にITO（In2O3
＋SnO2）、SnO2等の透明導電膜１７を蒸着やス
パツタ等で500〜2000Å程度の厚さに付着し、こ
の透明導電膜上に有機感光性材料により所望形状
のマスクパターンを形成した後、不要部分をエツ
チングすることによりゲート・バーが形成される
（第３図Ａ）。次に陽極酸化されるべき金属、例え
ばAl、Ta等を蒸着、スパツタやイオンプレーテ
イング等で1000〜2000Å程度付け、ゲート・バー
上に薄膜トランジスタ部となる領域を残し、不要
となる領域をウエツト・エツチングあるいはドラ
イ・エツチングにより除去してゲートのパツド１
８を形成する（第３図Ｂ）。上記基板上に基板と
の密着性に優れかつ耐圧の大きいホトレジスト１
９（例えばポジタイプのホトレジストとしてシプ
レイフアーイースト社のAZ−1350、AZ−1470、
AZ−1470Zや1300−37タイプ、メルク社の
Selectilux Ｎ、コダツク社のKMPR−809等があ
り、ネガタイプのレジストとして東京応化の
OMR−83や感光性ポリイミド前駆体である東レ
のフオトニースUR3100、メルク社のSelectilux
HTR等の如く各種商品名のものが市販されてい
る。）を塗布し、ゲート電極上の所望の部分に開
口部を設けるようにしたマスクパターンを形成す
る（第３図Ｃ）。上記開口部のゲート電極の金属
をホウ酸アンモニウム水溶液、リン酸、クエン酸
等の電解液中にて電圧値約50〜200V程度で陽極
酸化し、膜厚500〜2000Åの絶縁膜を形成してこ
の膜をゲート絶縁膜２０とする（第３図Ｄ）。ゲ
ート絶縁膜２０を形成した後、レジスト膜を剥離
液や有機溶剤で除去する（第３図Ｅ）。半導体膜
２１とソース・ドレイン電極２２，２３をそれぞ
れ膜付着とエツチングやリフトオフ等によつてパ
ターン化する。また第３図Ａにて形成された透明
導電膜のソース・バー（図示せず）とソース電極
を連結する（第３図Ｆ）。 FIG. 3 is a cross-sectional view showing each manufacturing process of the thin film transistor section. First, a base coat 16 is applied on an insulating substrate 15 such as glass, and ITO (In 2 O 3
After depositing a transparent conductive film 17 such as +SnO 2 ) or SnO 2 to a thickness of about 500 to 2000 Å by vapor deposition or sputtering, and forming a mask pattern of a desired shape using an organic photosensitive material on this transparent conductive film, Gate bars are formed by etching away unnecessary portions (FIG. 3A). Next, a metal to be anodized, such as Al, Ta, etc., is deposited to a thickness of about 1000 to 2000 Å by sputtering or ion plating, leaving an area on the gate bar that will become the thin film transistor part, and wetting the unnecessary area. Gate pad 1 is removed by etching or dry etching.
8 (Figure 3B). A photoresist 1 with excellent adhesion to the substrate and high withstand voltage is placed on the above substrate.
9 (For example, as a positive type photoresist, Shipley Far East Co., Ltd.'s AZ-1350, AZ-1470,
AZ-1470Z and 1300-37 types, Merck's
There are Selectilux N, Kodatsuk's KMPR-809, etc., and Tokyo Ohka's negative type resist.
OMR-83, Toray's Photonice UR3100, a photosensitive polyimide precursor, and Merck's Selectilux
Various product names such as HTR etc. are commercially available. ) to form a mask pattern in which an opening is provided at a desired portion on the gate electrode (FIG. 3C). The metal of the gate electrode in the opening is anodized in an electrolytic solution such as ammonium borate solution, phosphoric acid, citric acid, etc. at a voltage of about 50 to 200 V to form an insulating film with a thickness of 500 to 2000 Å. This film is used as the gate insulating film 20 (FIG. 3D). After forming the gate insulating film 20, the resist film is removed using a stripping solution or an organic solvent (FIG. 3E). The semiconductor film 21 and source/drain electrodes 22 and 23 are patterned by film deposition, etching, lift-off, etc., respectively. Further, the source bar (not shown) of the transparent conductive film formed in FIG. 3A is connected to the source electrode (FIG. 3F).
以上の工程により薄膜トランジスタが形成され
る。 A thin film transistor is formed through the above steps.
次に上記薄膜トランジスタを保護するために
Si3N4、SiO2または配向膜を兼用した有機膜等を
CVD法、プラズマCVD法、蒸着法または塗布法
等により形成し、ラビングまたは斜方蒸着法等に
よる配向処理を行なつた後、対向基板とシール材
を介して貼り合わせることにより液晶セルが形成
される。この液晶セルに液晶を注入し、注入口を
封止してマトリツクス型液晶表示装置が作製され
る。 Next, to protect the thin film transistor above
Si 3 N 4 , SiO 2 or an organic film that also serves as an alignment film, etc.
A liquid crystal cell is formed by forming by CVD method, plasma CVD method, vapor deposition method, coating method, etc., and after performing alignment treatment by rubbing or oblique vapor deposition method, etc., it is bonded to a counter substrate via a sealing material. Ru. A matrix type liquid crystal display device is manufactured by injecting liquid crystal into this liquid crystal cell and sealing the injection port.
次にゲート電極の金属とゲート・パツドの透明
導電膜を連結する他の従来方式について第４図を
参照しながら説明する。基板２４上にベースコー
ト２５を施し、その上に透明導電膜を付けたのち
ゲート・バー２６及びソース・バー（図示せず）
となるべきパターンをホトレジストによりパター
ン化し透明導電膜をエツチングする（第４図Ａ）。
この場合、第３図の例と異なり、ゲート絶縁膜が
形成される部分には透明導電膜は存在しない。次
に陽極酸化されるべき金属を付けた後エツチング
によりパターン化し、透明導電膜で形成したゲー
ト・バー２６間に架設することによりゲート電極
２７とし、ゲート電極２７とゲート・バー２６を
連結させる（第４図Ｂ）。次に陽極酸化する領域
以外の部分をレジスト２８でマスクして陽極酸化
処理し、ゲート絶縁膜２９を形成する（第４図
Ｃ，Ｄ）。レジスト２８を剥離し、ゲート電極２
７、ゲート絶縁膜２９及びゲート・バー２６の形
成が完了する（第４図Ｅ）。半導体層３０、ソー
ス電極３１及びドレイン電極３２を形成し、薄膜
トランジスタが形成される（第４図Ｆ）。以後の
工程は前述した通りである。この方式ではゲート
絶縁膜の下に透明導電膜がなく、これによつて、
陽極酸化時に陽極酸化される金属のピンホールに
よる透明導電膜を電解液との接触に起因する酸素
発生とそれに伴う化成膜の損傷は免れる。しかし
ながら、透明導電膜上のマスクのレジストにピン
ホールがあるかあるいは陽極酸化時の電圧に対し
てレジストの一部分に弱い部分があれば、レジス
トが絶縁破壊を起し、電解液と下の透明導電膜と
が接触して短絡するため陽極酸化膜の成長に支障
をきたす場合がある。 Next, another conventional method for connecting the metal of the gate electrode and the transparent conductive film of the gate pad will be described with reference to FIG. After applying a base coat 25 on the substrate 24 and attaching a transparent conductive film thereon, a gate bar 26 and a source bar (not shown) are applied.
A pattern to be formed is formed using photoresist, and the transparent conductive film is etched (FIG. 4A).
In this case, unlike the example shown in FIG. 3, there is no transparent conductive film in the area where the gate insulating film is formed. Next, after applying the metal to be anodized, it is patterned by etching and is installed between the gate bars 26 formed of a transparent conductive film to form the gate electrode 27, and the gate electrode 27 and the gate bar 26 are connected ( Figure 4B). Next, a portion other than the area to be anodized is masked with a resist 28 and anodized, thereby forming a gate insulating film 29 (FIGS. 4C and 4D). The resist 28 is peeled off and the gate electrode 2 is removed.
7. Formation of gate insulating film 29 and gate bar 26 is completed (FIG. 4E). A semiconductor layer 30, a source electrode 31, and a drain electrode 32 are formed to form a thin film transistor (FIG. 4F). The subsequent steps are as described above. In this method, there is no transparent conductive film under the gate insulating film, so
Oxygen generation caused by contact of the transparent conductive film with the electrolytic solution due to pinholes in the anodized metal during anodization and the resulting damage to the chemically formed film are avoided. However, if there are pinholes in the resist of the mask on the transparent conductive film or parts of the resist are weak against the voltage during anodic oxidation, the resist will cause dielectric breakdown and the electrolyte and the transparent conductor underneath will Contact with the film may cause a short circuit, which may hinder the growth of the anodic oxide film.
＜発明の目的＞
本発明は上記TFTを有する液晶表示装置に於
いて、特にゲート電極に陽極酸化可能な金属、ゲ
ートバーに透明導電膜を用いたTFTを基板上に
形成し、マトリツクス型液晶表示装置を作製する
製造技術を提供することを目的とするものであ
る。<Object of the Invention> The present invention relates to a liquid crystal display device having the above TFT, in particular a matrix type liquid crystal display device in which a TFT using a metal that can be anodized for the gate electrode and a transparent conductive film for the gate bar is formed on a substrate. The purpose of this research is to provide a manufacturing technology for producing .
＜実施例＞
第５図は本発明の一実施例を説明するTFT基
板の製造工程図であり、Ａ乃至Ｈは断面図、
A′乃至H′はそれぞれ対応する平面図である。ベ
ースコートを施した基板３３上に陽極酸化可能な
金属を付け、エツチングによりゲート・バー３４
を形成する（第５図Ａ，A′）。次にゲート・バー
３４上のゲート絶縁膜となる領域以外の部分をホ
トレジスト３５でマスクする（第５図Ｂ，B′）。
露出しているゲート・バー３４の陽極酸化を行な
つて厚さ500〜3000Å程度のゲート絶縁膜３６を
形成する（第５図Ｃ，C′）。次にマスクのホトレ
ジストを剥離液または有機溶剤で取り除く（第５
図Ｄ，D′）。ゲート・バー３４の陽極酸化した部
分及びその両端の陽極酸化されていない金属のう
ち、後に形成される透明導電膜のゲート・バーと
連結するために必要な部分をホトレジスト３７で
マスクする（第５図Ｅ，E′）。マスクされた部分
以外のゲート・バー３４をエツチングで除去した
後、ホトレジスト３７を取り除く（第５図Ｆ，
F′）。この上にITO、SnO2等の透明導電膜３８を
蒸着法あるいはスパツタリング法等で堆積する
（第５図Ｇ，G′）。透明導電膜３８をホトレジス
トでマスクした後、エツチングすることによりパ
ターン化しゲート・バーとする。ゲート・バーは
金属部と透明導電膜とが重なつた状態で連結され
る（第５図Ｈ，H′）。以後の工程は前述した如く
であり、ゲート絶縁膜３６上に硫化物、セレン化
物、Te、アモルフアスシリコン、多結晶シリコ
ン等の半導体層を堆積した後、ソース電極及びド
レイン電極を形成し、TFTとする。TFTの基板
への配置は第２図と同様な構成とし、これを液晶
表示装置のセル基板の一方としてこのTFT基板
に対向基板を接着し、その間隙にツイストネマテ
イツク構造等の液晶層を注入する。TFTを動作
させるとともに液晶層の電気光学効果を利用する
ことによりドツトマトリツクス型の表示を実行す
ることができる。従来では金属のゲート電極と透
明導電膜のゲート・バーを形成したのちに陽極酸
化を行なつたが、本実施例では金属でバーを形成
し、必要部分を陽極酸化したのち、不要な部分を
エツチングで取り除き透明導電膜のゲート・バー
を形成する。従つて、マスクのレジストにピンホ
ールが生じて陽極酸化時に電解液がレジスト中に
滲みこんでも、接触するのは陽極酸化可能な金属
であるのでその部分は直ちに陽極酸化されて絶縁
膜となりカバーされるため本来の陽極酸化膜の成
長に支障をきたさない。またピンホール部の絶縁
膜は面積が小さいのでのちの不要金属部のエツチ
ング時にリフトオフされ、工程の歩留りの点でも
本実施例の製造方法は優れた結果を得ることがで
きる。<Example> FIG. 5 is a manufacturing process diagram of a TFT substrate explaining an example of the present invention, A to H are cross-sectional views,
A' to H' are respectively corresponding plan views. A metal that can be anodized is attached on the base coated substrate 33, and gate bars 34 are formed by etching.
(Fig. 5 A, A'). Next, a portion of the gate bar 34 other than the region that will become the gate insulating film is masked with a photoresist 35 (FIGS. 5B and B').
The exposed gate bar 34 is anodized to form a gate insulating film 36 having a thickness of about 500 to 3000 Å (FIGS. 5C and C'). Next, remove the photoresist on the mask with a stripper or organic solvent (step 5).
Figures D, D'). Of the anodized portion of the gate bar 34 and the non-anodized metal at both ends thereof, the portion necessary for connection with the gate bar of the transparent conductive film to be formed later is masked with a photoresist 37 (fifth Figures E, E′). After removing the gate bar 34 other than the masked portion by etching, the photoresist 37 is removed (FIG. 5F,
F′). A transparent conductive film 38 of ITO, SnO 2 or the like is deposited thereon by vapor deposition or sputtering (FIGS. 5G and G'). After masking the transparent conductive film 38 with photoresist, it is patterned into gate bars by etching. The gate bar is connected with the metal part and the transparent conductive film in an overlapping state (FIG. 5 H, H'). The subsequent steps are as described above, and after depositing a semiconductor layer of sulfide, selenide, Te, amorphous silicon, polycrystalline silicon, etc. on the gate insulating film 36, a source electrode and a drain electrode are formed, and a TFT is formed. shall be. The arrangement of the TFT on the substrate is similar to that shown in Figure 2, and this is used as one of the cell substrates of a liquid crystal display device.A counter substrate is bonded to this TFT substrate, and a liquid crystal layer such as a twisted nematic structure is injected into the gap. do. By operating the TFT and utilizing the electro-optic effect of the liquid crystal layer, dot matrix type display can be performed. In the past, anodic oxidation was performed after forming a metal gate electrode and a transparent conductive film gate bar, but in this example, a metal bar is formed, the necessary parts are anodized, and the unnecessary parts are anodized. It is removed by etching to form gate bars of transparent conductive film. Therefore, even if a pinhole occurs in the resist of the mask and the electrolyte seeps into the resist during anodization, the contact is made with a metal that can be anodized, so the area is immediately anodized and covered with an insulating film. Therefore, it does not interfere with the growth of the original anodic oxide film. Further, since the area of the insulating film in the pinhole portion is small, it is lifted off later when unnecessary metal portions are etched, and the manufacturing method of this embodiment can achieve excellent results in terms of process yield.
＜発明の効果＞
以上詳述した製造方法でバーの部分を透明導電
膜にしてマトリツクス型液晶表示装置を製作した
ところ、薄膜トランジスタ自体は安定な電気的特
性が再現性良く得られ、その上に表示装置として
もTN−FEMのみならずゲストホスト型や反射
型、透過型のいかなる表示モードに対しても表示
面の「見え」を損うことなく高コントラストの表
示が可能になり、TFTを備えたことによる利点
を大いに発揮することができる。また、透明導電
膜の陽極酸化時に陽極酸化される金属のピンホー
ルに起因する酸素発生や化成膜の損傷を回避する
こともできる。<Effects of the Invention> When a matrix type liquid crystal display device was manufactured using the manufacturing method described in detail above by using a transparent conductive film in the bar portion, the thin film transistor itself had stable electrical characteristics with good reproducibility, and the thin film transistor itself had stable electrical characteristics with good reproducibility. As a device, it is possible to display high contrast not only in TN-FEM but also in any display mode such as guest-host type, reflective type, and transmissive type without impairing the "visibility" of the display surface, and it is equipped with TFT. You can take full advantage of the benefits of this. Further, it is also possible to avoid oxygen generation and damage to the chemically formed film due to pinholes in the metal that is anodized during anodization of the transparent conductive film.
第１図はTFTの一般的な構造の１例を示す断
面図である。第２図はマトリツクス型液晶表示装
置のTFT及びその周辺部の拡大構成図である。
第３図及び第４図はそれぞれ従来のTFTの各製
作工程を示す断面図である。
第５図は本発明の一実施例を説明するTFT基
板の製造工程図である。
３３……基板、３４……ゲート・バー、３６…
…ゲート絶縁膜、３８……透明導電膜。
FIG. 1 is a sectional view showing an example of a general structure of a TFT. FIG. 2 is an enlarged configuration diagram of the TFT and its surrounding area of a matrix type liquid crystal display device.
FIGS. 3 and 4 are cross-sectional views showing each manufacturing process of a conventional TFT. FIG. 5 is a manufacturing process diagram of a TFT substrate explaining one embodiment of the present invention. 33...Substrate, 34...Gate bar, 36...
...Gate insulating film, 38...Transparent conductive film.
Claims (1)
陽極酸化してゲート絶縁膜を形成した後、ゲート
電極領域以外の前記金属を除去し、残存する前記
金属の陽極酸化されない両端部と電気的に接続さ
れる透明導電膜を堆積してゲート電極ラインを形
成し、前記ゲート絶縁膜上には薄膜トランジスタ
を構成するとともに前記基板を一方のセル基板と
して液晶表示セルを作製することを特徴とする液
晶表示装置の製造方法。1 After anodizing the metal that will become the gate electrode formed on the substrate to form a gate insulating film, remove the metal other than the gate electrode area, and connect electrically with both ends of the remaining metal that are not anodized. A liquid crystal display characterized in that a transparent conductive film to be connected is deposited to form a gate electrode line, a thin film transistor is formed on the gate insulating film, and a liquid crystal display cell is manufactured using the substrate as one cell substrate. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57216318A JPS59105617A (en) | 1982-12-08 | 1982-12-08 | Production of liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57216318A JPS59105617A (en) | 1982-12-08 | 1982-12-08 | Production of liquid crystal display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59105617A JPS59105617A (en) | 1984-06-19 |
| JPH0334045B2 true JPH0334045B2 (en) | 1991-05-21 |
Family
ID=16686644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57216318A Granted JPS59105617A (en) | 1982-12-08 | 1982-12-08 | Production of liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59105617A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012067053A1 (en) | 2010-11-18 | 2012-05-24 | 帝人ファイバー株式会社 | Fabric and clothing |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2620240B2 (en) * | 1987-06-10 | 1997-06-11 | 株式会社日立製作所 | Liquid crystal display |
| JPH01219721A (en) * | 1988-02-19 | 1989-09-01 | Internatl Business Mach Corp <Ibm> | Metal insulator construction and liquid crystal display device |
| US6713783B1 (en) | 1991-03-15 | 2004-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Compensating electro-optical device including thin film transistors |
| JP3172841B2 (en) * | 1992-02-19 | 2001-06-04 | 株式会社日立製作所 | Thin film transistor, method of manufacturing the same, and liquid crystal display device |
| KR100659710B1 (en) * | 2003-11-29 | 2006-12-21 | 삼성에스디아이 주식회사 | Light emitting display device and display panel |
-
1982
- 1982-12-08 JP JP57216318A patent/JPS59105617A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012067053A1 (en) | 2010-11-18 | 2012-05-24 | 帝人ファイバー株式会社 | Fabric and clothing |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59105617A (en) | 1984-06-19 |
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