JPH0334071A - Logic simulator - Google Patents

Abstract

PURPOSE:To increase the executing speed of the logic simulation by using hardware to carry out the simulation of the logic described in a language. CONSTITUTION:An input data setting memory 10 is prepared to store the input value of a described sentence together with a described sentence identification memory 20 which identifies each described sentence, an input change described sentence identification memory 30 which can identify the described sentence whose input value is changed, a language evaluation circuit 40 which evaluates a language with input of the output of the memory 10 and the output of the memory 20, an output data store memory 50 which stores the result of the circuit 40, a changing signal sequencing circuit 60 which sequences the output changing signals of the evaluation result one by one, and a described sentence connection memory 70 which stores the connection goals of described sentences. Then the simulation of the logic described in a language is carried out with use of hardware. As a result, the executing speed of the logic simulation is increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logic simulator, and particularly to a logic simulator that realizes a simulation of a functional description language using hardware.

[Conventional technology]

Conventionally, this type of logic simulator has been mainly realized by software, and recently some have started to be realized by firmware/hardware, but these are limited to the gate level.(2) 8imulator for Large Di
digitalSystem LogicVerif
cation.

17th DA 0onf, pp, 626~
633 (1980).

``OAI!: 5tation's simula
tors tacklel m1llion g
ates'' Electron, Des,.

Halation llingine: Introd
uction.

Proc, 19th DA Col/f,,
PI), 51-54 (1982).

[Problem to be solved by the invention]

Since the above-mentioned conventional language (function) level logic simulator is realized by 7 software, the simulation process involves sequential processing of each descriptive statement (function operator), which takes a long time to execute. In particular, there is a problem in that the simulation time required when large-scale logic circuits are described in language is enormous.

The present invention aims to solve the above-mentioned problems of the conventional technology, and provides a logic simulator that realizes the simulation of logic written in a language using hardware and has an increased simulation execution speed.

[Means to solve the problem]

The logic simulator of the present invention includes a storage means for storing input values of a language (sentence) describing a simulation model, a storage means for identifying individual descriptive sentences in which the model is described, A storage means capable of identifying a descriptive sentence whose value has changed, a language evaluation means that receives the identifier and input value of the descriptive sentence, performs a language evaluation (simulation), and returns an output result, and a memory in which the evaluation result is stored. means for comparing the newly evaluated results with the old results and ordering the changed signals one by one; and storage means for storing the connection destinations of the descriptive sentences.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

10 is an input data setting memory in which input values of descriptive sentences are stored; 20 is a descriptive sentence identification memory for identifying individual descriptive sentences;
30 is a language evaluation circuit that evaluates the language by inputting the output of the memory 20 in which the input value has changed; 50 is the language evaluation circuit 40
60 is a change signal ordering circuit that orders the output change signals of the evaluation results one by one; 70 is a descriptive sentence connection memory that stores the connection destinations of descriptive sentences; 80 to 88 is a signal line connecting each part.

FIG. 2 is a configuration diagram of an example of the language evaluation circuit 4o in FIG. 1.

110 is an input/output data setting memory (CAM) for descriptive sentences in which language identifiers, input values, and evaluation results are stored; 120
130 is a microroutine memory (AS) in which a microprogramming execution routine is stored, and 130 is an old data storage memory (D) such as a memory element or register element.
M).

140 is a model storage memo in which sentences written in a language are stored in the form of instruction codes! , l(IM).

150 is an arithmetic circuit that evaluates the language, 160 is a control circuit that controls all of these, 170 is a data path to each memory and circuit, 180 is an address bus, and 190 is a control signal line.

FIG. 5 is an example of a logic circuit described using language. (
(a) shows a part of the language description, (b) shows the circuit diagram corresponding to the language, and (C) shows the instruction codes used when the language description is executed in comparison with each description. .

FIG. 4 combines FIGS. 1 and 2 to show how the descriptive text shown in FIG. 5 is evaluated.

The operation of the present invention will be explained with reference to these figures.

It is assumed that necessary data is stored in each memory in the simulator before simulation execution begins. In this example, the input data setting memory 10 contains the descriptive text [,I
The input value of f, ie.

The values of A, B, and C, and the values of D and ADR are 2. The descriptive sentence identification memory 20 has a descriptive sentence 1. The identifier of II is 2,0 . . . for descriptive sentence l. 9,2 is entered for the descriptive sentence ■. In the input change description sentence identification memory 50, “1n” is set for the input signal change of the description sentence. In this example, “1#” is set for the description sentence I in the initial state, and @ is set for the description sentence ■. On
is assumed to be standing. Output data is added and sent.

(5) When the signal change of D is sent, the input value of the description ■ in the input data setting memory 10 is “
It is rewritten from 0" to "1". At the same time, the n+4 address of the input change description identification memory 50 is rewritten from "0" to "1" to notify the change in the human input signal.

This completes the simulation of descriptive sentence I.

Next, the descriptive sentence (■) is similarly executed as follows.

(1) Read data from address n+4 and send it to human output data setting memo IJ (CM) 110.

Since the descriptive sentence ■ is a memory sentence, not only the identifier of the descriptive sentence but also the memory start address is sent at the same time. This pattern is shown at 110゛. Descriptive sentence ■ checks the value of D, and
="1", 1 word 1 from the address indicated by ADR
This is an instruction to read 6 bits. Memory Mi; 11.1
In 024wx16 bits, the read value becomes the output of M.

(2) When an execution command comes, the identifier of the model storage memory (engineering M) 140 is taken out, the model storage memory (engineering M) 140 is read, and the value of D is taken into the control circuit 160 in the same way as in the description I. .

Next, execute the next instruction (TRN 1 ) in the model storage memory J (IM) 1400 and jump to the next address in the model storage memory (IM) 140.

Check if it is finished. In this example, D-"1", so the next command sets ADH to input/output data setting memory (CM) 11.
It is taken into the zero-work control circuit 160. Next, the RAT instruction is read, and based on the RAT execution routine in the microroutine memory (AS) 120, ADH=mth data (
In this example, 0FIF) is read out and incorporated into the control circuit 160. Finally, the KX Engineering T command is executed and the read result is stored in the input/output data setting memo IJ (CM) 110.

(3) The subsequent processing is performed in the same way as the descriptive sentence [.

As described above, language evaluation is performed using this simulator.

〔Effect of the invention〕

As explained above, the present invention includes a storage means for storing input values of descriptive sentences, a storage means for identifying individual descriptive sentences, a storage means for identifying descriptive sentences whose input values have changed, and a language evaluation method. and the means to do so.

Storage means for storing the evaluation results; and means for ordering the output change signals of the evaluation results one by one.

By combining this method with a storage means that stores the connection destinations of written statements, it is possible to realize a simulation of logic written in a language using hardware, thereby increasing the speed of simulation execution.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the logic simulator of the present invention, Fig. 2 is a block diagram of an example of the language evaluation circuit in Fig. 1, and Figs. FIG. 2 is a diagram showing a description example, a corresponding circuit diagram, and an example of an instruction code;
FIG. 4 is a diagram showing the execution process of FIG. 5. Explanation of symbols: 10...Manual data setting memory. 20... Descriptive sentence identification memory, 50... Input change descriptive sentence identification memory, 40... Language evaluation circuit, 50... Output data storage memory, 60... Change signal ordering circuit,
70... Connection memory for descriptive text, 80 to 88 signal lines, 1
10...Input/output data setting method (DM) for descriptive text, 14
0...Memory for storing models (engineering M). 150... Arithmetic circuit, 160... Control circuit, 170
... data bus, 180 ... address bus, 190
...Control signal line. (Q) Figure 3

Claims (1)

[Claims] 1. A storage means for storing the input values of statements describing the simulation model, a memory means for identifying individual descriptive statements in which the model is described, and a memory capable of identifying descriptive statements whose input values have changed during logical simulation. a language evaluation means for receiving the identifier and input value of the descriptive sentence, evaluating the language, and returning an output result; a storage means for storing the evaluation result; A logic simulator comprising means for comparing and ordering change signals one by one, and a storage means for storing connection destinations of the descriptive sentences.